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# Sequential Logic

## Latches, Flip-Flops-SR, D, JK & T, realization of FFs

synchronous and asynchronous sequential circuitsState table and state diagrams, State reduction
Shift Registers-SISO, SIPO, PISO,PIPO
Design of counters-Modulo-n, Johnson, Ring,
Up/Down,
Design of Serial Adder, Serial Multiplier, FSM, Mealy
and Moore state machines - State minimization
Sequence detection.
Modeling of above sequential circuits using Verilog

Flip-Flops
Sequential Circuits use flip-flops as storage elements
Flip-Flop is a binary storage device that saves one bit of
information
The outputs can come from flip-flops or combinational logic
Flip-flop inputs come from combinational logic or clock
generators

Latches
Different flip-flops are different based on the number of inputs and how the inputs
affect the binary state.
Basic types of flip-flops operate with signal levels and are called latches.
Example: SR latch

## SR Latches with Control input

S and R are allowed to change the flip-flop only when C = 1.
If C=0, S and R cant change output

D Latch
Want to get rid of the undesirable SR condition where both S and R are 1.

1
1

0
1

1
1

1
0

## Also called a transparent latch

7

D Latch
Want to get rid of the undesirable SR condition where both S and R are 1.

1
1
1

0
1

8

## Graphic symbols for Latches

FLIP-FLOPS
Many flip-flops are edge triggered: They respond to the input only during
transition from 0 to 1 or from 1 to 0.

10

Edge-Triggered D Flip-Flop
The output can change only when clock goes from 1 to 0.

## Data blocked here while CLK =1

1

11

Edge-Triggered D Flip-Flop
The output can change only when clock goes from 1 to 0.

## Data passes here while CLK =0

1

12

Graphic Symbols

13

Other Flip-Flops
Each flip-flop is made of interconnection of gates.
The edge-triggered D flip-flop is the most efficient flipflop since it requires the least number of gates.
Other flip-flops are made using the D flip-flop and extra
logic.
Two flip-flops widely used are the JK and T flip-flop.

14

What is a JK Flip-flop?
A flip-flop is a circuit that has two stable states
and can be used to store state information.
The flip-flop can be made to change state by
signals applied to one or more control inputs
and will have one or two outputs.

JK Terminology/Structure
Has 5 inputs named:
J(set),K(reset), PR, CLR, and CLK
Has 2 outputs: Q and Q

PR = Preset
CLR = Clear
CLK = Clock

## Cleared (reset): when it stores a binary 0

Outputs
The Q output is the primary output.
This means that the binary bit
stored in the flip-flop, 1 or 0, is
the same as Q.
The Q output is the
opposite binary bit value
that is stored in Q.

## The PR and CLR inputs always

override the J,K inputs.

## A low at the CLR input sets Q = 0

Inputs: J and K
The logic states applied to the J and K inputs cause the flipflop to operate 4 different ways.
The way the logic state is applied to J and K is called Mode
of Operation.
The mode of operation refers to the condition of the flipflop as it prepares for the positive clock pulse.

## Four Modes Of Operation

The 4 modes of operation are:
hold, set, reset, toggle

Q(t+1)

Q(t+1)

Mod
e

Hold

Sets

Rese
ts

Togg
le

JK contains an internal
Active Low SR latch.

## Active Low SR Latch

Point to remember:
A 0 at the set or the
reset will either set or
reset the value of Q.

S set

R
reset

Invalid

Invalid

2 Inputs:

3 Inputs:

## Mode of Operation: Hold

Hold: no change in Q.

Orig. Q

Orig. Q

Set: Q = 1.

Orig. Q

Orig. Q

Reset: Q = 0.

Orig. Q

Orig. Q

Toggle: Q = Q.

Orig. Q

Orig. Q

Toggle: Q = Q.

Orig. Q

Orig. Q

## Overview: During a time period

Characteristic Equation
Q

Q(t + 1)

Characteristic Equation:

## If only one slide to remember

Characteristic Equation:
Q(t+1) = J.Q+ K.Q

## Q is the primary output.

Mode

Hold

Sets

Resets

Toggle

SR Latch:
A 0 at the set or the
reset will either set or
reset the value of Q.

JK Flip-Flop
Three flip-flop operations: Set, Reset,
Complement output.
JK performs all three

31

JK Flip-Flop
D = JQ + KQ
if J=1 , K=0 then D=Q+Q=1
if J=0 , K=1 then D=0
if j =1 , K=1 then D = Q

32

T Flip-Flop
T (Toggle) flip-flop is a complementing one.
T flip-flop is obtained from a JK when inputs J and K are tied together.

33

T Flip-Flop
If T=0 ( J=K=0) output does not change.
If T=1 ( J=K=1) output is complemented.
A T flip-flop can also be made of D flip-flop and a XOR.
D = T XOR Q = TQ + TQ

34

Characteristic Tables
JK Flip-flop

J
0
0
1
1

K
0
1
0
1

Q(t+1)
Q(t)
0
1
Q(t)

No change
Reset
Set
Complement
35

Characteristic Tables
D Flip-flop
D
0
1

Q(t+1)
0
Reset
1
Set

T Flip-flop
T
0
1

Q(t+1)
Q(t) No change
Q(t) Complement
36

Introduction: Registers
An n-bit register has a group of n flip-flops and some
logic gates and is capable of storing n bits of
information.

## The flip-flops store the information while the gates

control when and how new information is transferred
into the register.

## Some functions of register:

retrieve data from register
store/load new data into register (serial or parallel)
shift the data within register (left or right)

Introduction: Registers

37

Simple Registers
No external gates.
Example: A 4-bit register. A new 4-bit data is loaded
every clock cycle.
A3

A2

A1

A0

I3

I2

I1

I0

CP

CS1104-13

Simple Registers

38

we may want to control when to load.

register. Requires a load control input.

CS1104-13

39

D Q

A0

D Q

A1

D Q

A2

D Q

A3

I0

I1

I2

I3

CLK
CLEAR
CS1104-13

40

## Using Registers to implement

Sequential Circuits
A sequential circuit may consist of a register
(memory) and a combinational circuit.
Next-state value
Register

Clock

Combinational
circuit

Inputs

Outputs

## The external inputs and present states of the register

determine the next states of the register and the
external outputs, through the combinational circuit.

## The combinational circuit may be implemented by

any of the methods covered in MSI components and
Programmable Logic Devices.
CS1104-13

## Using Registers to implement

Sequential Circuits

41

## Using Registers to implement

Sequential Circuits
Example 1:

## A1+ = S m(4,6) = A1.x'

A2+ = S m(1,2,5,6) = A2.x' + A2'.x = A2 x
y = S m(3,7) = A2.x

Present
state
A1 A2
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1

CS1104-13

Input
x
0
1
0
1
0
1
0
1

Next
State
A1+ A2+
0
0
0
1
0
1
0
0
1
0
0
1
1
1
0
0

Output
y
0
0
0
1
0
0
0
1

A1.x' A
1
A2x
x

## Using Registers to implement

Sequential Circuits

A2
y

42

## Using Registers to implement

Sequential Circuits
Example 2: Repeat example 1, but use a ROM.
1
2
3
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

Outputs
1
2
3
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
0
1

A1
A2
x

8x3
ROM
y

CS1104-13

## Using Registers to implement

Sequential Circuits

43

Shift Registers
Another function of a register, besides storage, is to
provide for data movements.

## Each stage (flip-flop) in a shift register represents

one bit of storage, and the shifting capability of a
register permits the movement of data from stage to
stage within the register, or into or out of the register
upon application of clock pulses.

CS1104-13

Shift Registers

44

Shift Registers
Basic data movement in shift registers (four bits are
used for illustration).
Data in

Data out

Data in

Data out

Data in

Data in
Data out

Data in

Data out

## (d) Serial in/parallel out

Data out

(e) Parallel in /
parallel out
(f) Rotate right
CS1104-13

Shift Registers

45

## Serial In/Serial Out Shift Registers

Accepts data serially one bit at a time and also
produces output serially.

Serial data
input

D Q
C

Q0

D Q
C

Q1

D Q

Q2

D Q

Q3

Serial data
output

CLK

CS1104-13

46

## Serial In/Serial Out Shift Registers

Application: Serial transfer of data from one register
to another.
SI
Clock

Shift register A

SO

SI

Shift register B

SO

CP

Shift control

Clock
Shift
control
CP

CS1104-13

Wordtime

T1

T2

T3

T4

47

## Serial In/Serial Out Shift Registers

Serial-transfer example.
Timing Pulse
Initial value
After T1
After T2
After T3
After T4

CS1104-13

Shift register A
1
1
1
0
1

0
1
1
1
0

1
0
1
1
1

1
1
0
1
1

Shift register B
0
1
1
0
1

0
0
1
1
0

1
0
0
1
1

0
1
0
0
1

## Serial In/Serial Out Shift Registers

Serial output of B
0
1
0
0
1

48

## Serial In/Parallel Out Shift Registers

Accepts data serially.
Outputs of all stages are available simultaneously.
Data input

D Q

D Q

D Q

D Q

CLK
Q0

Data input
CLK

Q1

Q2

Q3

SRG 4

Logic symbol

C
Q0 Q1 Q2 Q3

CS1104-13

Registers

49

## Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.
Data input
D0

D1

D2

D3

D Q
C

Q0

D Q

Q1

D Q
C

Q2

Serial
data
D Q
Q3 out
C

CLK
SHIFT.Q0 + SHIFT'.D1

CS1104-13

Registers

50

## Parallel In/Serial Out Shift Registers

Bits are entered simultaneously, but output is serial.
Data in
D0 D1 D2 D3

CLK

SRG 4
C

Logic symbol

CS1104-13

Registers

51

## Parallel In/Parallel Out Shift Registers

Simultaneous input and output of all data bits.
Parallel data inputs
D0

D1

D2

D3

D Q

D Q

D Q

D Q

CLK
Q0

Q1

Q2

Q3

CS1104-13

Registers

52

## Bidirectional Shift Registers

Data can be shifted either left or right, using a control
line RIGHT/LEFT (or simply RIGHT) to indicate the
direction.
RIGHT/LEFT
Serial
data in

RIGHT.Q0 +
RIGHT'.Q2

D Q

D Q

Q1

D Q
C

Q2

D Q

Q3

Q0
CLK

CS1104-13

53

## Bidirectional Shift Registers

4-bit bidirectional shift register with parallel load.
Parallel outputs

Clear

A4

A3

A2

A1

CLK
s1
s0

Serial
input for
shift-right

CS1104-13

4x1
MUX
3 2 1 0

I4

4x1
MUX
3 2 1 0

I3

4x1
MUX
3 2 1 0

I2

Parallel inputs
Bidirectional Shift Registers

4x1
MUX
3 2 1 0

I1

Serial
input for
shift-left
54

## Bidirectional Shift Registers

4-bit bidirectional shift register with parallel load.
Mode Control
s1
s0
0
0
1
1

CS1104-13

0
1
0
1

Register Operation
No change
Shift right
Shift left

## Bidirectional Shift Registers

55

Most operations in digital computers are done in
parallel. Serial operations are slower but require less
equipment.

## A serial adder is shown below. A A + B.

SI

SO

Shift-right
CP
External input

Shift-register A

x
S
y FA
C
z

SI
Shift-register B

SO
Q D

Clear
CS1104-13

56

A = 0100; B = 0111. A + B = 1011 is stored in A
after 4 clock pulses.

CS1104-13

Initial:

A: 0 1 0 0
B: 0 1 1 1

Q: 0

Step 1: 0 + 1 + 0
S = 1, C = 0

A: 1 0 1 0
B: x 0 1 1

Q: 0

Step 2: 0 + 1 + 0
S = 1, C = 0

A: 1 1 0 1
B: x x 0 1

Q: 0

Step 3: 1 + 1 + 0
S = 0, C = 1

A: 0 1 1 0
B: x x x 0

Q: 1

Step 4: 0 + 0 + 1
S = 1, C = 0

A: 1 0 1 1
B: x x x x

Q: 0

57

clk

qb

## D Flipflop Verilog code

module dff(d,clk,rst,q,qb);
input d,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;

begin
if (rst==0)
temp=d;
else
temp=temp;
q=temp;
qb=~ temp ;
end
end module

rst

pr

Clk

qb

Qb

Qbpreviou
s

## module srff(s,r,clk,rst, q,qb);

input s,r,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]sr;
always@(posedge clk,posedge rst)
begin
sr={s,r};
if(rst==0)
begin
case (sr)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=1'b1;
default: begin end
endcase
end
else
begin
q=1'b0;
end

qb=~q;
end

Rst

Clk

Qb

Previous

state

Qb

No +ve edge -

Previous

state

## JK Flipflop Verilog code

module jkff(j,k,clk,rst, q,qb);
input j,k,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]jk;
always@(posedge clk,posedge rst)
begin
jk={j,k};
if(rst==0)
begin
case (jk)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=~q;
default: begin end
endcase
end
else
q=1'b0;
qb=~q;
end
end module

Edge-Triggered D Flip-Flop

## Same result can be had using a different design that

uses only 6 NANDs 6 * 4 = 24 transistors

## Want to design a circuit that responds on the positive

edge of the clock pulse only

1

P3

P1

Clock
P2

P4

When Clock = 0

## P1 = P2 = 1 Q and Q' remain unchanged

P4 = D' and P3 = D

## P4 transmits thru gate 3 P2 = D

P3 transmits thru gate 2 P1 = D'

## After the 0 1 transition of Clock

If D = 0 at edge of Clock P4 = 1
regardless of any further D changes
If D = 1 at edge of Clock P2 = P3 = 1
regardless of any further D changes

## Clock = 1 P1 = D', P2 = D, P3 = D, P4 = D' (memory)

Clock transitions 1 0, back to P1 = P2 = 1 case (memory)

## Active low clear and preset asynchronous

operation on a Master-Slave D Flip-Flop

Preset = 0 Q = 1
Clear = 0 Q = 0

Preset
D

Clock
Preset
Q
D

Q
Q

Clear
Clear

Preset

Preset
Q
D

Clock
Q
Q
Clear
D
Clear

Clear

D
Clock

Terms Reviewed

Latch

Gated latch

## Latch with an control enable, called Clk

Two basic types: SR and D, both level sensitive

Master-slave flip-flop

## State changes only on clock edge; made from two gated D

latches

Edge-triggered flip-flop

T Flip-Flop

Toggle flip-flop

D = T'Q + TQ'

D
T

Clock

Q(t+1)

Q(t)

Q(t)'

Q
Q

JK Flip-Flop

## JK behaves just like SR but

removes the S=R=1 problem

Q(t+1)

## Output toggles on clock edge

when J = K = 1

Q(t)

D = JQ' + K'Q

Q(t)'

J
D
K
Clock

State Diagrams: D

D

Q(t+1)

Q(t+1) = D

## Again, transitions occurs only on a clock edge

1

1
0

characteristic equation

State Diagrams: T

T
T

Q(t+1)

Q(t)

Q(t)'

## The state diagram is

1
characteristic equation

1
1

State Diagrams: SR

## The SR flip-flop state table

S

Q(t+1)

00

01

11

10

Q(t)

SR
Q

x
Q(t+1) = S + R'Q(t)

## The state diagram is

10

0x

1
01

x0

characteristic equation

State Diagrams: JK

## The JK flip-flop state table

J

Q(t+1)

static hazard!!

00

01

11

10

Q(t)

JK
Q

Q(t)'
Q(t+1) = J Q(t)' + K' Q(t), or
Q(t+1) = J Q(t)' + K' Q(t) + J K'

## The state diagram is

1x

0x

x0
characteristic equation

x1

Characteristic Equations

## How is the next state determined from the inputs and

current state?

Flip-flop

Characteristic Equation

Q(t+1) = D

Q(t+1) = T Q(t)

SR

JK

## Q(t+1) = J Q(t)' + K' Q(t)

Excitation Tables

## For each state transition Q(t) Q(t+1), what input

combination(s) will produce that transition?

Q(t)

Q(t+1)

SR

JK

0x

0x

10

1x

01

x1

x0

x0

Registers

## When you want to store n bits register

n flip-flops used
Clock is shared by all so action is synchronous with clock
edge

## Some common register types

Simple register
Shift register
Parallel access shift register
Lots of counters: up counter, down counter, BCD counter,
ring counter, Johnson counter

Parallel output
Q3

Q
Q

Q2

Q
Q

Q1

Q
Q

Q0

Q
Q

Parallel input
Clock

Parallel output
Q3

Q2

Q1

Q0

Parallel input
Clock

In
Clock

Q
Q

Q1

Q
Q

Q2

Q
Q

Q3

Q
Q

Q4

Out

In

Q1

Q2

Q3

Q4 = Out

t0

t1

t2

t3

t4

t5

t6

t7

a flip-flop?

## Parallel Access Shift Register

Provide serial shift
D

Shift right

Parallel output

Q3
Q
Q

input

Q2
D

Q1
D

Parallel input

Q
Q

Q0
D

Q
Q

Clock

## Design a parallel access (parallel data in / out) shift

register that can load or shift either left or right
choice dictated by a control signal

## Then add the ability to "stay in memory"

Don't forget to connect serial in to both MSB and LSB

S1

S0

Function

memory

SHR

SHL

Parallel output
Q3
D

Q3

s1
s0

0 1 2 3

Q3

s1
s0

0 1 2 3

Q3

s1
s0

0 1 2 3

SRSI

Q
Q

s1
s0

0 1 2 3

SLSI
Parallel input

Clock

74164 Shifter

## Active low clear (CLRN)

Data-in provided by AND(A,B)
Positive edge triggered shift right register

74165 Shifter

modems)

## Active low asynchronous parallel load output is H

CLKIH is an active high clock inhibit memory state
Positive edge-triggered shift right register: SER is serial in

## Active low asynchronous clear

Shift Left Serial In (SLSI)
Shift Right Serial In (SRSI)
Positive edge-triggered

Asynchronous Counters

1
Clock

Q0

MSB of count

Q1

Q2

## Q0 toggles on every 0 1 clock edge

Q1 toggles on every 1 0 transition of Q0
Q2 toggles on every 1 0 transition of Q1

Clock

Q0

Q
Q

Q1

Q2

Clock
Q0
Q1
Q2
Count

## Assumes output is in order Q2 Q1 Q0

Modulo 8 up counter

## All other flip-flops are not asynchronous

Also called ripple counter

1
Clock

Q0

Q
Q

Q1

Q2

## To count 111 110 001 000 111

Clock

Q
Q0

Q
Q

Q1

Q2

Clock
Q0
Q1
Q2
Count

Synchronous Counters

delays

## Synchronous counters share the clock among all flip-flops

clock cycle

Q2

Q1

Q0

T0 = 1
T1 = Q0
T2 = Q1Q0
T3 = Q2Q1Q0

always toggle
toggle when Q0 = 1
toggle when Q1Q0 = 1
toggle when Q2Q1Q0 = 1

Q0
Clock

Q1
Q

Q2
Q

Q3
Q

Q0
Clock

Q1

T
Q2

Q3

Clock
Q0
Q1
Q2
Q3
Count 0

10 11

12 13

14 15

## Just use T flip-flop with asynchronous clear

Cascade the Enable via AND gates to the T inputs

Enable
Clock

Clear

Q
Q

Q
Q

Q
Q

Q
Q

## How can you make an up counter using D flip-flops?

clock cycle

Q2

Q1

Q0

D0 = 1 Q0
D1 = Q1 Q0
D2 = Q2 Q1Q0
D3 = Q3 Q2Q1Q0

always toggle
toggle when Q0 = 1
toggle when Q1Q0 = 1
toggle when Q2Q1Q0 = 1

4 Bit Up Counter
Enable

D Q

Q0

## Enable input permits

control of counter

D Q

Q1

## Output carry permits

chaining of counters
to make larger ones

D Q

Q2

D Q

Q3

Q
Clock

Output
carry

## Want a counter that

value that you desire
in order to start the
count

Enable

D0

0
1

D1

0
1

DQ

Q0

DQ

Q1

D2
Enable = 1 increment
Load = Enable = 0 memory
D3

Clock

0
1

DQ

Q2

0
1

DQ

Q3

Q
Output
carry

## Most counters reset (cycle) to 0 when all k flip-flops

are 1 value of count = 2k-1

Mod 8 counter: k = 3

## 000 001 101 000

This is a mod 6 counter

## When output = Q2Q1Q0 = 101, load 000 to force

reset on next clock edge

Enable

D0

Q0

D1

Q1

D2

Q2

Clock
Clock

BCD Counter

## Count from 0 to 9 and back to 0

Cascade the counters to mimic decimal counting

Ring Counter

00 01 09 10 11 19 20
Each position is a BCD digit

## 4 bit ring count: 1000 0100 0010 0001 1000

One-hot output that cycles in a ring

Johnson Counter

0011 0001 0000

1
0
0
0
0

Enable
D0
D1
D2
D3

Q0
Q1
Q2
Q3

BCD 0

Clock
Clock
Clear

0
0
0
0

Enable
D0
D1
D2
D3
Clock

## Is 1 when 1xx1 is detected

-- first time is for 1001 = 9
Q0
Q1
Q2
Q3

BCD 1

## A design that uses a minimum of combinational

logic, but uses more flip-flops
asynchronous preset
Q0

Q1

Qn 1

Start

Clock

asynchronous clear

Johnson Counter

0001 0000 .

Q0

Q
Q

Reset
Clock

Q1

Q
Q

Qn 1

Q
Q

into the count

## Verilog assumes the value of Q

must be maintained if Clk is 0 and
therefore synthesizes a latch

change in level

## Verilog will use flip-flops to synthesize

circuits that are edge-triggered

Verilog Example

x3
x1

x2
Q

D
Clock

## Order matters inside an always block!

x3

x1
x2
Clock

Blocking Assignments

## The order of statements inside an always block can

affect the synthesized design

## Verilog evaluates the assignments in an always block in the

order in which they are written

## This can cause unexpected designs

D

Clock

Q1

D
treated as Q2 = D since Q1 = D

Q2

Non-Blocking Assignments

## What if you wanted a cascaded design for the

previous example?

## The assignment to Q2 should be from the previous Q1

Need both assignments to occur in parallel on the same
clock edge

## The LHS of a non-blocking assignment is updated after all

RHS values for all assignments have been evaluated

D
Clock

non-blocking assignment

Q1
D

Q2

Non-Blocking Example

## Compare this to the earlier example

using blocking assignments

x3

x1
x2
Clock

## Use blocking assignments when designing

combinational logic

## Non-blocking is OK when doing finite state machine (FSM)

design (to be covered later)

## Use non-blocking assignments when designing

sequential logic (including for latches)

## Do not mix blocking and non-blocking assignments

in the same always block

## The sensitivity list cannot mix edge triggered and

level sensitive events

## Must make reset edge-triggered, but on a different edge

Synchronous Clear

Parallel output

## One technique: build a

simple 2X1 MUX
controlled D flip-flop

Q3

Q2

Q1

Q0

D Q

D Q

D Q

D Q

input

Parallel input

Clock

## A hierarchical design mixing

behavioral and structural styles

N-Bit Up Counter

## Provide an n-bit up counter with asynchronous clear

and an enable control

## Provide an n-bit up counter with asynchronous clear,

an enable control, and parallel load

## blocking assignments are executed

before non-blocking ones

## Do not mix blocking and non-blocking assignments in the

same always block

latches

## This style separates

blocking and non-blocking
assignments into separate
always blocks

pinB

pinB

## module serial_adder_datapath(sum, sout, pinB, ctl, reset, clk) ;

output [7:0] sum ;
output sout ;
input
sinB ;
input
[ ] ctl ;
input
reset, clk ;
endmodule
module serial_adder_control(ctl, busy, start, clrA, reset, inv_clk) ;
output [ ] ctl ;
output busy ;
input
reset, start, inv_clk ;
endmodule

Binary Multiplication

Binary Multiplier

ASM Chart

Numerical Example

## Serial Multiplier (Verilog)

// multiplier
module multiplier(S, clk, clr, Bin, Qin, C, A, Q, P) ;
input
S, clk, clr ;
input
[4:0] Bin, Qin ;
output C ;
output [4:0] A, Q ;
output [2:0] P ;
// system registers
reg
reg
reg
reg

C ;
[4:0] A, Q, B ;
[2:0] P ;
[1:0] pstate, nstate ;

parameter

## T0 = 2'b00, T1= 2'b01, T2 = 2'b10, T3 = 2'b11 ;

// combinational circuit
wire
assign

Z ;
Z = ~|P ;

## always @(negedge clk or negedge clr) begin

if (~clr) pstate <= T0 ;
else pstate <= nstate ;
end

## Serial Multiplier (Continued)

// state transition process for controller
always @(S or Z or pstate) begin
case (pstate)
T0:
if (S) nstate = T1; else nstate = T0 ;
T1:
nstate = T2 ;
T2:
nstate = T3 ;
T3:
if (Z) nstate = T0; else nstate = T2 ;
endcase
end
// register transfer operations
always @(posedge clk) begin
case (pstate)
T0:
B <= Bin ;
T1:
begin
A <= 0 ;
C <= 1 ;
P <= 5 ;
Q <= Qin ;
end
T2:
begin
P <= P - 1 ;
if (Q) {C,A} <= A + B ;
end
T3:
begin
C <= 0 ;
A <= {C, A[4:1]} ;
Q <= {A, Q{4:1]} ;
end
endcase
end
endmodule

## Serial Multiplier (Testbench)

// multiplier testbench
module multiplier_tb;
reg
S, clk, clr ;
reg
[4:0] Bin, Qin ;
wire
C ;
wire
[4:0] A, Q ;
wire
[2:0] P ;
// instantiate multiplier
multiplier

initial begin
#0
begin
S =
clk
clr
end
#5 begin
S =
Bin
Qin
#15 begin
S =
end
end

0;
= 0;
= 0 ;

1; clr = 1;
= 5'b10111 ;
= 5'b10011 ;

0 ;

## Serial Multiplier (Testbench, continued)

// create dumpfile and generate clock
initial begin
\$dumpfile("./multiplier.dmp") ;
\$dumpflush ;
\$dumpvars(2, multiplier_tb) ;
repeat (26) #5 clk = ~clk ;
end
endmodule

## Design of Sequential Circuits

StateTable
The state table representation of a sequential circuit
consists of three sections labelled
present state,
next state
output.
The present state designates the state of flip-flops before
the occurrence of a clock pulse.
The next state shows the states of flip-flops after the clock
pulse, and
the output section lists the value of the output variables
during the present state.

State Diagram
The binary number inside each
circle identifies the state the
circle represents. The directed
lines are labelled with two
binary numbers separated by a
slash (/).
The input value that causes the
state transition is labelled first.
The number after the slash
symbol / gives the value of the
output.

## For example, the directed line from state 00 to 01

is labelled 1/0, meaning that, if the sequential
circuit is in a present state and the input is 1, then
the next state is 01 and the output is 0.
If it is in a present state 00 and the input is 0, it
will remain in that state.
A directed line connecting a circle with itself
indicates that no change of state occurs.
The state diagram provides exactly the same
information as the state table and is obtained
directly from the state table.

## Sequential Circuit Design

Process
Steps in Design of a Sequential Circuit
1. Specification A description of the sequential
circuit. Should include a detailing of the inputs, the
outputs, and the operation. Possibly assumes that you
have knowledge of digital system basics.
2. Formulation: Generate a state diagram and/or a state
table from the statement of the problem.
3. State Assignment: From a state table assign binary
codes to the states.
4. Flip-flop Input Equation Generation: Select the type
of flip-flop for the circuit and generate the needed input
for the required state transitions
150

## Sequential Circuit Design

Process 2
5. Output Equation Generation: Derive output
logic equations for generation of the output
from the inputs and current state.
6. Optimization: Optimize the input and output
equations. Today, CAD systems are typically
used for this in real systems.
7. Technology Mapping: Generate a logic
diagram of the circuit using ANDs, ORs,
Inverters, and F/Fs.
8. Verification: Use a HDL to verify the design.
151

## Mealy and Moore

Sequential machines are typically classified as
either a Mealy machine or a Moore machine
implementation.
Moore machine: The outputs of the circuit
depend only upon the current state of the
circuit.
Mealy machine: The outputs of the circuit
depend upon both the current state of the
circuit and the inputs.
152

## An example to go through the

steps
The specification: The circuit will have one
input, X, and one output, Z. The output Z
will be 0 except when the input sequence
1101 are the last 4 inputs received on X. In
that case it will be a 1.

153

## Generation of a state diagram

Create states and meaning for them.
State A the last input was a 0 and previous inputs
unknown. Can also be the reset state.
State B the last input was a 1 and the previous
input was a 0. The start of a new sequence
possibly.

154

## Notes on State diagrams

Capture this in a state diagram
Circles represent the states
Lines and arcs represent the transition between state.
The notation Input/Output on the line or arc specifies
the input that causes this transition and the output for
this change of state.

155

## Continue to build up the diagram

State C Have detected the input sequence 11
which is the start of the sequence.

9/15/09 - L22
Sequential Circuit

## Copyright 2009 - Joanne DeGroat,

ECE, OSU

156

Continue
State D have detected the 3rd input in the start
of a sequence, a 0, now having 110. From State
D, if the next input is a 1 the sequence has been
detected and a 1 is output.

157

The previous diagram was incomplete.
In each state the next input could be a 0 or a
1. This must be included.

158

## Now generate a state table

The state table
This can be done directly from the state
diagram.

159

## Select a state assignment

Will select a gray encoding
For this state A will be encoded 00,
state B 01, state C 11 and state D 10

160

## Flip-flop input equations

Generate the equations for the flip-flop
inputs
Generate the D0 equation

161

## The output equation

The next step is to generate the equation for
the output Z and what is needed to generate
it.
Create a K-map from the truth table.

162

## Now map to a circuit

The circuit has 2 D type F/Fs

163

Circuits
Example:

1

0
S0 / 0

S1 / 0
0

0
S3 / 1

S2 / 0

State A B
S0
0 0
S1
0 1
S2

1 0

S3

1 1

1
164

Circuits
Example:

Present
Input
State

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

x
0
1
0
1
0
1
0
1

Next
State

A
0
0
0
1
0
1
0
1

B
0
1
0
0
0
1
0
1

Output

y
0
0
0
0
0
0
1
1

0
S0 / 0

S1 / 0
0

0
S3 / 1

1
S2 / 0

1
165

Circuits
Example:

Present
Input
State

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

x
0
1
0
1
0
1
0
1

Next
State

A
0
0
0
1
0
1
0
1

B
0
1
0
0
0
1
0
1

Output

y
0
0
0
0
0
0
1
1

## Synthesis using D Flip-Flops

A(t+1) = DA (A, B, x)
= (3, 5, 7)
B(t+1) = DB (A, B, x)
= (1, 5, 7)
y (A, B, x) = (6, 7)
166

## Design of Clocked Sequential

Example:Circuits with D F.F.

## Detect 3 or more consecutive 1s

Synthesis using D Flip-Flops

DA (A, B, x) = (3, 5, 7)
= Ax + B x
DB (A, B, x) = (1, 5, 7)
= A x + B x
y (A, B, x) = (6, 7)
=AB

0 0 1 0
A 0 1 1 0
x

B
0 1 0 0

A 0 1 1 0
x

0 0 0 0
A 0 0 1 1
x

167

## Design of Clocked Sequential

Example:Circuits with D F.F.

## Detect 3 or more consecutive 1s

Synthesis using D Flip-Flops

DA = A x + B x
DB = A x + B x
y =AB

Q
y

D
CLK
Eastern Mediterranean University

Q
168

Present Next
State State

F.F.
Input

Q(t) Q(t+1) D
0
0 0
0
1 1
1
0 0
1
1 1

Present Next
State State

F.F.
Input

Q(t) Q(t+1) J K
0
0 0 x
0
1 1 x
1
0 x 1
1
1 x 0

0 0 (No change)
0 1 (Reset)
1 0 (Set)
1 1 (Toggle)
0 1 (Reset)
1 1 (Toggle)
0 0 (No change)
1 0 (Set)

Q(t) Q(t+1) T
0
0 0
0
1 1
1
0 1
1
1 0
169

## Design of Clocked Sequential

Example:Circuits with JK F.F.

## Detect 3 or more consecutive 1s

Present
Input
State

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

x
0
1
0
1
0
1
0
1

Next
State

A
0
0
0
1
0
1
0
1

Flip-Flop
Inputs

B JA KA JB KB
0 0 x 0 x
1 0 x 1 x
0 0 x x 1
0 1 x x 1
0 x 1 0 x
1 x 0 1 x
0 x 1 x 1
x University
0
1 xEastern 0Mediterranean

## Synthesis using JK F.F.

JA (A, B, x) = (3)
dJA (A, B, x) = (4,5,6,7)
KA (A, B, x) = (4, 6)
dKA (A, B, x) = (0,1,2,3)
JB (A, B, x) = (1, 5)
dJB (A, B, x) = (2,3,6,7)
KB (A, B, x) = (2, 3, 6)
dKB (A, B, x) = (0,1,4,5)
170

## Design of Clocked Sequential

Example:Circuits with JK F.F.

## Detect 3 or more consecutive 1s

Synthesis using JK Flip-Flops

KA = x
KB = A + x

JA = B x
JB = x

CLK

0 0 1 0

x x x x
A 1 0 0 1
x
B
x x 1 1
A x x 0 1
x

A x x x x
x
B
0 1 x x

A 0 1 x x
x

171

## Design of Clocked Sequential

Example:Circuits with T F.F.

Present
Input
State

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

x
0
1
0
1
0
1
0
1

Next
State

A
0
0
0
1
0
1
0
1

B
0
1
0
0
0
1
0
1

F.F.
Input

TA
0
0
0
1
1
0
1
0

TB
0
1
1
1
0
1
1
0

## Synthesis using T Flip-Flops

TA (A, B, x) = (3, 4, 6)
TB (A, B, x) = (1, 2, 3, 5, 6)

172

## Design of Clocked Sequential

Example:Circuits with T F.F.

## Detect 3 or more consecutive 1s

Synthesis using T Flip-Flops

TA = A x + A B x
TB = A B + B x
B

0 0 1 0

0 1 1 1

A 1 0 0 1
x

A 0 1 0 1
x

CLK
173