FACULTY OF ENGINEERING

UNIVERSITI MALAYSIA SARAWAK

SEMESTER 1
SESSION 2012/2013

Course Title
Course Code
Course Credit
Course Status
Prerequisite
Synopsis

Course Outcomes (CO)

COURSE PLAN
VLSI Design
KNL 4343
3
Core
This course teaches techniques in designing and analyzing VLSI circuits. These include
design rules, layout fundamentals, switch-level simulation, charge sharing, static and
dynamic logics, propagation-delay estimates, power considerations, data-path
organization, clocking schemes, synchronizers, asynchronous circuits, pads, systolic
computation, silicon compiler, high-level synthesis and hardware description languages.
Students will also utilized EDA tools in this course.
By the end of this course, students should be able to;
CO1
CO2
CO3
CO4

Week

Topics

1
(10/9/12 16/9/12)

2
(17/9/12 23/9/12)

3
(24/9/12 30/9/12)

4
(1/10/12 7/10/12)

5
(8/10/12 14/10/12)

6
(15/10/12 21/10/12)

KNL4343

comprehend the properties of VLSI technology and the effect in logic

implementation, optimization and system design (A2).
acquire design skills and its role in VLSI(C2).
use EDA software for VLSI design(P2).
use varieties of technologies, design objectives and analysis techniques for
relevant VLSI applications(A2).

Page 1 of 3

Introduction
VLSI history
CMOS circuits
Design representations
Process Technology
semi-conductor technology
wafer processing
CMOS technologies
P-well, n-well, twin-tub
interconnect
Process Technology (contd)
circuit elements
layout design rules
mask layout editors
design description languages
process and design rules
MOS Circuit
nMOS transistor
pMOS transistor
threshold voltage
body effect
DC characteristics
MOS Circuit (Contd)
inverters
transmission gates
bipolar devices
latch-up
SPICE simulation
Circuit Characterization
capacitance estimation
resistance estimation

CO

Delivery

Assessment/Evaluation

Lecture
CO1
Lecture
Tutorial

Test
Final Examination

Lecture
Tutorial

Lecture
Tutorial

Assignment
Test
Final Examination

Lecture
Tutorial

Assignment
Test
Final Examination

Lecture
Tutorial

Assignment
Test

CO1

CO1

CO2

CO2

CO2

Assignment
Quiz
Test
Final Examination

switching characteristics

Circuit Characterization
(contd)
design for speed
transistor gate sizing
power consumption
charge sharing and reliability
design margins and scaling
Circuit and Logic Design
CMOS structure
electrical and physical design
of gates
clocking strategies
Input/Output
Structures and logic
simulation

7
(22/10/12 28/10/12)

8
(29/10/12 4/11/12)

Lecture
Tutorial
CO2

Final Examination
Assignment
Quiz
Test
Final Examination

Lecture
Tutorial

Assignment
Test
Final Examination

Lecture
Tutorial

Lecture
Tutorial

Assignment
Test
Final Examination

Lecture
Tutorial

Lecture
Tutorial

Lecture
Tutorial

Assignment
Final Examination

Lecture
Tutorial

Assignment
Final Examination

CO3

Mid Semester Break

9
(12/11/12 18/11/12)

10
(19/11/12 25/11/12)

11
(26/11/12 2 /12/12)

12
(3/12/12 - 9/12/12)

13
(10/12/12 16/12/12)

14
(17/12/12 23/12/12)

KNL4343

CMOS Logic Design

power dissipation
power delay
NOR and NAND gates
inverter layout
static and dynamic
characteristic of inverter
Design High-Speed CMOS Logic
Network
high speed design
introduction
design techniques
transistor sizing
ordering effect
intrinsic delay
Low Power Design
power delay
energy delay
dynamic power consumption
Low Power Design (contd)
leakage
transition probabilities
dynamic CMOS
dynamic gates
Timing Issues
digital circuits
synchronous
mesochronous
plesiochronous and
asynchronous interconnect
self timed circuit design
clock synthesis
Subsystem Design
adders
counters
RAM

Page 2 of 3

CO3

Assignment
Quiz
Test
Final Examination

CO3

CO3

Assignment
Quiz
Test
Final Examination
Assignment
Final Exam

CO4

CO4

CO4

PLA
Design synthesis
Design for testability

15
(24/12/12 30/12/12)

Revision Week
(1 week)

16 18
(31/12/12 20/1/13)

Exam Week
(3 weeks)

Teaching - Learning
Approach

Assessment

Test (s)
Assignment(s)/Tutorial(s)/
(s)/Cooperative Learning
Final Exam

1.
2.
Resources
3.

KNL4343

Hours per semester

28
28

Lectures (2 hours = 2 credits)

Tutorial (2 hours = 1 credit)
Laboratory/Practical
Case Study Presentation
Total

Page 3 of 3

PBL

56
Percentage
/Quiz

(s)/

Project

20
30
50

Total
100
Wolf W., Modern VLSI Design, 4th Ed., Prentice Hall, 2009.
Brunvand E., Digital VLSI Chip Design with Cadence
and Synopsys CAD Tools, Addison-Wesley, 2010.
Weste N. H. E. and Harris D., Principles of CMOS
VLSI Design, 3rd Edition, Addison Wesley, 2004.