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The field of micromachined sensors and actuators, offen reffered to as “MEMS”, has
been growing at an exciting place in recent years. Using tools originally developed for the
silicon integrated circuit industry, people are now fabricating miniaturized transducers and
structures from silicon and other materials. In many cases, these new devices offer their
conventional counterparts, including great reduction in siz, new functions that could not
reductions in per-unit cost, and the ability to fabricate scaled and multimodal arrays.
In this theses I design a RF switch which can be used in many RF circuits such as
1
CHAPTER 2 – GENERAL PERSPECTIVE OF DESIGN
2.1. RF SWITCH
RF switches have a broad varietyof where active and passive components can be switched into
or out of RF circuits. Example applications are digitally conroled antenna matching circuits,
transmit/receive switches, phase shifters for phassed array radars, input filters, tuning circuits,
In my design I used a comb drive for the actuator of the switch. Moreover I designed a
automatic control system to control switch. These two systems designed separetly on different
chip, then wire bonded each other. Because the integration of microelectronics with MEMS is a
key component to the success of most MEMS devices. By placing electronics closer to sensors
and actuators, the device performance is improved. Several different approaches have been
taken in the integration of electronics with MEMS. The hybrid approach, in which the
electronics and MEMS are wire bonded into a single package has long been the industry
standard. This is the simplest approach is not batch produced, can suffer from large
capacitances and inductive losses in wires and can result in a large final product. The
embedded or monolithic approach, in which the electronics are fabricated on the same substrate
as the MEMS, provides excellent performance and benefits from batch fabrication. However,
because the electronics and MEMS are fabricated on the same substrate, the processing is
extremely complex and the MEMS and electronics processes must be compatible. The
increased complexity of the process can drive up cost and impact process yield.
Flip chip MEMS has emerged as an excellent alternative to the above methods. This method
involves fabricating the electronics and MEMS as separate parts and then attaching them, face-
toface, with solder bumps. Flip chip provides good device performance with little or no area
penalty and most importantly, it provides complete process independence of the MEMS and
the electronics. This allows the manufacturer to optimize the performance of each component
separately. Flip chip also allows the building of the electronics and MEMS on substrate types
2
2.2. Flip Chip MEMS
Flip chip is a general term that describes a method of attaching an IC (or MEMS chip) to
substrate. The substrate can be another chip, a PC board, a special carrier or a multichip
module. More specifically, flip chip is a technology in which one chip is placed face down (flip
chipped) on to the substrate and attached through solder bumps that provide both mechanical
and electrical connection. Flip chip provides a much higher interconnection density than
traditional methods (i.e. wire bonding) because the interconnections are distributed across the
entire chip surface rather than being restricted to the periphery of the chip. When applied to
MEMS, flip chip provides an alternative to the traditional integration methods of either hybrid
packaging or embedded (monolithic) electronics integration. Since flip chip allows the IC to be
placed directly over a MEMS device, there is little or no area penalty and the electronics are
electrically much closer to the sensor or actuator thus improving performance. In cases where
the MEMS device must be exposed to the environment (e.g. an optical device), the electronics
can be attached to one side of the MEMS device. Once the two chips are joined by flip chip,
the attached pair can be mounted in a traditional package. An outer pad ring on the bottom
(larger) chip provides wire bonding pads for connection to the package.
The flip chip process developed by MCNC uses electroplated solder to create bumps for
attachment. The electroplating method provides a cost effective method of fabricating small
bumps with small pitches. Figure 2.1 Figure 2.5 illustrate the bump fabrication process wich is
3
Figure 2.1 The bumping process begins with a finished, passivated IC wafer. The solder bumps
The process begins by sputtering a layer of metal known as the under bump metallurgy, or
UBM on the finished ECOSYS wafer (Figure 2.1). The UBM is a solder wettable metal that
acts as both a plating base and a good contact for the solder bump after reflow. A second metal
layer is evaporated and patterned by liftoff to form the solder dam that confines the bump
upon reflow (Figure 2.2). The holes in the solder dam are centered on the underlying I/O's. A
thick layer of photoresist is then patterned to form the solder plating template and the solder is
electroplated (Figure 2.3). The template is then removed and the solder is reflowed to produce
a solder bump confined at the base by the solder dam (Figure 2.4). After the reflow, the
solder dam and UBM are removed (Figure 2.5). At this point, the wafer can be diced and the
individual chips are ready for die attach. Figure 2.6 is a scanning electron micrograph of the
Figure 2.2 The under bump metallurgy (UBM) is sputtered. This is followed by the thermal
evaporation and liftoff patterning of the solder dam metallurgy. The solder dam is a non solder
4
Figure 2.3 A thick layer of photoresist is patterned to create a plating template. The solder is
Figure 2.4 The plating template is removed and the wafers are heated to reflow the solder.
Figure 2.5 The solder dam and UBM is etched to expose the original passivation layer. The
wafer can now be diced and the individual chips are ready for flip chip attach to the MUMPs
chip.
5
Figure 2.6 Scanning electron micrograph of solder bumps after reflow. At this point the chip is
The die attach process is performed on the chip level. Because solder is attacked in the
HF used for releasing the MEMS devices, the release must be performed before die attach. The
ECOSYS chip is pretreated in a plasma process that eliminates the need for flux to attach the
solder joints,. This "fluxless solder" technique, known as PADS (Plasma Assisted Dry
Soldering), has the added benefit of not requiring a post solder clean which would expose the
MEMS devices to wet chemicals causing stiction problems. After plasma treatment, the chips
are aligned (Figure 2.7), contacted and the solder is reflowed. Figure 2.8 is a picture of a joined
pair following reflow. After solder reflow, the joined pair can be placed in a
6
Figure 2.7 The MEMS chip is aligned so that the appropriate pads are in contact and the solder
is heated to reflowtemperature providing both mechanical and electrical contact. In this case
the MEMS chip is the smaller of the two and it is attached on top of the IC. For SmartMUMPs,
the MEMS chip is larger and the IC is mounted on top of the MEMS chip and the wirebond
7
Figure 2.9 The joined MEMS/IC pair is die and wire bonded to a standard package.
8
CHAPTER 3 – MEMS PROCESS
government worldwide. MEMSCAP offers three standard processes as part of the MUMPs ®
micromachining process.
The following is a general process description and user guide for PolyMUMPs, which
FIGURE 3.1 Cross sectional view showing all 7 layers of the PolyMUMPs process (not to
scale).
PolyMUMPs process. This process has the general features of a standard surface
micromachining process: (1) polysilicon is used as the structural material, (2) deposited oxide
9
(PSG) is used as the sacrificial layer, and silicon nitride is used as electrical isolation between
the polysilicon and the substrate. The process is different from most customized surface
of supporting many different designs on a single silicon wafer. Since the process was not
optimized with the purpose of fabricating any one specific device, the thicknesses of the
structural and sacrificial layers were chosen to suit most users, and the layout design rules were
derived from work performed at the Berkeley Sensors and Actuators Center (BSAC) at the
University of California in the late 80's and early 90's. Several modifications and enhancements
have been made to increase the flexibility and versatility of the process for the multi-user
environment. The process flow described below is designed to introduce inexperienced users to
polysilicon micromachining. The text is supplemented by detailed drawings that show the
The process begins with 100 mm n-type (100) silicon wafers of 1-2 W-cm resistivity.
The surface of the wafers are first heavily doped with phosphorus in a standard diffusion
furnace using POCl 3 as the dopant source. This helps to reduce or prevent charge feedthrough
to the substrate from electrostatic devices on the surface. Next, a 600 nm low-stress LPCVD
(low pressure chemical vapor deposition) silicon nitride layer is deposited on the wafers as an
electrical isolation layer. This is followed directly by the deposition of a 500 nmLPCVD
the coating of the wafers with photoresist (Figure 3.2), exposure of the photoresist with the
appropriate mask and developing the exposed photoresist to create the desired etch mask for
subsequent pattern transfer into the underlying layer (Figure 3.3). After patterning the
photoresist, the Poly 0 layer is then etched in an RIE (Reactive Ion Etch) system (Figure 3.4).
A 2.0 µm phosphosilicate glass (PSG) sacrificial layer is then deposited by LPCVD (Figure
10
3.5) and annealed @1050°C for 1 hour in argon. This layer of PSG, known as First Oxide, is
removed at the end of the process to free the first mechanical layer of polysilicon. The
sacrificial layer is lithographically patterned with the DIMPLES mask and the dimples are
transferred into the sacrificial PSG layer by RIE, as shown in Figure 3.6. The nominal depth of
the dimples is 750 nm. The wafers are then patterned with the third mask layer, ANCHOR1,
and reactive ion etched (Figure 3.7). This step provides anchor holes that will be filled by the
Poly 1 layer. After etching ANCHOR1, the first structural layer of polysilicon (Poly 1) is
deposited at a thickness of 2.0 µm. A thin (200 nm) layer of PSG is deposited over the
polysilicon and the wafer is annealed at 1050°C for 1 hour (Figure 3.8). The anneal dopes the
polysilicon with phosphorus from the PSG layers both above and below it. The anneal also
serves to significantly reduce the net stress in the Poly 1 layer. The polysilicon (and its PSG
masking layer) is lithographically patterned using a mask designed to form the first structural
layer POLY1. The PSG layer is etched to produce a hard mask for the subsequent polysilicon
etch. The hard mask is more resistant to the polysilicon etch chemistry than the photoresist and
ensures better transfer of the pattern into the polysilicon. After etching the polysilicon (Figure
3.9), the photoresist is stripped and the remaining oxide hard mask is removed by RIE.
After Poly 1 is etched, a second PSG layer (Second Oxide) is deposited and
annealed(Figure 3.10). The Second Oxide is patterned using two different etch masks with
different objectives. The POLY1_POLY2_VIA level provides for etch holes in the Second
Oxide down to the Poly 1 layer. This provide a mechanical and electrical connection between
the Poly 1 and Poly 2 layers. The POLY1_POLY2_VIA layer is lithographically patterned and
etched by RIE (Figure 3.11). The ANCHOR2 level is provided to etch both the First and
Second Oxide layers in one step, thereby eliminating any misalignment between separately
etched holes. More importantly, the ANCHOR2 etch eliminates the need to make a cut in First
Oxide unrelated to anchoring a Poly 1 structure, which needlessly exposes the substrate to
subsequent processing that can damage either Poly 0 or Nitride. The ANCHOR2 layer is
11
Figure 3.12 shows the wafer cross section after both POLY1_POLY2_VIA and
ANCHOR2 levels havebeen completed. The second structural layer, Poly 2, is then deposited
(1.5 µm thick) followed by the deposition of 200 nm PSG. As with Poly 1, the thin PSG layer
acts as both an etch mask and dopant source for Poly 2 (Figure 3.1.13). The wafer is annealed
for one hour at 1050 C to dope the polysilicon and reduce the residual film stress. The Poly 2
layer is lithographically patterned with the seventh mask (POLY2) and the PSG and
polysilicon layers are etched by RIE using the same processing conditions as for Poly 1. The
photoresist then is stripped and the masking oxide is removed (Figure 3.1.14). The final
deposited layer in the PolyMUMPs process is a 0.5 µm metal layer that provides for probing,
bonding, electrical routing and highly reflective mirror surfaces. The wafer is patterned
lithographically with the eighth mask (METAL) and the metal is deposited and patterned using
lift-off. The final, unreleased structure is shown in Figure 3.15. The wafers are diced, sorted
and shipped to the PolyMUMPs user for sacrificial release and test. Figure 3.16 shows the
device after sacrificial oxide release. The release is performed by immersing the chip in a bath
of 49% HF (room temperature) for 1.5-2 minutes. This is followed by several minutes in DI
water and then alcohol to reduce stiction followed by at least 10 minutes in an oven at 110° C.
Generally the participants receive their dice and perform the sacrificial oxide release in their
own facility. For those participants who request it, release of their dice at MEMSCAP's facility
can be arranged for an additional fee. The following provides a graphical representation of the
process steps.
12
FIGURE 3.2. The surface of the starting n-type (100) wafers are heavily doped with
phosphorus in a standard diffusion furnace using POCl 3 as the dopant source. A 600 nm
blanket layer of low stress silicon nitride (Nitride) is deposited followed by a blanket layer of
500 nm polysilicon (Poly 0). The wafers are then coated with UV-sensitive photoresist.
through the first level mask (POLY0) and then developing it. The photoresist in exposed areas
13
FIGURE 3.4. Reactive ion etching (RIE) is used to remove the unwanted polysilicon.
After the etch, the photoresist is chemically stripped in a solvent bath. This method of
patterning the wafers with photoresist, etching and stripping the remaining photoresist is used
FIGURE 3.5. A 2.0 µm layer of PSG is deposited on the wafers by low pressure
FIGURE 3.6. The wafers are coated with photoresist and the second level (DIMPLE) is
lithographically patterned. The dimples, 750 nm deep, are reactive ion etched into the first
14
FIGURE 3.7. The wafers are re-coated with photoresist and the third level
(ANCHOR1) is lithographically patterned. The unwanted oxide is removed in an RIE etch and
followed by the deposition of 200 nm PSG and a 1050°C/1 hour anneal. The anneal serves to
15
FIGURE 3.9. The wafer is coated with photoresist and the fourth level (POLY1) is
lithographically patterned. The PSG is first etched to create a hard mask and then Poly 1 is
etched by RIE. After the etch is completed, the photoresist and PSG hard mask are removed.
FIGURE 3.10. The Second Oxide layer, 0.75 µm of PSG, is deposited on the wafer.
This layer is patterned twice to allow contact to both Poly 1 and substrate layers.
FIGURE 3.11. The wafer is coated with photoresist and the fifth level
16
FIGURE 3.12. The wafer is re-coated with photoresist and the sixth level (ANCHOR2)
is lithographically patterned. The Second and First Oxides are RIE etched, stopping on either
Nitride or Poly 0, and the photoresist is stripped. The ANCHOR2 level provides openings for
PSG hardmask layer. The wafers are annealed at 1050°C for one hour to dope the polysilicon
17
FIGURE 3.14. The wafer is coated with photoresist and the seventh level (POLY2) is
lithographically patterned. The PSG hard mask and Poly 2 layers are RIE etched and the
photoresist and hard mask are removed. All mechanical structures have now been fabricated.
The remaining steps are to deposit the metal layer and remove the sacrificial oxides.
FIGURE 3.15. The wafer is coated with photoresist and the eighth level (METAL) is
lithographically patterned. The metal (gold with a thin adhesion layer) is deposited by lift-off
patterning which does not require etching. The side wall of the photoresist is sloped at a
reentrant angle, which allows the metal to be deposited on the surfaces of the wafer and the
photoresist, but provides breaks in the continuity of the metal over the reentrant photoresist
step. The photoresist and unwanted metal (atop the photoresist) are then removed in a solvent
bath. The process is now complete and the wafers can be coated with a protective layer of
18
FIGURE 3.16. The structures are released by immersing the chips in a 49% HF
solution. The Poly 1 ``rotor'' can be seen around the fixed Poly 2 hub. The stacks of Poly 1,
Poly 2 and Metal on the sides represent the stators used to drive the motor electrostatically.
19
CHAPTER 4 – MECHANICAL SYSTEM
Comb drive is used in mechanical system as actuator of the switch. Two main formula
of comb drive is vey important. First of stifness of beam which is formulated as;
3EI
K=
L3
EWt 3
K=
4L3
1 2 t
F e= εV
2 g
For ε represents permittivity, V represents voltage between stator comb and actuated
comb, t is with of the comb and g is the distance between the actuated and stator comb. For n
1 t
F e= nεV 2
2 g
I designed the space between the actuated comb and stator comb 6um. Then From the equation
Kx=F
I used LASI software package to draw layout of mechanical part and ANSYS software package
20
MECHANICAL PROPERTIES OF POLYSILICON USED IN MUMPs PROCESS
21
micro California,Feb 1996, p.97
Friction 0.05 Lapped, scan size=500X500 nm2,using IEEE Micro Electro Mechanical
coefficient, nanotribology studies(AFM/FFM). Systems Workshop,SanDiego,
micro California,Feb 1996, p.97
Hardness 11.5 LPCVD,n+type(phosphorous doped),obtained by J.mater.Res,Vol.
GPa nanodentation at a load of 0.2 mN and indentation 12,No.1,Jan1997, p.59
depth of 25 nm at peak load.
Hardness 10.5 LPCVD,n+type(phosphorous doped),values J.mater.Res,Vol.
GPa obtained by nanodentation at a load of 15 mN and 12,No.1,Jan1997, p.59
indentation depth of 289 nm at peak load.
Hardness,n 12.5 Lapped, scan size=500X500 nm2,using IEEE Micro Electro Mechanical
anoindenta GPa nanotribology studies(AFM/FFM). Systems Workshop,SanDiego,
tion(at California,Feb 1996, p.97
100uN)
Internal -0.18 LPCVD film,calculated by using Load-Deflection Sensors and Actuators,20(1989),
stress GPa of composite rectangular p.138
membranes,thickness=0.2 um.
Roughness 1.45 nm LPCVD film,n+type(phosphorous doped), value J. Mater. Res., Vol. 12 No. 1, Jan
(Rms) measured using AFM at a scan size of 1 um x 1 1997, p.60
um.
Roughness 1.07 Scan size=500X500 nm2,using nanotribology IEEE Micro Electro Mechanical
(Rms) studies(AFM/FFM). Systems Workshop,SanDiego,
California,Feb 1996, p.97
Roughness 0.16 Lapped, scan size=500X500 nm2,using IEEE Micro Electro Mechanical
(Rms) nanotribology studies(AFM/FFM). Systems Workshop,SanDiego,
California,Feb 1996, p.97
Scratch 18 nm Scan size=500X500 nm2,using nanotribology IEEE Micro Electro Mechanical
depth,micr studies(AFM/FFM). Systems Workshop,SanDiego,
o(at 40uN) California,Feb 1996, p.97
Scratch 18 nm Lapped, scan size=500X500 nm2,using IEEE Micro Electro Mechanical
depth,micr nanotribology studies(AFM/FFM). Systems Workshop,SanDiego,
o(at 40uN) California,Feb 1996, p.97
Shear 69 GPa Equivalent to rigidity modulus,MCNC MUMPS W.Sharpe,B.Yuan,R.Vaidyanatha
Modulus Process, n,R.Edwards, Proceedings of the
URL:http://titan.me.jhu.edu/~sharpe/ptt/ptt.html, 10th MEMS
Value deducted from the Young's modulus (169 Workshop,Nagoya,Japan,1997,
GPa) and poisson ratio (0.22) by G = E{2(1 + v)} p.424-429
Strain,Co 0.006 .. LPCVD,thickness=230nm,oxide type=3.5um J.Appl.Phys,Vol.54,No.8,August
mpressive 0.007 PSG,unannealed, value measured locally by 1983, p.4675
observing the relaxation of a silicon overhang
over an oxide underlayer.
Strain,Co 0.0035 LPCVD,thickness=230nm,oxide type=3.5um J.Appl.Phys,Vol.54,No.8,August
mpressive .. PSG, value measured locally by observing the 1983, p.4675
0.0045 relaxation of a silicon overhang over an oxide
underlayer,annealed in N2 for 20 min at 1100C.
Strain,Co 0.0035 LPCVD,thickness=800 nm,oxide type=1.7 um J.Appl.Phys,Vol.54,No.8,August
mpressive .. PSG,unannealed, value measured locally by 1983, p.4675
0.0045 observing the relaxation of a silicon overhang
over an oxide underlayer.
Strain,Co 0.004 .. LPCVD,thickness=1.45um ,oxide type=1.1 um J.Appl.Phys,Vol.54,No.8,August
mpressive 0.005 thermally grown, unannealed,value measured 1983, p.4675
locally by observing the relaxation of a silicon
22
overhang over an oxide underlayer.
Stress,Co 1.4 .. LPCVD,thickness=230nm,oxide type=3.5um J.Appl.Phys,Vol.54,No.8,August
mpressive 1.6 GPa PSG,unannealed, value measured locally by 1983, p.4675
observing the relaxation of a silicon overhang
over an oxide underlayer.
Stress,Co 0.8 .. 1 LPCVD,thickness=230nm,oxide type=3.5um J.Appl.Phys,Vol.54,No.8,August
mpressive GPa PSG, value measured locally by observing the 1983, p.4675
relaxation of a silicon overhang over an oxide
underlayer,annealed in N2 for 20 min at 1100C.
Stress,Co 0.8 .. 1 LPCVD,thickness=800 nm,oxide type=1.7 um J.Appl.Phys,Vol.54,No.8,August
mpressive GPa PSG,unannealed, value measured locally by 1983, p.4675
observing the relaxation of a silicon overhang
over an oxide underlayer.
Stress,Co 0.9 .. LPCVD,thickness=1.45um ,oxide type=1.1 um J.Appl.Phys,Vol.54,No.8,August
mpressive 1.1 GPa thermally grown, unannealed,value measured 1983, p.4675
locally by observing the relaxation of a silicon
overhang over an oxide underlayer.
Stress,resi 290 Undoped,thickness=2.5um ,using wafer curvature IEEE Micro Electro Mechanical
dual MPa experiments, as film is deposited. Systems Workshop,SanDiego,
California,Feb 1996, p.345
Stress,resi 270 Undoped,thickness=5 um ,using wafer curvature IEEE Micro Electro Mechanical
dual MPa experiments, as film is deposited. Systems Workshop,SanDiego,
California,Feb 1996, p.345
Stress,resi 350 Undoped,thickness=2.5 um ,using wafer IEEE Micro Electro Mechanical
dual MPa curvature experiments, after undergoing a wet Systems Workshop,SanDiego,
oxidation at 1000C for 107min with the oxide California,Feb 1996, p.345
layer subsiquently stripped.
Stress,resi 190 Undoped,thickness=5 um ,using wafer curvature IEEE Micro Electro Mechanical
dual MPa experiments, after undergoing a wet oxidation at Systems Workshop,SanDiego,
1000C for 107min with the oxide layer California, Feb 1996, p.345
subsiquently stripped.
Tensile -5.2 .. Thick film,value is for thickness higher than Sensors & Actuators,A51(1995),
stress 18.8 10um,CVD film, deposited at RP(reduced press) p.11
MPa or atm press,temperature of deposition from 870
to 1000C,grown on top of a standard LPCVD
polysilicon on top of a 1um sacrificial SiO2
layer,assuming biaxial stress, value obtained from
relation between Raman shift and stress.
Wear 25 nm Lapped, scan size=500X500 nm2,using IEEE Micro Electro Mechanical
depth,micr nanotribology studies(AFM/FFM). Systems Workshop,SanDiego,
o(at 40uN) California,Feb 1996, p.97
Young's 201 LPCVD,n+type(phosphorous doped),obtained by J.mater.Res,Vol.
Modulus GPa nanodentation at a load of 0.2 mN and indentation 12,No.1,Jan1997, p.59
depth of 25 nm at peak load.
Young's 176 LPCVD,n+type(phosphorous doped),values J.mater.Res,Vol.
Modulus GPa obtained by nanodentation at a load of 15 mN and 12,No.1,Jan1997, p.59
indentation depth of 289 nm at peak load.
Young's 120 .. In-situ B-doped ,for thickness upto 10um IEEE Micro Electro Mechanical
Modulus 180 ,obtained by lateral resonant structure method. Systems Workshop,SanDiego,
GPa California,Feb 1996, p.347
Young's 152 .. Obtained from laser induced ultrasonic surface Thin solid films 290-291(1996),
Modulus 171 wave method for a thickness of 0.4-0.5 p.309
23
GPa um,choosing an intermediate density.
Young's 160 LPCVD film,calculated by using Load-Deflection Sensors and Actuators,20(1989),
Modulus GPa of composite rectangular p.138
membranes,thickness=0.2 um.
24
Figure 4.1 Layout of mechanical chip
25
Figure 4.2 3D model maked by ANSYS®
26
4.3. Finite Element Model of Comb Drive
27
CHAPTER 5 – ELECTRONIC SYSTEM
The mathematical model of the combdrive(Figure 5.1) is nonlinear. I tried to control it with a
linear PID controller but I couldn’t achieve a good result. (Figure 5.2)
28
Figure 5.3 Schematic of Op-Amp
29
Figure 5.4 Layout of Op-Amp
30
Figure 5.5 Schematic of PID Controller
31
CHAPTER 6 – CONCLUSION
As shown in the study nonlinearity of the comb drive makes it vey hard to control via
inexpensive PID controller in RF switch application. It may be more usefull to use it without a
32
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34