REPORT ON

VLSI DESIGN LAB

Under the guidance of:

Dr.Ramesh Kini
Mr. Chenna Reddy

Submitted by:
DHINKAR B. 12EC107
UJJWAL DHUSIA 12EC109

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

NATIONAL INSTITUTE OF TECHNOLOGY KARNATAKA, SURATHKAL
SRINIVASNAGAR-575025,MANGALORE,KARNATAKA,INDIA
April 2015

Contents
1

0.1 MODULE-1 REPORT : CIRCUIT SIMULATION WITH NGSPICE ......................................................................... 2

0.1.1 Lab 1: MOSFET input and output characteristics with parametric sweep ................................................. 3
0.1.2 LAB 2: Spice analysis of nmos inverter ............................................................................................................... 8
0.1.3 LAB 3: Study of MOS inverter with active load - NMOS and PMOS (pseudo) .......................................... 12
0.1.4 LAB 4: Study of CMOS Inverter ........................................................................................................................... 16
0.1.5 LAB 5: Depletion MOS and I vs V characteristics of PMOS ........................................................................... 19
0.1.6 LAB 6: study of CMOS gates ................................................................................................................................. 21
0.2 MODULE-2 REPORT : LAYOUT DESIGNING WITH MAGIC .............................................................................. 30
0.2.1 Layout design for CMOS inverter ....................................................................................................................... 31
0.2.2 Layout design for CMOS 3 input NAND gate .................................................................................................... 32
0.2.3 Layout design for CMOS 3 input NOR gate ....................................................................................................... 33
0.2.4 Layout designs for CMOS OR gate ...................................................................................................................... 35
0.2.5 Layout designs for function ab+c using CMOS ans Pseudo NMOS .............................................................. 36
0.2.6 Layout design for D - Latch .................................................................................................................................. 38
0.2.7 Layout design for D - Flip Flop............................................................................................................................ 39

0.1

MODULE-1 REPORT : CIRCUIT SIMULATION

WITH NGSPICE

Number of experiments performed : 5

0.1.1

Lab 1: MOSFET input and output characteristics

with parametric sweep

Objective: Study the input and output characteristic of NMOS transistor. Effect of length,width,VTO,
VSB,lambda, and temperature on the behavior of transistor.
============= CODE FOR VARYING LAMBDA ==============
m1 d g 0 0 my_nmos l = .5u w = 0.5u
*sources
v_dd d 0 dc 5 v_gg g
0 dc 3
.dc v_dd 0 5 0.1 v_gg 0 3 1
*response for varying lambda
.control foreach lmda .03 .06
.09 altermod m1
LAMBDA=$lmda run end .endc

Figure 1: Id vs Vdd (curve for varying lambda)

.control
foreach iter 1 2 3
setplot dc$iter plot v_dd#branch end
.endc
.end

Reason : The id vs Vdd curve is at first linear then becomes varies slowly in saturation region
due to channel length modulation which should be otherwise constant.

============= CODE FOR VARYING LENGTH ==============

*nmos charactorstic
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level1.txt
m1 d g 0 0 RITSUBN1 l=1u w=0.5u v_dd
d 0 dc 5 v_gg g 0 dc 5
.dc v_dd 0 5 0.01
*response for variable width
.control foreach length 1u 2u 5u alter m1 l=$length run end plot (dc1.v_dd#branch) (-dc2.v_dd#branch) (-dc3.v_dd#branch)
.endc

Figure 2: Id vs Vdd (curve for varying length)

========== CODE FOR VARYING TEMPERATURE ===========
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level1.txt m0 out in Vss
0 RITSUBN1 TEMP=27
*sources

Vgng Vss 0 dc 0 vdd

out 0 dc 5 Vin in 0 dc
5
.dc Vin 0 5 .1
.control foreach t1 27 50
100 alter m0 TEMP =$t1
run end .endc

Figure 3: Id vs Vdd (curve for varying temperature)

======= CODE FOR VARYING THRESHOLD VOLTAGE -VTO =======
*nmos characteristics varing length("current decreases as length is increased")
*include model files
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level1.txt
*netlist m1 drain gate 0 0 RITSUBN1 l=3u
w=0.5u
*define the sources vdd
drain 0 dc 5 vgg gate 0
dc 5
.dc vdd 0 5 0.1 vgg 0 5 1

*Computing the response for various width(len variable)

.control
foreach vth 0.5 1 3 alter m1
VTO = $vth
run end
.endc
*plotting the output for various width
.control
foreach iter 1 2 3
setplot dc$iter plot vdd#branch end .endc

Figure 4: Id vs Vdd (curve for vto)

===============CODE FOR VARYING Vsb===============

.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt m1 drn gate s

0 cmosn l=1u w=.5u
vdd drn 0 5 vin
gate 0 5 vss s 0 0
.dc vin 0 6 .1 vss 0 3 1
.control run plot vdd#branch
.end

Figure 5: Id vs Vdd (curve for varying vsb)

============== CODE FOR VARYING WIDTH ==============
*nmos characterstic
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level1.txt
m1 d g 0 0 RITSUBN1 l=1u w=0.5u v_dd
d 0 dc 5 v_gg g 0 dc 5
.dc v_dd 0 5 0.01
*response for variable width
.control foreach wid 1.6e-6 6.4e-6 96e-6 alter m1 w=$wid run end plot (dc1.v_dd#branch) (-dc2.v_dd#branch) (-dc3.v_dd#branch)
.endc

Figure 6: Id vs Vdd (curve for varying width)

0.1.2

LAB 2: Spice analysis of nmos inverter

Objective : Study the transfer function ,noise margin,effect on risetime ,falltime, propogation
delay ,power and energy consumed of a MOS inverter for various L,W of the transistor,load
capacitance and rise or fall time of input .

Figure 7: NMOS with resistive load

==== CODE FOR VARYING POWER WITH CHANGING RESISTANCE ====

*nmos characteristics with passive R load

.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt M1 vdd1 in 0
0 cmosn L=10U W=5U
R1 v_connect vdd1 1k v_dd1
v_connect 0 5
v_gs in 0 5
.control foreach resistance 100 1K 10K 100K
1Meg alter R1 = $resistance dc v_gs 0 5 0.1
run *plot
vdd1 end
let p1 = (v_connect*(-dc1.v_dd1#branch)) let p2 =
(v_connect*(-dc2.v_dd1#branch)) let p3 =
(v_connect*(-dc3.v_dd1#branch)) let p4 =
(v_connect*(-dc4.v_dd1#branch)) let p5 =
(v_connect*(-dc5.v_dd1#branch))
*dc2.vdd1 dc3.vdd1 dc4.vdd1 dc5.vdd1
.endc
.control
plot p1 p2 p3 p4 p5
.endc
.end

Figure 8: Id vs Vdd (curve for power consumption with varying load) ========
CODE FOR OUT vs IN FOR VARYING LENGTH =========
*nmos char

.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt
*netlist
m1 out in 0 0 cmosn l=1u w=0.5u

* input output voltage sourcev_dd vdd 0 dc 3.3 v_in in 0 dc

3.3 pulse(0 3.3 0.1n 1n 1n 10u 20u) r0 vdd out 50

* analysis request
.dc v_in 0 3.3 0.4 .tran .01u
80u
*compute response for various widths

10

.control foreach res 100 1k

100k alter r0 = $res run end
.endc
*iterations for various values
.control
foreach iter 1 2 3 setplot
dc$iter plot in out v_dd#branch
setplot tran$iter plot in out v_dd#branch end
.endc
.end

Figure 9: Id vs Vdd (curve for out vs in of invetor

11

Figure 10: Id vs Vdd (curve for out vs in of inveter for varying resistance

Figure 11: Id vs Vdd (transient response of inverter for varying resistance

0.1.3 LAB 3: Study of MOS inverter with active load - NMOS and PMOS (pseudo)
Objective : For a MOS inverter with active load ,study the transfr functions ,noise margins
,effect on risetime and falltime, propogation delay ,power and energy consumed with length
and width variations od pull up and pull down transistors.

12

Figure 12: Id vs Vdd (Pseudo NMOS

Figure 13: Id vs Vdd (NMOS with load enhancement

============= CODE FOR ACTIVE LOAD ================
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt
m1 dl dl out 0 cmosn l=.5u w=.5u m2 out in
0 0 cmosn l=.5u w=.5u
*sources m1 v_dd dl
0 dc 3.3 v_gg in 0 dc
3.3
.control
dc v_dd 0 3.3 .01 plot v_dd#branch vs 3.3-dl dc v_gg 0
3.3 .01 plot out vs in

.endc
.end

13

Figure 14: Id vs Vdd (transient response and out vs in for pseudo NMOS

============== CODE FOR PSEUDO MOS ===============

*pseudo nmos char
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt
*mos m1 out 0 vdd vdd cmosp l=1u w=0.2u
m2 out in 0 0 cmosn l=1u w=.5u
*sources
v_dd vdd 0 dc 3.3 v_in in 0
dc 3.3
.control foreach wd .1u
1u 5u alter m2 w= $wd
dc v_in 0 3.3 .01
run end plot dc1.out dc2.out
dc3.out
.endc
.end

14

Figure 15: Input output graph for pseudo NMOS

Figure 16: pseudo transfer characheristics

15

Figure 17: transfer characteristics pseudo MOS with varying load width

Figure 18: transfer characteristics for pseudo MOS with varing driver width

0.1.4

LAB 4: Study of CMOS Inverter

Objective : Study the transfer function, noise margin, effect on risetime ,falltime,propogation delay,
power of CMOS inverter with variation in L and W of pullup and pulldown transistors.

=========== Code for varing length in CMOS inverter ===========

*pseudo nmos char
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt

16

*mos m1 out in vdd vdd cmosp l=1u w=1.5u

m2 out in 0 0 cmosn l=1u w=.5u
*sources
v_dd vdd 0 dc 3.3 v_in in 0
dc 3.3
.control foreach ld 1u 5u
10u alter m2 l= $ld dc
v_in 0 3.3 .01
run end plot dc1.out dc2.out
dc3.out
.endc
.end

Figure 19: transfer characteristics of CMOS with varing driver length

=========== Code for varying width of CMOS inverter=============

*pseudo nmos char
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt
*mos m1 out in vdd vdd cmosp l=1u w=1.5u
m2 out in 0 0 cmosn l=1u w=.5u

17

*sources
v_dd vdd 0 dc 3.3 v_in in 0
dc 3.3
.control foreach wd .1u
1u 5u alter m2 w= $wd
dc v_in 0 3.3 .01
run end plot dc1.out dc2.out
dc3.out
.endc
.end

Figure 20: transfer characteristics of CMOS with varing driver width

============ Code for cascading CMOS transistor =============

*cmos cascadination
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt

18

m1 o_1 in 0 0 cmosn l=1u w=.5u m2 o_2

o_1 0 0 cmosn l=1u w=.5u m3 out o_2 0
0 cmosn l=1u w=.5u
*define resistors r_1
vdd o_1 100k r_2 vdd
o_2 100k r_3 vdd out
100k
*define sources v_dd vdd 0 dc 3.3 v_in in 0 dc 3.3 pulse(0 3.3
0.1n 1n 1n 50n 100n) .control tran .001n 200n plot in o_1 plot
o_1 o_2 plot o_2 out
.endc
.end

Figure 21: transient analysis for cascaded CMOS transistors

0.1.5

LAB 5: Depletion MOS and I vs V characteristics of PMOS

Objective : study the behaviour of depletion MOS and PMOS transistors.

19

============== CODE FOR DEPLETION MOS ===============

*include
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt
*nmos m1 vdd out out 0 mynmos l=1u
w=.2u m2 out in 0 0 cmosn l=1u w=.2u
.model mynmos nmos level=1 vto=-0.7
*sources
v_dd vdd 0 dc 3.3 v_in in 0
dc 3.3
.control
dc v_in 0 3.3 0.01
run end plot out
plot deriv(out)
.endc

Figure 22: transient analysis and derivative for depletion MOS

============ Code for PMOS I vs V characteristics ============

.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt

20

m1 drain in vdd -3.3 cmosp l=1u w=0.5u v_dd

vdd 0 dc -3.3 v_in in 0 dc -3.3 v_drain drain 0 dc
0
.control
dc v_in 0 -3.3 -.01 v_dd 0 -3.3 -1
run end plot v_dd#branch
.endc

Figure 23: I vs V characteristics for PMOS

0.1.6

LAB 6: study of CMOS gates

Objective : study the behaviour transfer function,noise margin, rise time ,fall time,
propogation delay,paower of a CMOS gates like NAND ,NOR functions (2 input AND gate ,2
input OR gate) with variations in L and W of pullup and pulldown transistors.

21

Figure 24: CMOS NAND gate

============== CODE FOR NAND GATE ================

*NAND Gate Implementation

.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt
M1 vdd1 A top1 0 cmosn L=1U W=10U
M2 top1 B 0 0 cmosn L=1U W=10U
M3 vdd1 A v_connect v_connect cmosp L=1U W=10U M4
vdd1 B v_connect v_connect cmosp L=1U W=10U
v_dd v_connect 0 3.3 v_gs1 A 0 PULSE(0 3.3 0 0
0 8NS 16NS) v_gs2 B 0 PULSE(0 3.3 0 0 0 16NS
32NS)
.control tran 0.1NS 32NS run end plot
tran1.A tran1.B tran1.vdd1
.endc
.end

22

Figure 25: transient response for NAND gate for input a=0,b=0

Figure 26: transient response for NAND gate for input a=0,b=1

23

Figure 27: transient response for NAND gate for input a=1,b=0
=============== CODE FOR AND GATE =================
top1 A v_connect v_connect cmosp L=1U W=10U *NAND Gate Implementation
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt
M1 vdd1 A top1 0 cmosn L=1U W=10U
M2 top1 B 0 0 cmosn L=1U W=10U
M5 stage2 vdd1 0 cmosn L=1U W=10U
M3 vdd1 A v_connect v_connect cmosp L=1U W=10U
M4 vdd1 B v_connect v_connect cmosp L=1U W=10U M6 stage2
vdd1 v_connect v_connect cmosp L=1U W=10U
v_dd v_connect 0 3.3 v_gs1 A 0 PULSE(0 3.3 0 0
0 8NS 16NS) v_gs2 B 0 PULSE(0 3.3 0 0 0 16NS
32NS)
.control tran 0.1NS 32NS run end plot tran1.A tran1.B
tran1.vdd1 tran1.stage2
.endc
.end

24

Figure 28: transient response for AND gate for input a=0,b=0

Figure 29: transient response for AND gate for input a=0,b=1

25

Figure 30: transient response for AND gate for input a=1,b=0
============== CODE FOR NOR GATE ================
*NOR Gate Implementation
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt
M1 vdd1 A 0 0 cmosn L=1U W=10U
M2 vdd1 B 0 0 cmosn L=1U W=10U
M3 top1 A v_connect v_connect cmosp L=1U W=10U M4
vdd1 B top1 top1 cmosp L=1U W=10U
v_dd v_connect 0 3.3 v_gs1 A 0 PULSE(0 3.3 0 0
0 8NS 16NS) v_gs2 B 0 PULSE(0 3.3 0 0 0 16NS
32NS)
.control tran 0.1NS 32NS run end plot
tran1.A tran1.B tran1.vdd1
.endc
.end

26

Figure 31: CMOS OR gate

Figure 32: transient response for NOR gate for input a=1,b=0

27

Figure 33: transient response for NOR gate for input a=1,b=1

================ CODE FOR OR GATE =================

*NOR Gate Implementation
.include /home/ACADEMICS/Projects/VLSI/t14y_tsmc_025_level3.txt
M1 vdd1 A 0 0 cmosn L=2U W=4U
M2 vdd1 B 0 0 cmosn L=2U W=4U
M5 stage1 vdd1 0 0 cmosn L=2U W=4U
M3 top1 A v_connect v_connect cmosp L=2U W=12U
M4 vdd1 B top1 v_connect cmosp L=2U W=12U M6 stage1 vdd1
v_connect v_connect cmosp L=2U W=12U

v_dd v_connect 0 3.3 v_gs1 A 0 PULSE(0 3.3 0.1p 0.1p 0.1p

4NS 8NS) v_gs2 B 0 PULSE(0 3.3 0.1p 0.1p 0.1p 8NS 16NS)
.control foreach wid 12u 24u 36u
28u alter M3 W=$wid alter M4
W=$wid

28

tran 0.1NS 20NS run

plot A B vdd1
end .endc
.end

Figure 34: transient response for OR gate for input a=0,b=0

Figure 35: transient response for OR gate for input a=0,b=1

29

Figure 36: transient response for OR gate for all input combinations

0.2

MODULE-2 REPORT : LAYOUT DESIGNING WITH MAGIC

Number of experiments performed : 2

30

0.2.1

Layout design for CMOS inverter

Figure 37: Layout design for CMOS inveter

Capacitances observed in the circuit :

C0 vss 0 2.8fF
C1 out 0 2.3fF
C2 vdd 0 2.8fF
C3 input 0 6.3fF

31

0.2.2

Layout design for CMOS 3 input NAND gate

Figure 38: Layout design for CMOS 3 input NAND gate

Figure 39: simulation results for CMOS 3 input NAND gate

Capacitances observed in the circuit:

C0 vss gnd! 9.4fF

C1 out gnd! 4.5fF
C2 b gnd! 6.3fF
C3 a gnd! 6.3fF
C4 vdd gnd! 4.9fF

32

0.2.3

Layout design for CMOS 3 input NOR gate

Figure 40: Layout design for CMOS 3 input NOR gate

Capacitances observed in the circuit:

C0 vss 0 8.8fF
C1 b 0 6.3fF
C2 a 0 6.3fF
C3 out1 0 11.2fF
C4 out 0 3.2fF

33

Figure 41: simulation results for CMOS 3 input NOR gate

34

0.2.4

Layout designs for CMOS OR gate

Figure 42: Layout design for OR CMOS

Capacitances observed in the circuit:

C0 vss 0 8.8fF
C1 b 0 6.3fF
C2 a 0 6.3fF
C3 out1 0 11.2fF
C4 out 0 3.2fF

35

0.2.5

Layout designs for function ab+c using CMOS ans Pseudo NMOS

Figure 43: Layout design for ab+c CMOS design

Figure 44: Layout design for ab+c pseudo NMOS

36

Figure 45: Simulation for ab+c pseudo NMOS

Capacitance values for Enhancement load:
C0 vss 0 9.4fF
C1 out 0 2.8fF
C2 c 0 6.3fF
C3 b 0 5.2fF
C4 a 0 5.2fF

Capacitance values for Pseudo NMOS

C0 b 0 3.5fF
C1 c 0 4.0fF
C2 a 0 3.7fF
C3 out 0 5.8fF
C4 vdd 0 7.0fF
C5 out1 0 8.9fF
C6 vss 0 26.8fFu

37

0.2.6

Layout design for D - Latch

Figure 46: Layout design for D - Latch

capacitance values:
C0 vdd d 2.5fF
C1 vdd a_29_n15# 2.1fF
C2 vdd a_7_26# 4.4fF
C3 vdd m1_n6_n8# 3.0fF
C4 vdd a_39_n16# 2.1fF
C5 vdd a_n7_8# 3.1fF
C6 m1_n6_n8# gnd! 2.9fF **FLOATING
C7 gnd gnd! 11.3fF
C8 a_7_n9# gnd! 4.4fF
C9 clk- gnd! 4.4fF
C10 out gnd! 3.4fF
C11 a_11_n13# gnd! 3.3fF
C12 a_n3_n13# gnd! 10.8fF
C13 a_n14_n13# gnd! 2.7fF
C14 a_39_n16# gnd! 7.5fF
C15 a_29_n15# gnd! 7.3fF
C16 d gnd! 7.0fF

38

0.2.7

Layout design for D - Flip Flop

Figure 47: Layout design for DFF

Figure 48: Simulation for DFF

capacitances values :
C0 vdd QS 2.1fF
C1 vss dpassslave 9.8fF
C2 vss clk 3.8fF
C3 QMn vss 2.4fF
C4 clk QM 2.6fF
C5 vss QS 2.1fF

39

C6 clkn QMn 2.5fF

C7 QMn clk 2.6fF
C8 vdd clk 5.8fF
C9 vdd QMn 27.5fF
C10 vss dpass 9.8fF
C11 QSn gnd! 6.1fF
C12 clknslave gnd! 7.5fF
C13 QM gnd! 6.1fF
C14 clkn gnd! 8.3fF
C15 QS gnd! 10.0fF
C16 dpassslave gnd! 13.2fF
C17 QMn gnd! 17.3fF
C18 dpass gnd! 13.2fF
C19 clk gnd! 23.7fF

40