Dept.

of Electronics Engineering
University of Engineering & Technology, Taxila

By Dr. Yaseer A. Durrani

Course Outline

(EN 5305)
5305) Semiconductor
Devices & Technology

Course Outline

Technology:
Introduction & Historical Perspective
Modern CMOS Technology
Crystal Growth, Wafer Fabrication & Basic Properties of
Si Wafers
Semiconductor Manufacturing
Lithography
Thermal Oxidation, Dopant Diffusion, Ion Implantation,
Thin film deposition, Etching
Back-End Technology
Device:
Semiconductor Devices
Dielectric Materials & Insulations
Magnetic Properties & Superconductivity
Optical properties of Materials

Reference Books

08%
12%
20%
20%
40%

Silicon VLSI Technology, Fundamentals, Practice &

Modeling, James D. Plummer, M.D.Deal, P. B. Griffin,
Pearson Publisher, ISDN: 978-81-317-2604-4

Semiconductor Devices, Kannaan Kano, Prentice Hall
Publisher, ISBN: 81-203-2877-9

Device Electronics for Integrated Circuits, R. S. Muller, T. I.
Kamins, ISBN: 978-81-265-1096-2

Assignments
Quizzes
Mid
Course Project/Case Studies
Final

Grading Policy

(EN 5305) Semiconductor

Devices & Technology
Introduction to Device &
Technology
By Dr. Yaseer A. Durrani
Dept. of Electronics Engineering
University of Engineering & Technology, Taxila

CMOS Techonlogy Scaling

Historical Trends & Future Predictions
Materials & Devices
Semiconductor Technology Families

Outline

Currently, technology scaling has a threefold objective:

Reduce the gate delay by 30% (43% increase in frequency)
Double the transistor density
Saving 50% of power (at 43% increase in frequency)

Evolution of Silicon Integrated Circuits since 1960s

Increasing: circuit complexity, packing density, chip size, speed & reliability
Decreasing: feature size, price per bit, power (delay) product

1990s

Integrated Circuit (IC) is an electronic network fabricated in a single piece of

semiconductor material
Semiconductor surface is subjected to various processing steps in which
impurities and other materials are added with specific geometrical patterns
Fabrication steps are sequenced to form three dimensional regions that act as
transistors & interconnects that form the switching or amplification network

CMOS Technology

1960s

How is scaling achieved?

All the device dimensions (lateral & vertical) are reduced by 1/
Concentration densities are increased by
Device voltages reduced by 1/ (not in all scaling methods)
Typically 1/ = 0.7 (30% reduction in the dimensions)

Technology Scaling

VddVdd /
LL/
W W/
toxtox /
XjXj /
NANA

Scaling variables are:

Supply voltage:
Gate length:
Gate width:
Gate-oxide thickness:
Junction depth:
Substrate doping:

Technology Scaling

Electric field across gate-oxide does not change when technology is scaled
called constant field scaling
If power supply voltage is maintained constant the scaling is called constant
voltage. In this case, electric field across gate-oxide increases as technology is
scaled down
Due to gate-oxide breakdown, below 0.8m only constant field scaling is used
Some consequences 30% scaling in constant field regime ( = 1.43, 1/ = 0.7):
Device/die area: W L (1/)2 = 0.49
In practice, uPs die size grows about 25% per technology generation
Transistor density: (unit area) /(W L) 2 = 2.04
In practice, memory density has been scaling as expected.
(not true for uPs)
Gate capacitance: W L / tox 1/ = 0.7
Drain current: (W/L) (V2/tox) 1/ = 0.7
Gate delay: (C V) / I 1/ = 0.7, Frequency = 1.43
In practice, uPs frequency has doubled every technology generation (2 to 3
years)! This faster increase rate is due to two factors:
Number of gate delays in clock cycle decreases with time (designs
become highly pipelined)
Advanced techniques reduce average gate delay 30% per generation

In practice, for uPs, active capacitance/unit-area only increases b/w 30%- 35%.
Twofold improvement in logic density b/w technologies is not achieved

Power: C V2 f (1/)2 = 0.49

Power density: 1/tox V2 f 1
Active capacitance/unit-area: Power dissipation is a function of operation
frequency, power supply voltage and of circuit size (number of devices)
If we normalize the power density to V2 f we obtain the active capacitance per
unit area for a given circuit. This parameter can be compared with oxide
capacitance per unit area: 1/tox = 1.43

Technology Scaling

Interconnects scaling:
Higher densities are only possible if the interconnects also scale.
Reduced width increased resistance
Denser interconnects higher capacitance
To account for increased parasitics & integration complexity more
interconnection layers are added:
Thinner & tighter layers local interconnections
Thicker & sparser layers global interconnections & power Interconnects are
scaling as expected

Technology Scaling
Parameter
Supply voltage (Vdd)
Length (L)
Width (W)
Gate-oxide thickness (tox)
Junction depth (Xj)
Substrate doping (NA)
Electric field across gate oxide (E)
Depletion layer thickness
Gate area (Die area)
Gate capacitance (load) (C)
Drain-current (Idss)
Transconductance (gm)
Gate delay
Current density
DC & Dynamic power dissipation
Power density
Power-Delay product

Technology Scaling

Constant Field
1/
1/
1/
1/
1/

1
1/
1/2
1/
1/
1
1/

1/2
1
1/3

Constant Voltage
1
1/
1/
Scaling
Variables
1/
1/

1/
1/2
Device
1/
Repercussion

1/2
3
Circuit

Repercussion
3
1/

Electron Beam Lithography (EBL)

Patterns are derived directly from digital data
Process can be direct: no masks
Pattern changes can be implemented quickly
However:
Equipment cost is high
Large amount of time required to access all the points on wafer
Optics technology
Technology node
248nm mercury-xenon lamp
180 - 250nm
248nm krypton-fluoride laser
130 - 180nm
193nm argon-fluoride laser
100 - 130nm
157nm fluorine laser
70 - 100nm
13.4nm extreme UV
50 - 70nm

Historical Trends & Future Predictions

0.25m in 1997
130 nm in 2002

Transition Region
Quantum Effects Dominate

Scaling + Innovation
(ITRS)
18 nm in 2018

Cell dimensions

Invention

2010

2013
22 nm

2016
18 nm

2018

Atomic dimensions

2007
32 nm

2040

2004
45 nm

2020
2002
65 nm

2000
90 nm

2000

130 nm

1998

Atomic Dimensions
1980
Year of Production
250 nm 180 nm

128G

10 nm

14,000

128G

0.5-0.7

13 nm

8800

64G

0.5-0.8

18 nm

4400

32G

06-0.9

25 nm

2200

16G

0.7-1-0

35 nm

1100

4G

0.8-1.1

53 nm

550

1G

0.9-1.2

70 nm

1.2-1.5

512M

256M

1.8-2.5

1.5-1.8

100 nm

Year

Device Scaling Over Time

~13% decrease in feature size each year (now: ~10%)
Era of Simple Scaling ~16% increase in complexity
each year (now:6.3% for P,
12% for DRAM)

We are now in a period where technology & device innovations are required.
Beyond 2020, new currently unknown inventions will be required
Feature Size
100m
10m

1m

0.1m
10nm
1nm
0.1nm
1960

Technology Node (half pitch)

MPU Printed Gate Length
DRAM Bits/Chip (Sampling)

Min Supply Voltage (volts)

MPU Transistors/Chip (x106)

Historical Trends & Future Predictions

14

Integrated Circuits

Al wires

Si O2

Si O2

Lithography to open
window in SiO2

Phosphorus diffusion
through the oxide mask

Contacts Alloyed
N

Mesa Etched

Double diffused Mesa technology

Solid State P diffusion

Solid State B diffusion

Invention of BJT transistor - 1947, Bell Labs

Exposed junctions had degraded surface properties and no possibility of
connecting multiple devices
Bell Lab, 1957: Double Diffused Process
Advantage: Connection of multiple devices but no ICs
Disadvantage: Degradation by exposed junctions at the surface
In 1950s, Alloy junction technology used. Ge used as crystal, III & V group atoms
used as dopants

Grown junction technology in 1950s

Planar Design of BTJs

Planar process (Hoerni-Fairchild, late 1950s). First passivated junctions

Boron diffusion
N

Boron diffusion

Beginning of Silicon technology & end of Ge devices

Implementation of masking oxide to protect junctions at Si surface
Oxidation possible for
Si not good for Ge
SiO2
Mask

Oxidation & out diffusion

P
N

Photolithography used for Pattern Formation

Exposure

Light

Photoresist application

Resist removal

Mask

Etching

Photoresist

Beginning of ICs in 1959

Basic photolithography process. IC pattern is transferred from mask to silicon by
printing it on wafer using light sensitive resist material

Deposited Film
Substrate
Film deposition
Etch mask

Development

Alignment of Layers

B Emitter

BJT
B

P
Resistor

0V

Oxide
Isolation

P+

Via

N+

TiN

Interconnect
M2

N+

M1OXIDE
P

P Well

NMOS

Silicide
P+

N Well

Schematic of ICs with Two Metal Levels

PMOS

ICs used photolithography & masking to fabricate that allows integration of

multiple devices side by side on a wafer

Bipolar Transistor & resistors made in base region

Accuracy of placement ~1/4 to 1/3 of linewidth being printed

Collector

IC is located at surface of Si wafer (~500m thick)

Vcc

P Resistor

Contact to collector
N

R=L/WRs

IC with 5-Level Metallization Scheme

Metal Planarization requires multiple metal layers

Metal Deposition

Patterning

Fill Dielectric

Planarization

Contact Vias

Contact Deposition

Computer Simulation Tools (TCAD)

Most of the basic technologies in silicon chip manufacturing can be simulated

Simulation is now used for:

Designing new processes and devices

Exploring the limits of semiconductor devices and technology (R&D)

Centering manufacturing processes

Solving manufacturing problems
Simulation of advanced
local oxidation process

Simulation of photoresist
exposure

Physical Devices

NPN & PNP Bipolar Junction Transistors

Field Effect Transistors (FET)

Metal-Oxide-Semiconductor FET (MOSFET)

Junction FET (JFET)

Others:

PN Junction, Resistor, Capacitor, Photo-Diode and Photo-Transistor

Materials & Devices

Semiconductors: Si, Ge, Compound (III-V, II-VI)

Si atom has:

Electron orbits 2-8-4 outer half filled

Covalent bound each (share electron) with 4
other Si atoms

Stable, high impedance (poor conductor)

Conduction in Pure Silicon Crystal

Energy added to free shared electron in lattice

Electron is free but leaves a net +ve charge or
hole trapped at missing electron site

Holes will attract & recapture electrons

Electrons will flow through lattice until
recombining with hole

Spontaneous thermal generation of holeelectron pairs always occurring; therefore, Si
can conduct poorly

21

Intrinsic Carrier Concentration

Intrinsic concentration of carriers for three common semiconductor materials

Si, at room temperature: ni~1.4 x 1010/ cubic cm

Si lattice has ~5x1022 atoms/cubic cm. Therefore temperature, only 1 in
3.5x1012 atoms involved

Electron & hole generation occur at elevated

temperature (above 0K). n=p
Energy Band Gap determines the intrinsic carrier
concentration. ni EgGe< EgSi< EgGaAs
For devices we need concentrations: n & p>>ni

Semiconductor Materials & Dopants

Intrinsic Semiconductors

Column 4 atoms in a lattice (Si, Ge)

Compound Semiconductors

Column 3-5 atoms (GaAs, InP)

Column 2-6 atoms (CdS, CdSe, CdTe, ZnO)

Dopants

Replace an intrinsic atom with one that as additional or fewer electrons in
outer orbit

For Silicon:

Fewer electrons: B

More electrons: P or As

24

Doped Si Lattice
B mobile hole
P or As mobile electron

Replace an atom




Donate an electron
Column 5 materials (P, As)

N-type Dopant

P-type Dopant

Accept electrons (additional holes)

Column 3 materials (B)

Lightly doped or heavily doped

Lightly doped N-, N--, P-, P

Heavily doped N+, N++, P+, P++

Resistivity Change with Doping

Resistivity (): In ohm-meters

R=.Length/Area= .L/A

Dopant Percentages

N-- or P-- : <1014 cm-3

1 in 5 x 108 cm-3

N- or P- : 1014 to 1016 cm-3

N or P : 1016 to 1018 cm-3

N+ or P+ : 1018 to 1020 cm-3

N++or P++ : >1020 cm-3

1 in 5 x 102 cm-3 (0.2%)

r=1/(qnn+qpp)

carrier mobility depends on scattering i.e.
dopants, lattice imperfections (defects) &
vibration (temperature)

nND

pNA

n>p

Donor & Acceptor Bands

T>0K

n=NAs

Band Model & Bond Model of Intrinsic (Undoped) Silicon

Band Model & Bond Model of n-type Silicon doped with As
Valence Band electrons bound in lattice
Conduction Band free electrons
Energy Gap (EG) amount of energy required to move an electron from EC to EV
Donors

ED close to EC

Little energy required to release electron
Acceptor

EA close to EV

Little energy required to release hole to valence band

n=p

Energy
Gap
Very small ionization
energies ED and EA
n=p=ni

Intrinsic Carrier Concentration

N=ND

Relatively constant over
operating range

From freezeout region

To processing temperature

At processing temperatures

Intrinsic carrier levels
dominate
ni=1.45x1010cm-3 at RT (300K)

nipi

n-type semiconductor
nn>>pn

intrinsic
semiconductor

Free carrier concentration Vs. Temp

Fermi-Dirac Probability

N-doped Si
Valence Band

below Ei

p=Na

Majority
carriers

above Ei

P-doped Si

p=type Semiconductor
n-type Semiconductor
n=Nd
Conduction Band
Majority carriers

Fermi level is the energy at which probability of

finding an electron F(Ef)=1/(1+1)=0.5

Probability of an electron occupy an energy state

Pauli Exclusion Principle (no two electrons can occupy same quantum state)

Ef Fermi level defined as the energy where the probability of finding an
electron is 50%

Ef Fermi Level

Centered for intrinsic: EF = Ei (Some electrons, some holes)

N-doped causes the level to rise: EF > Ei (More electrons, few holes)

P-doped causes the level to fall: EF < Ei (Few electrons, more holes)
Fermi Dirac probability function:
1
F(E) =
E EF
1 + exp(
)
kT
Intrinsic Semiconductor

EF Eg/2
Undoped

Distribution of Free Carriers

F(E)N(E)dE N

1+ exp(

E F EV
)
kT

1
E EF
)
kT

EF is a greatest use in semiconductors is in visualizing the electronic properties

(carrier concentrations & type) through the band diagram concept

To calculate n & p in a given situation, we need to know the probability of finding
them at energy level E, number & position of allowed energy levels

Allowable energy levels:

Energy levels exists above Ec & below Ev

Approximations for number of allowed electron energy levels are:

n=
EC

EV

2me 3 / 2
2mh 3 / 2
N
)
)
C = 2(
h2
h2

p = [1 F(E)]N(E)dE NV exp(

NV = 2(

Carriers in Bands

n=

1
E EF
)
kT

E EV
)
kT

1 + exp(

exp(

F (E )N( E)dE N

EC

[1 F(E )]N(E)dE N

EV

Electrons in Conduction Band

p=

EG= EC-EV Band gap

Heavy doping moves EF to EC

Holes in Valence Band

EC
EF
EV

Carrier Concentration
Charge Neutrality

NC

2 m e kT 3 / 2
= 2(
)
h2
2 m h kT 3 / 2
)
h2

N V = 2(

Energy Band Dependence on Temperature

Larger temperature weakens the bonding b/w atoms causing band gap energy EG (energy
needed to free e-h pairs) to decrease
EG shrinks with T

EG is temperature dependent
Conduction & valence band bend
Fermi level based on dopant concentration
Converge on Ei as temperature increases
EG(eV)=1.17-4 -4. 73x10-4T2/(T+636)1.16 - (3x10-4)T

Example

1000C

Doping by As & B results in p-type Si at RT

RT

p>>n

Electron-Hole Pair Generation

Energy levels for

shallow dopants are
close to the majority
carrier bands

In intrinsic Si at 1000C

npni at 1000C

When ionizing radiation strikes a semiconductor, it may excite an electron out of its energy
level and consequently leave a hole. This process is called EPH

EPH are constantly generated from thermal energy as well, in the absence of any external
energy source

EPH are also apt to recombine. Conservation of energy demands that these recombination
events, in which an electron loses an amount of energy larger than the band gap, be
accompanied by the emission of thermal energy (in the form of phonons) or radiation (in the
form of photons)

34

Trapping Phenomena

Intrinsic absorption & band-to-band recombination

Recombination levels
Trapping levels
35

Non-equilibrium free carriers can be generated in bulk semiconductor materials by various

processes, such as light absorption, high electric field, carrier injection through a barrier,
irradiation with high-energy particles

After the process which has generated the non-equilibrium carriers has ceased, the system
returns to equilibrium due to the annihilation of EPH by recombination. If the carriers that
recombine are both free (electron in conduction band & hole in valence band), their annihilation
process is called band-to-band recombination

If one of the carriers is captured on a localized state (i.e., it has a fixed position in
semiconductor) & other one is free called recombination on localized states

In recombination process, an amount of energy is released by emission of either a photon
(radiative recombination), or a phonon (non-radiative recombination), or secondary electron
(Auger recombination), etc.

Carrier captured on a localized state can recombine with an opposite sign carrier, if this
opposite sign carrier is subsequently captured on same localized state, or it can be released in
the corresponding band. The capture of second carrier with an opposite sign on same localized
state leads to annihilation of pair and it is called recombination on a localized state. If the
captured carrier is released in the band, the capture center is called a trap. Then the capture
process is called trapping and the release process is called detrapping
a.
b.
c.

Shockley, Read , Hall Recombination (SRH)

s=svthNit

U=

s(np n i2 )

SRH recombination is indirect transition of carriers b/w conduction & valence bands
Traps due to impurities result in intermediate trap states
Carriers transition to trap & then capture the opposite carrier at trap sate

Minority carrier concentration is a limiting element in capture process (lots of majority carrier
already trapped)

Recombination of Carriers

Si is an indirect semiconductor so indirect recombination (Shockley-Read-Hall) occurs
through traps located in the mid-gap

Carrier Recombination & Generation

Traps (defects, metal impurities) present in silicon act either to annihilate carriers
(recombination) or produce (generation) them

Surface of Si with traps lead to surface recombination velocity, which affects carrier lifetime
intrinsic Si

np>ni2 U>0 recombination

np<ni2 U<0 generation
lifetime trtg
Umax for ET=Ei

E Ei
SRH recombination/generation rate
p + n + 2n i cosh( T
)
kT
np ni2
n-type Si; a trap (below EF) is always U =
E
E
(p + n + 2ni cosh( T i ))
filled with electron=majority carrier
kT
and waits for a minority hole

tR=1/svthNt
Lifetime, capture cross section
thermal velocity, & traps

36

Forward biased diode

Semiconductor Devices

Reverse biased diode

Minority
electrons

Majority
electrons

n+ for low resistance

Electric field only

in depletion layer

Carriers move & create

depletion layers

Dopants positions
are fixed

p-n Diodes at Thermal Equilibrium

Majority
holes
Minority
holes

At thermal equilibrium charge neutrality

qN+dxn=qN-Axp leads to asymmetrical depletion layers

Uncompensated acceptors & donors

p-n Diodes at Thermal Equilibrium

p0nni2/ND

Reverse biased diode

(+ -)

I~exp(qV/kT)

Forward biased diode

Majority electrons (and holes) diffuse,

become minority carriers and produce large current

Minority electrons & holes drift

(small current)

(- +)

No current flows at thermal

equilibrium

Build-in voltage determined by doping on

both sides of the p-n junction

n0nND

p-n Diodes Under Bias

holes

p-n Diodes Under Forward Bias

Depletion layer shrinks

Electric field decreases

Junction potential decreases by Va

Energy barrier decreases by qVa

p-n Diodes Under Reverse Bias

Depletion layer spreads mainly to the low
doped side

Electric field increases

Junction potential increases by Va

Energy barrier increases by qVa

J~exp(qVa/kT)

J0A

1 dE i
q dx

Boltzman approximation

d
E
; = i
dx
q

E-field is where Ei=f(x)

Built-in voltage

E=

E =
Electrostatic potential

Poissons equation:

E peak =

divE =
0 Si
2Vb
xd

Minority & majority carriers

Junction at Thermal Equilibrium

Fermi potentials in
n and p-regions

p-n Diodes Under Bias

Carrier
Injection and Extraction

No recombination
assumed in the
SCR

Current distribution in a p-n diode

For the forward biasing condition

Breakdown of a p-n Diode

Zener effect

Eg

Avalanche effect

Breakdown Voltage of a p-n Diode

5-7V

Ebr field increases with ND but not very much

Wdepl~1/ND
Vbr=EbrWdepl so Vbr decreases with ND

Bipolar Transistors

VBE>0 VBC<0

IB

IC

a<1
n-p-n IC

Forward Operation Mode

Early Effect

small

Current Components

p-n-p
Individual
device

E-B junction is forward biased=injects minority carriers to base

Base (electrically neutral) is responsible for electron transport via diffusion (or drift
also if the build in electric field exists) to collector

C-B diode is reverse biased & collects transported carries

IE

IE=IEn+IEp

IC=aIE
IB=IEp+Ire
c

Extracted
holes electrons

Reverse bias

Bipolar Junction Transistors

Forwards bias

minority carriers
Injected
electrons

Early
Voltage

 =IC/IB

Operation of NMOS-FET

Collector-Base junction

Common Base

Bipolar Junction Transistors

Breakdown Voltages

Common Emitter

Current Gain =/1-

Kirk Effect

Recombination in the E-B Space Charge Region

MOSFET, NMOS & PMOS

VG>VT to creates
strong inversion

depletion

Linear Region, Low VD

Saturation Region, Channel Starts to Pinch-Off

Saturation Region,
channel shortens beyond pinch-off, L<L

Modern MOS Transistors

Lightly Doped Drain (LDD) used
to reduce the electric field in
drain depletion region & hot
carrier effects

Self aligned contacts decrease resistance

Source

Gate

LDD

Semiconductor Technology Families

Drain

isolation

First circuits were based on BJT as a switch because MOS circuits limitations
related to large oxide charges

1960s

1970s

1980s & beyond

Smaller power
consumption

Future Challenges
Silicide

Poly
Gate

Sidewall
Spacer

Drain

Gate
Dielectric

S/D Ext

Source

Drain

Gate

Technology Performance Boosters

3 stages for future development:

Source

Silicide
Rchan

Substrate

S/D Ext

Drain

???

Invention
Spin-based devices
Molecular devices
Rapid single flux quantum
Quantum cellular automata
Resonant tunneling devices
Single electron devices

Beyond Si CMOS
Materials/process innovations
IN 15 YEARS??
NOW
Device innovations
IN 5-15 YEARS

Traditional finFET (upper left), a trigate on SOI (upper right), trigate on bulk silicon (lower left)
and a pseudo-trigate on SOI (lower right)

Many other applications e.g. MEMs & many new device structures e.g. carbonnanotube
devices, all use basic silicon technology for fabrication

Source
SiO2
Gate

Future Challenges