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Assignments
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15%
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25%
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50%
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References
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Fun to Check
William F. Brinkman, Douglas E. Haggan, and William W. Troutman,
A History of the Invention of the Transistor and Where It Will Lead
Us, IEEE Journal of Solid-State Circuits, volume 32, no. 12,
December 1997, pp. 1858-1865
http://download.intel.com/newsroom/kits/22nm/pdfs/Intel_Transistor_Backgrounder.pdf
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Why Analog?
That is why analog and mixed-signal designers are still and hopefully
will be in demand for the foreseeable future.
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AFE
Data Converter
DSP
Example:
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Filter
ADC
DSP
http://www.intel.com/content/www/us/en/silicon-innovations/intel-tick-tock-model-general.html
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Intel 45 nm Process
http://blog.oregonlive.com/siliconforest/2007/11/intel11.pdf
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Background
1. Suggested Reading
2. Structure of MOS Transistors
3. Threshold Voltage
4. Long-Channel Current Equations
5. Regions of Operation
6. Transconductance
7. Second-Order Effects
8. Short-Channel Effects
9. MOS Layout
10. Device Capacitances
11. Small-signal Models
12. Circuit Impedance
13. Equivalent Transconductance
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Suggested Reading
Most of the material in this set are based on
Many of the figures in this set are from Design of Analog CMOS Integrated Circuits,
McGraw-Hill, 2001, unless otherwise noted.
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10
Transistor
Transistor stands for
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11
Simplistic Model
NMOS
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PMOS
VG high
Device is ON
D is shorted to S
Device is OFF
D & S are disconnected
VG low
Device is OFF
Device is ON
D & S are disconnected D is shorted to S
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Physical Structure - 1
Source and Drain terminals are identical except that Source provides
charge carriers, and Drain receives them.
MOS devices have in fact 4 terminals:
Source, Drain, Gate, Substrate (bulk)
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Physical Structure - 2
Charge Carriers are electrons in NMOS devices, and holes in
PMOS devices.
Electrons have a higher mobility than holes
So, NMOS devices are faster than PMOS devices
We rather to have a p-type substrate?!
LD: Due to Side Diffusion
Poly-silicon used instead of Metal
for fabrication reasons
Actual length of the channel (Leff) is less than the length of gate
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14
Physical Structure - 3
N-wells allow both NMOS and PMOS devices to reside on the
same piece of die.
15
Physical Structure - 4
MOS transistor Symbols:
electron
In NMOS Devices: Source Drain
Current flows from Drain to Source
Drain
Current flows from Source to Drain
Current flow determines which terminal is Source and which one
is Drain. Equivalently, source and drain can be determined based
on their relative voltages.
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16
Threshold Voltage - 1
Consider an NMOS: as the gate voltage is increased, the surface
under the gate is depleted. If the gate voltage increases more,
free electrons appear under the gate and a conductive channel is
formed.
(a) An NMOS driven by a gate voltage, (b) formation of depletion region, (c) onset of inversion,
and (d) channel formation
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Threshold Voltage - 2
Intuitively, the threshold voltage is the gate voltage that forces the
interface (surface under the gate) to be completely depleted of charge (in
NMOS the interface is as much n-type as the substrate is p-type)
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Threshold Voltage - 3
Analytically:
VTH MS 2 F
Qdep
C ox
Where:
N
K T
ln
q
n
sub
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4 q N
si
sub
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Threshold Voltage - 4
In practice, the native threshold value may not be suited for
circuit design, e.g., VTH may be zero and the device may be on for
any positive gate voltage.
Typically threshold voltage is adjusted by ion implantation into the
channel surface (doping P-type material will increase VTH of
NMOS devices).
20
The voltage of the surface under the gate, V(x), depends on the
voltages of Source and Drain.
If VDS is zero, VD= VS=V(x). The charge density Qd (unit C/m) is uniform.
Qd
L
L
L
If VDS is not zero, the channel is tapered, and V(x) is not constant. The
charge density depends on x.
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21
dQ dQ dx
Qd velocity
dt
dx dt
Velocity in terms of V(x):
dV
velocity E , E
dt
dV ( x)
velocity (
)
I
dx
Qd in terms of V(x):
VDS
x 0
V 0
dV ( x)
V ( x) VTH ] n
dx
W
1 2
[(VGS VTH )VDS VDS
]
L
2
EECE 488 Set 1: Introduction and Background
22
If VDS VGS-VTH we say the device is operating in triode (or linear) region.
Terminology:
I D n Cox
W
L
1 2
W
L
Overdrive Voltage Effective Voltage VGS VTH Veff
Aspect Ratio
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23
W
n C ox VGS VTH
L
I D n C ox
RON
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VDS
ID
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When VDS is more than VGS VTH the channel is pinched off, and the
horizontal electric field produces a current.
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L'
VGS VTH
x 0
V 0
I D dx
ID
1
W
n Cox (VGS VTH ) 2
2
L'
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I D I DS
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W
n C ox VGS VTH VDS ; if VGS VTH , VDS 2(VGS VTH ) ( Deep Triode)
L
W
1 2
n C ox VGS VTH VDS VDS
; if VGS VTH , VDS VGS VTH (Triode)
L
2
1 C W (V V ) 2 ; if V V , V V V ( Saturation )
GS
TH
GS
TH
DS
GS
TH
2 n ox L
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I D I SD
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W
p C ox VSG VTH VSD ; if VSG VTH , VSD 2(VSG VTH ) ( Deep Triode)
L
W
1 2
p C ox VSG VTH VSD VSD
; if VSG VTH , VSD VSG VTH (Triode)
L
2
1 C W (V V ) 2 ; if V V , V V V ( Saturation )
SG
TH
SG
TH
SD
SG
TH
2 p ox L
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Regions of Operation - 1
Regions of Operation:
Cut-off, triode (linear), and saturation (active or pinch-off)
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Once the channel is pinched off, the current through the channel is
almost constant. As a result, the I-V curves have a very small slope in
the pinch-off (saturation) region, indicating the large channel
resistance.
EECE 488 Set 1: Introduction and Background
29
Regions of Operation - 2
The following illustrates the transition from pinch-off to triode region for
NMOS and PMOS devices.
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Regions of Operation - 3
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Regions of Operation - 4
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Regions of Operation - 5
Example:
For the following circuit assume that VTH=0.7V.
When is the device on?
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33
Transconductance - 1
It makes sense to define a figure of merit that indicates how well the
device converts the voltage to current.
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I D
VGS VDS Const.
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Transconductance - 2
Example:
Plot the transconductance of the following circuit as a function of VDS
(assume Vb is a constant voltage).
Transconductance in triode:
W
1 2
n C ox VGS VTH VDS VDS
VGS
L
2
VDS Const.
W
n C ox VDS
L
gm
Transconductance in saturation:
VGS
W
1
2
n C ox (VGS VTH )
L
2
W
n C ox (VGS VTH )
L
gm
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VDS Const.
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Transconductance - 3
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2 ID
W
W
g m n Cox (VGS VTH ) 2 n Cox I D
L
L
VGS VTH
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2 F where g
2 q si N sub
Cox
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Body Effect - 2
Example:
Consider the circuit below (assume the transistor is in the active region):
If body-effect is ignored, VTH will be constant, and I1 will only depend on
VGS1=Vin-Vout. Since I1 is constant, Vin-Vout remains constant.
No Body Effect
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Body Effect - 3
Example:
For the following Circuit sketch the drain current of transistor M1 when VX
varies from - to 0. Assume VTH0=0.6V, g=0.4V1/2, and 2F=0.7V.
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1
W
(VGS VTH ) 2 where L' L- L
2
L'
1
1 L
L
L
L' L L L 1 L
1 1
1
1 L 1 VDS
L L
L' L
Assuming
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VDS
we get:
1
2
W
1
W
2
(VGS VTH ) 2 n Cox VGS VTH 1 VDS
L'
2
L
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represents the relative variation in effective length of the channel for a given
increment in VDS.
Transconductance:
In Triode:
gm
g m n Cox
I D
VGS VDS Const.
W
VDS
L
2 ID
W
W
(VGS VTH ) 2 n Cox I D
L
L
VGS VTH
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2 ID
W
W
(VGS VTH ) 1 VDS 2 n Cox I D 1 VDS
L
L
VGS VTH
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W
VGS VTH
L
I D
W
Therefore :
VDS
L
In Triode Region:
In Saturation Region:
I D n Cox
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DS
1 2
VDS
2
1
W
nCox VGS VTH 2 1 VDS
2
L
I D
1
W
So we get :
nCox VGS VTH 2
VDS 2
L
ID
Therefore :
I D
W W
VDS
L
L2
Changing the length of the device from L1 to 2L1 will flatten the ID-VDS
curves (slope will be divided by two in triode and by four in saturation).
Increasing L will make a transistor a better current source, while
degrading its current capability.
Increasing W will improve the current capability.
EECE 488 Set 1: Introduction and Background
42
Sub-threshold Conduction
VBE
VT
VGS
VT
In MOS: I D I 0 e
In BJT devices the current drops faster (one decade for approximately
each 60mv of drop in VGS).
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Photolithography (Lithography)
Used to transfer circuit layout information to the wafer
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Self-Aligned Process
Why source and drain junctions are formed after the gate oxide
and polysilicon layers are deposited?
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Back-End Processing
Oxide spacers and silicide
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49
Back-End Processing
Contact and metal layers fabrication
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Back-End Processing
Large contact areas should be avoided to minimize the
possibility of spiking
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51
MOS Layout - 1
It is beneficial to have some insight into the layout of the MOS devices.
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52
MOS Layout - 2
Example:
Figures below show a circuit with a suggested layout.
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The same circuit can be laid out in different ways, producing different
electrical parameters (such as different terminal capacitances).
53
Device Capacitances - 1
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54
Device Capacitances - 2
C W LC , C
1. Oxide Capacitance:
t
ox
ox
ox
ox
q si N sub
4F
2.
Depletion Capacitance:
C 2 C dep W L
3.
Overlap Capacitance:
4.
Junction Capacitance:
Sidewall Capacitance:
C jsw
Bottom-plate Capacitance:
C jun
Cj
C j0
VR
1
C5 C6 C j C jsw
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Device Capacitances - 3
In Cut-off:
1. CGS: is equal to the overlap capacitance. C C C
2. CGD: is equal to the overlap capacitance. C C C
3. CGB: is equal to Cgate-channel = C1 in series with Cchannel-bulk = C2.
4.
5.
GS
ov
GD
ov
C DB C6
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Device Capacitances - 4
In Triode:
The channel isolates the gate from the substrate. This means that if VG
changes, the charge of the inversion layer are supplied by the drain
and source as long as VDS is close to zero. So, C1 is divided between
gate and drain terminals, and gate and source terminals, and C2 is
divided between bulk and drain terminals, and bulk and source
terminals.
C
1. CGS: CGS Cov 21
2. CGD: CGD Cov C1
2
3. CGB: the channel isolates the gate from the substrate. CGB 0
C
C SB C5 2
4. CSB:
2
C
5. CDB:
C DB C6 2
2
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Device Capacitances - 5
In Saturation:
The channel isolates the gate from the substrate. The voltage across
the channel varies which can be accounted for by adding two
equivalent capacitances to the source. One is between source and
gate, and is equal to two thirds of C1. The other is between source and
bulk, and is equal to two thirds of C2.
2
1. CGS: C C 3 C
2. CGD:
C C
3. CGB: the channel isolates the gate from the substrate. C 0
2
4. CSB:
C C C
3
5. CDB:
C C
GS
ov
GD
ov
GB
SB
DB
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Device Capacitances - 6
In summary:
Cut-off
Saturation
CGS
C ov
C ov
C1
2
2
C ov C1
3
CGD
C ov
C ov
C1
2
C ov
CGB
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Triode
C1 C 2
CGB C1
C1 C 2
CSB
C5
C5
C2
2
2
C5 C 2
3
CDB
C6
C6
C2
2
C6
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Importance of Layout
Example (Folded Structure):
Calculate the gate resistance of the circuits shown below.
Folded structure:
Decreases the drain capacitance
Decreases the gate resistance
Keeps the aspect ratio the same
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60
Passive Devices
Resistors
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Passive Devices
Capacitors:
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Passive Devices
Capacitors
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Passive Devices
Inductors
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Latch-Up
Due to parasitic bipolar transistors in a CMOS process
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In general, ID is a function of VGS, VDS, and VBS. We can use this Taylor
series approximation:
Taylor Expansion : I D I D 0
I D
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I D
I
I
VGS D VDS D VBS second order terms
VGS
VDS
VBS
VDS
I D
I
I
VGS D VDS D VBS g m VGS
g mb VBS
VGS
VDS
VBS
ro
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Taylor approximation: I D
Partial Derivatives:
W
1
W
2
(VGS VTH ) 2 n Cox VGS VTH 1 VDS
L'
2
L
I D
I
I
VGS D VDS D VBS
VGS
VDS
VBS
I D
W
n C ox (VGS VTH ) 1 VDS g m
VGS
L
I D
1
W
1
n C ox (VGS VTH ) 2 I D
VDS 2
L
ro
I D
I D VTH
W
g
g
g m
2 2 F VSB
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g m g mb
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Small-Signal Model:
i D g m vGS
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v DS
g mb v BS
ro
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Small signal model including all the capacitance makes the intuitive
(qualitative) analysis of even a few-transistor circuit difficult!
For intuitive analysis we try to find a simplest model that can represent
the role of each transistor with reasonable accuracy.
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69
Circuit Impedance - 1
R
X
V
I
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Circuit Impedance - 2
Example:
i
X
v
v
g v
r
r
X
R
X
GS
v
r
i
X
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Circuit Impedance - 3
Example:
i
X
v
v
g v g v g v g v
r
r
X
GS
mb
BS
R
X
mb
v
1
1 1
r
1
i
g g
g g
r
X
mb
mb
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Circuit Impedance - 4
Example:
v
v
i g v g v v g
r
r
r
GS
R
X
v
1
1
r
1
i
g
g
r
X
R r
X
1
1
1
g
g
g
m
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Circuit Impedance - 5
Example:
v
v
g v g v g v g v
r
r
X
GS
mb
BS
1
v g g
r
X
R
X
mb
mb
v
1
1
1 1
r
r
1
i
g g
g g
g g
r
X
mb
mb
mb
R r
X
1
1
1
1 1
g g
g g
g g
g g
m
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mb
mb
mb
mb
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Equivalent Transconductance - 1
GS
DS
IN
G
m
i
v v
OUT
IN
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OUT
OUT
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Equivalent Transconductance - 2
Example:
OUT
g v g v
G
m
GS
i
g
v
IN
OUT
IN
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Equivalent Transconductance - 3
Example:
v v v v i
IN
OUT
GS
GS
OUT
g v g v
m
GS
mb
BS
v
g (v i
r
S
IN
OUT
R ) g i
S
mb
OUT
R
r
OUT
R
1 g R g R g v
r
i
g
g r
G
R
v
r r g R g R R
1 g R g R
r
i
OUT
mb
IN
OUT
IN
mb
mb
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Short-Channel Effects
Threshold Reduction
Drain-induced barrier lowering (DIBL)
Mobility degradation
Velocity saturation
Hot carrier effects
Substrate current
Gate current
Output impedance variation
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Hot carriers may hit silicon atoms at high speed and cause
impact ionization
The resulting electron and holes are absorbed by the drain and
substrate causing extra drain-substrate current
Really hot carriers may be injected into gate oxide and flow out
of gate causing gate current!
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