Switching Circuits & Logic Design

Latches and Flip-Flops (FF)

Professor Chien-Mo James Li
Graduate Institute of Electronics Engineering
National Taiwan University
Logic Design

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Objective of this Chapter

Introduce basic building blocks of sequential circuits

Logic Design

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Outline

Introduction.
Set-Reset Latch.
Gated D Latch.
Edge-Triggered D Flip-Flop.
S-R Flip-Flop.
J-K Flip-Flop.
T Flip-Flop.
Flip-Flops with Additional Inputs.
Summary

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Logic Design

Sequential Circuits
Combinational circuits
Outputs depend on the present input only
Sequential Circuits
Outputs depends on not only the present input
But also the past sequence of inputs
Q: examples of sequential circuits?

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Feedback
Output of a circuit feeds to its own input
Example

One inversion
Results in oscillation

Fig. 11-1

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Feedback (2)
Two inversion

Results in 2 stable states

Memory effect
Not very useful because cannot change memory

Fig. 11-2

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Outline

Introduction.
Set-Reset Latch.
Gated D Latch.
Edge-Triggered D Flip-Flop.
S-R Flip-Flop.
J-K Flip-Flop.
T Flip-Flop.
Flip-Flops with Additional Inputs.
Summary.

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Logic Design

Set-Reset Latch
S=Set; R=Reset; Q = output
S=1, R=0 Q=1
S=0, R=0 Q=stable state

Fig. 11-3

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SR Latch (2)
S=0, R=1 Q=0
S=0, R=0 Q= sable state

Fig. 11-4

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SR Latch (3)
Drawn in cross-coupled form

Fig. 11-5
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What if S=R =1?

Set and Reset both 1 not allowed
Reasons

P and Q not complement when S=R=1

After S and R change to 0, oscillation starts

Fig. 11-6

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Logic Design

Timing Diagram
Fig 11-7
is delay

Fig. 11-7
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SR Latch Operation
Table 11-1
Present State

S(t)
0
0
0
0
1
1
1
1

Q = Q(t)
Next State
Q+ = Q(t+ )
Next-state equation
Q+ = S+RQ
Aka. Characteristic equation
Present output
P=SQ

Next state Q+

R(t)
0
0
1
1
0
0
1
1

Q(t)
0
1
0
1
0
1
0
1

Present output P

SR
00

SR
01

SR
11

SR
10

SR
00

SR
01

SR
11

SR
10

Logic Design

Q(t+)
0
1
0
0
1
1
-

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Table. 11-1

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Kmap for Q+

Fig. 11-8
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Application of SR Latch
Switch debouncing
Double throw switch

One end is R
One end is S

Fig. 11-9

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Another Possible Implementation

Fig 11-10
Use NAND
Bubbles at input indicates zero is active

Fig. 11-10
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Another Possible Implementation

Q

Q+

Fig. 11-10

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Outline

Introduction.
Set-Reset Latch.
Gated D Latch.
Edge-Triggered D Flip-Flop.
S-R Flip-Flop.
J-K Flip-Flop.
T Flip-Flop.
Flip-Flops with Additional Inputs.
Summary.

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Gated D Latch
D=Data input
G = gate input
When G=1
Latch is transparent
When G=0
Output Q remains unchanged
Fig 11-11

Fig. 11-11

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Logic Design

Symbol and Truth Table

Symbol of D Latch

Fig 11-12
G

Q+

Fig. 11-12 (a)

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K Map
Fig 11-12

K map
Characteristic eq.
Q+ = GQ+GD

Fig. 11-12

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Outline

Introduction.
Set-Reset Latch.
Gated D Latch.
Edge-Triggered D Flip-Flop.
S-R Flip-Flop.
J-K Flip-Flop.
T Flip-Flop.
Flip-Flops with Additional Inputs.
Summary.

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William H. Eccles (1875 1966, G. British)

Eccles is a British physicist and pioneer in radio communication
He helped in the design of the first long wave radio station, and

became involved in the early work of the British Broadcasting

Company (later the BBC) following its establishment in 1922.
Eccles invented the term Diode to
describe an evacuated glass tube
containing two electrodes; an anode and
a cathode.
1919, William Eccles and F. W. Jordan
patented the Eccles-Jordan trigger circuit
(now called flip-flop), which consists of
two tubes, for binary counters.
William Eccles was a Fellow of the Royal
Society (FRS). He was President of the
Physical Society from 1928 to 1930, and
President of the Institute of Electrical
Engineers (IEE) in 1926.
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Food for Thought

Why Eccles-Jordan trigger circuits becomes flip flops?

?
=

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Edge-Triggered D Flip-Flop (D-FF)

Rising edge of clock (aka. positive edge)
clock 01 transition
Falling edge of clock (aka. negative edge)
clock 1 0 transition
Rising-edge triggered FF: output changes at rising edge of clock
Indicated by a triangle sign at clock input
Falling-edge triggered FF: output changes at falling edge of clock
Indicted by a triangle and a bubble at clock input
Active edge: the edge where FF is triggered (either rising or falling)
D
Q
Q+
0
0
0
0
1
0
1
0
1
1
1
1

Char. Eq. Q+=D

Logic Design Fig. 11-13

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Fig. 11-13 ( c )

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Timing Diagram
Negative-edge triggered D-FF

Output Q changes only at clock falling edge

Fig. 11-14

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Making a FF using Two Latches

Rising-edge trigger D flip-flop
Q: Real life example ?

Fig. 11-15
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Setup Time and Hold Time

Setup time (Tsu)
time that D must be stable before the active edge of clock
Hold time (Th)
time that D must hold the same value after active edge of clock
Propagation time (Tp)
time from clock changes until output Q changes

Fig. 11-16

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Example Circuit
Fig 11-17

Tsu = 3ns
Tp = 5ns
Td = 2ns (inverter)
Th not used in example

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Setup Time Violation

Clock period = 9ns

Clock rising edge occurs = 0ns, 9ns, 18ns
Required D arrival time = 6ns (9ns-3ns)
Actual D arrival time = 7ns (5ns + 2ns)
Actual D arrival time later than required arrival time
setup time violation problem !!!

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No Setup Time Violation

Clock period = 15ns

Clock rising edge occurs = 0ns, 15ns, 30ns
Required D arrival time = 12ns (15ns-3ns)
Actual D arrival time = 7ns (5ns + 2ns)
Actual D arrival time earlier than required arrival time
No setup time violation

0 1 2
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3 4 5 6 7 8 9

10 11 12 13 14 15

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Minimum Clock Period

Clock period = 10ns

Clock rising edge occurs = 0ns, 10ns, 20ns
Required D arrival time = 7ns (10ns-3ns)
Actual D arrival time = 7ns (5ns + 2ns)
Actual D arrival time equal to required arrival time
Just make

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Real Life Example

Tsu = amount of time to sit down before clock rings

Th = amount of time to hold your seat after clock rings
Tp = amount of time for dull lecture after clock rings
Td = amount of time to walk on campus after lecture ends

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Outline

Introduction.
Set-Reset Latch.
Gated D Latch.
Edge-Triggered D Flip-Flop.
S-R Flip-Flop.
J-K Flip-Flop.
T Flip-Flop.
Flip-Flops with Additional Inputs.
Summary.

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S-R Flip Flop

SR FF Similar to SR Latch
But SR FF has clock input
Q changed only after active clock edge
Symbol
Fig 11-18

S=R=0; no state change

S=1, R=0; set Q=1
S=0, R=1; reset Q=0
S=R=1; not allowed

Fig. 11-18
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Master-Slave Flip-Flop
Fig 11-19

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Master-Slave FF vs. Edge-Triggered FF

Edge-triggered FF
input values sensed only at the active edge
Input can change while clock is low
Master-slave FF
When clock is low, Change of input can result in wrong output

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Outline

Introduction.
Set-Reset Latch.
Gated D Latch.
Edge-Triggered D Flip-Flop.
S-R Flip-Flop.
J-K Flip-Flop.
T Flip-Flop.
Flip-Flops with Additional Inputs.
Summary.

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J-K FF
JK FF is extended version of SR FF
J~S; K~R
J=K=1 is allowed
Truth table (Fig 11-20 b)
Characteristic equation
Q+ = JQ+KQ
If Q=0, J=1, then Q+=1
If Q=1, K=1, then Q+=0

J
0
0
0
0
1
1
1
1

K
0
0
1
1
0
0
1
1

Q
0
1
0
1
0
1
0
1

Q+
0
1
0
0
1
1
1
0

Fig. 11-20 (b)

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Logic Design

Timing Diagram
Fig 11-20 , positive-edge trigger

tp = propagation time

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Fig. 11-20

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Master-Slave JK FF
Very similar to SR FF
Feedback from Q to input
S and R inputs are never high at same time
S1=JQClk
R1=KQClk
Q changes on rising edge

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Outline

Introduction.
Set-Reset Latch.
Gated D Latch.
Edge-Triggered D Flip-Flop.
S-R Flip-Flop.
J-K Flip-Flop.
T Flip-Flop.
Flip-Flops with Additional Inputs.
Summary.

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T Flip-Flop
Aka Toggle flip-flop
Truth table (Fig 11-22 b)
Characteristic eq.
Q+ = TQ+TQ=T XOR Q
Symbol

Q+

Fig. 11-22 (b)

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Timing Diagram of T FF
Fig 11-23

tp = propagation time

Fig. 11-23

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Two Implementations of TFF

Fig 11-24

(a): Use JK FF
(b): use D FF

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FFT
What is wrong with Fig 11-24(b)?

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Outline

Introduction.
Set-Reset Latch.
Gated D Latch.
Edge-Triggered D Flip-Flop.
S-R Flip-Flop.
J-K Flip-Flop.
T Flip-Flop.
Flip-Flops with Additional Inputs.
Summary.

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Flip-flop with Clear and Preset

Clear forces output =0
Preset forces output =1
Very useful when circuit powered up
Example
Fig 11-25 D-FF with Clear and Preset

Fig. 11-25
Logic Design

CK

PreN

ClrN Q+

Not allow

1 preset

0 clear

0,1,

No
change

= falling edge of clock

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Asynchronous Clear and Preset

What is asynchronous clear and preset?
Their operation does not depend on the clock edges
Not like D and Q are synchronous to clock edges

Fig. 11-26

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Synchronous vs. Asynchronous *not in exam

Synchronous

Clear and preset wont take effect until active clock edge occurs

preN
clk
Q

Asynchronous

clear and preset take effect immediately independent of clock

preN
clk
Q
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Gated Clock
Mission
Design a flip-flop that holds data for two clock periods
How?
Gated clock may be a solution
En=1; FF is clocked
En=0; FF is not clocked
Synchronization problems of gated clock
1 gate delay of AND induced clock skew
2. hazards in En cause wrong operation
Clock is very sensitive and be careful when you play trick on it!

Fig. 11-27
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Better Design
Insert MUX
When CE = 0; FF not changed
When CE=1, FF changes
No synchronization problem
Fig 11-27

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FFT
Q: we consider hazard on En as synchronization problem

How about hazard on clock?

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Summary
Many types of memory elements introduced today
Flip-flops
Latches
Two stable states
0/1
They are called bistables in some books
Char. Equations
11-1 to 11-6
(S-R latch or flip-flop )
Q+ = S + RQ (SR=0)
(gated D latch )
Q+ = GD + GQ
+
(D flip-flop )
Q =D
(D-CE flip-flop )
Q+ = DCE + Q CE
(J-K flip-flop )
Q+ = JQ + KQ
(T flip-flop )
Q+ = T Q = TQ + TQ

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(11-1)
(11-2)
(11-3)
(11-4)
(11-5)
(11-6)

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Food for Thought

How do you choose which FF to Use?
Complexity

DFF < SRFF < JKFF < TFF

Solution see next chapter

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Next Time
ch 9 Multiplexers Decoders and PLD
ch 11 Latches and FF
ch 12 Registers and Counters
ch 13 Analysis of Clock Sequential Ckts
ch 14 Derivation of State Graphs and
Tables
ch 16 Sequential Ckt Design
ch 18 Ckts for Arith. Operations
final exam

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