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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 55, NO. 8, AUGUST 2008

Class-D Audio Amplifier Using 1-Bit Fourth-Order

Delta-Sigma Modulation
Kyoungsik Kang, Jeongjin Roh, Member, IEEE, Youngkil Choi, Hyungdong Roh, Hyunsuk Nam, and
Songjun Lee, Member, IEEE

AbstractWe present the design of a single-chip delta-sigma

(16) modulation-based class-D amplifier for driving head-

phones in portable audio applications. The presented class-D

amplifier generates output pulse signals using a single-bit
fourth-order high-performance 16 modulator. To achieve a high
signal-to-noise ratio and ensure system stability for a large input
range, the locations of the modulator loop filter poles and zeros are
optimized and thoroughly simulated. The test chip is fabricated
using a standard 0.18- m CMOS process. The active area of the
chip is 1.6 mm2 . It operates for the signal bandwidth from 20 Hz
to 20 kHz. The measured total harmonic distortion plus noise at
the 32-
load terminal is 0.022% from a single 3-V power supply.

Fig. 1. Block diagram of the designed class-D amplifier.

Index TermsClass-D amplifier, delta-sigma (16) modulator,

power switching, pulsewidth modulation (PWM), signal-to-noise
ratio (SNR), total harmonic distortion plus noise (THD+N).

I. INTRODUCTION

ORTABLE multimedia products, which are being developed these days, such as PDAs, mobile phones, and MP3
players, have embedded audio systems to drive earphones, headphones, etc. Since the power consumption of the audio system
accounts for a considerable portion of the total power consumption of the product, a highly efficient power amplifier is needed
to reduce the total power consumption of the product [1].
The pulsewidth modulation (PWM), which is one of the modulation techniques of class-D amplifiers, compares the input
signal with a triangular wave carrier, and generates wave PWM
signals to drive the switching stage. Due to such benefits as its
simplicity and low switching frequency, PWM has been used
widely as a traditional class-D modulation technique. However,
one shortcoming of the class-D amplifier that uses PWM is that
it generates many harmonic and nonharmonic distortions because it is implemented as an open loop circuit. On the other
modulation technique, which is one
hand, the delta sigma
of the modulation techniques spotlighted these days, is used in
this paper to overcome the disadvantage of the PWM technique.
The
modulator is configured as a closed loop using negative
feedback, and has the noise-shaping property that removes the
nonlinear components in the audio band [2].
This paper describes the design and implementation of a
class-D amplifier for 32- headphone load resistance [1], which
is composed of a
modulator with the input-feedforward
Manuscript received July 5, 2007; revised December 31, 2007. First published
July 18, 2008; last published August 13, 2008 (projected). This work was supported by the research fund of Hanyang University (HY-2006-S), Ansan, Korea.
This paper was recommended by Associate Editor P. K. T. Mok.
The authors are with the Department of Electrical Engineering, Hanyang University, Ansan 426-791, Korea (e-mail: jroh@hanyang.ac.kr).
Digital Object Identifier 10.1109/TCSII.2008.922457

Fig. 2. Fourth-order single-loop single-bit

fier.

16 modulator for class-D ampli-

structure, a power-efficient switching stage, and an LC filter, and

summarizes the conclusions based on the measurement results.
II. PROPOSED CLASS-D AMPLIFIER
Fig. 1 shows a block diagram of a class-D amplifier based on
modulator. In our class-D amplifier, the
the presented
modulator converts the differential audio signal into a high-frequency modulated binary signal. The two-level digital bit stream
of the modulated signal is made proportional to the amplitude of
the input audio signal, and then the modulated bit stream drives
the power transistors of the class-D output stage. Further, the
output signals of the power transistors are converted to amplified audio signals after the high frequency components are removed by a low-pass filter (LPF) outside the chip.
modulation-based class-D amplifier configuration is
The
shown in Fig. 1. In a typical open-loop class-D amplifier, noise
and distortion occur in the output signals due to the use of power
switches. However, the proposed circuit can reduce such effects using the noise-shaping property, which is a benefit of a
modulator as described above. The
modulator is composed of a loop filter, which is generally a cascade of integrators,
followed by a quantizer. By including the power switch in the
feedback loop, the quantization noise, together with the power
switching noise, can be shaped and removed out of the signal
band [3].

1549-7747/$25.00 2008 IEEE

KANG et al.: CLASS-D AUDIO AMPLIFIER USING 1-BIT FOURTH-ORDER DELTA-SIGMA MODULATION

Fig. 3. Fully differential switched capacitor implementation of the proposed

III.
A. Designed

729

16 modulator for class-D amplifier.

MODULATOR ARCHITECTURE
Modulator

The block diagram of the designed

modulator architecmodulator is composed of a
ture is presented in Fig. 2. The
fourth-order distributed-feedforward (DFF)-type loop filter with
local feedback around a pair of integrators and a single-bit comparator. An input-feed-forward modulator is an attractive architecture because the input signal does not pass through the loop
filter. As a result, the imperfections of the loop filter will have
less impact on the input signal quality. Also, as the signal swings
inside the loop filter decrease, the headroom requirements of the
internal circuit that forms the loop filter are relaxed for an easier
design [4][6].
Nowadays high-order modulators are preferred in order to
achieve higher signal-to-noise ratio (SNR). However, stability is
a major concern for high-order modulators. We have selected a
fourth-order architecture as a trade-off, then optimized the poles
and zeros to guarantee both high SNR and stability at the same
time. The extensive behavioral simulations with nonidealities
were done to guarantee the stability and the performance of the
modulator [7]. The oversampling ratio (OSR) was set to 80 and
the clock frequency to 3.2 MHz for the peak SNR of 103 dB in
an ideal behavioral simulation. If the OSR is too high, switching
power dissipation increases and efficiency decreases due to the
capacitances and resistances of the power transistors. To design
an optimal
modulator, a behavioral simulation using Matlab
was performed. To improve the SNR of the modulator within
the audio band, a couple of zeros of the noise transfer function
(NTF) were placed from dc to the edge of the signal band
.
The optimized , which has been determined using the behavioral simulation, is 21.3 kHz. To keep the
noise below the
quantization noise level, the sampling capacitor of the first integrator is decided carefully to provide a sufficiently low noise
floor for more than 100 dB dynamic range (DR) in our design
[8].
B. Circuit Implementation
We selected the fully differential switched capacitor architecture to implement the
modulator, shown in Fig. 3. The fully
differential architecture reduces sensitivity to undesired noises,
such as the substrate, clock feedthrough, and power supply
noise. No active summing element is required because the summing circuit in front of the quantizer can be implemented using

TABLE I
CAPACITOR VALUES OF THE PROPOSED

16 MODULATOR

switched capacitors. In a single-bit implementation, the sign

of the summer output is the only important information for the
single-bit quantizer. Therefore, additional amplification can be
omitted. The power loss of a passive summer is relatively small
compared to an active summer. In addition, the inaccuracy
caused by switched capacitive summer can be noise shaped in
the same way as the quantization noise [9].
Thus, only four opamps are required in our switched capacitor circuit implementation. All the capacitor values are summarized in Table I. For the accurate matching of the capacitors, all
integrating and sampling capacitors are implemented with unit
capacitors for common-centroid layout. In order to make the capacitors as the multiple of the unit capacitance, the modulator
coefficients are tuned using Matlab behavioral simulations with
circuit nonidealities [7]. The first and second integrators have
the unit capacitors of 0.2 pF, and the other blocks including the
feedforward path have the unit capacitors of 0.05 pF.
Shown in Fig. 4 is the opamp with the common-mode
modulator. The key
feedback (CMFB) circuit used in the
requirement for opamps used in switched capacitor-type
modulators is speed. Therefore, a fully differential folded-cascode opamp with high gain and high speed characteristics
that can drive large capacitive loads was chosen. Table II
summarizes the SPICE simulation results of the opamp used
in the first integrator with the small-signal equivalent load
capacitance [10]. The target specifications are determined by
extensive behavioral simulations with circuit nonidealities [7].
The opamps used in subsequent integrators are based on the
same folded-cascode architecture, but the bias current and
transistor sizes are scaled, which results in scaled performance.
The main drawback associated with the folded-cascode amplifier is its limited output swing. In our circuit design, this
drawback is overcome by reducing the voltage swing of the integrators using the input-feedforwarded modulator architecture,
as explained earlier. A drawback of the fully differential opamp

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 55, NO. 8, AUGUST 2008

Fig. 4. Schematic of the opamp with CMFB circuit.

Fig. 6. Power switching stage and LC filter.
TABLE II
SIMULATED PERFORMANCE OF THE OPERATIONAL AMPLIFIER

Fig. 5. Schematic of the comparator with SR latch.

is the need for a CMFB circuit to set the output common-mode

voltage. We chose a switched capacitor CMFB circuit, shown
in Fig. 4, in our design because of its simplicity and power efficiency.
The single-bit quantizer is realized using a regenerative comparator and an SR latch, shown in Fig. 5. The whole comparator
is a purely dynamic circuit controlled by clocks, which is very
power efficient. For a single-bit
modulator, the requirement
for the quantizer is relaxed because imperfections in this stage
undergo noise-shaping of the modulator [8]. The following SR
latch drives the power switching stage.
IV. POWER SWITCHING STAGE AND LC FILTER
The power switching stage of the class-D amplifier consists
of the gate driver and power transistors, as shown in Fig. 6.

The devices of the power switching stage are driven to act as

a switch that connects either the power supply voltage or the
ground. In this design, the driving signal is the output of the
modulator. The
modulated signal is reconstructed at
a higher power level by the power transistors. Similar to the
modulator, the power switching stage was implemented as
a differential topology, with CMOS transistors only, instead of
the high-voltage DMOS process in consideration of cost and
process complexity.
One of the key factors that determine the efficiency of class-D
amplifiers is the shoot-through current that occurs in the power
transistors and another is the on-resistance value of the power
transistors. For high power efficiencies, the on-resistances of the
pMOS and nMOS power transistors are designed to be 0.5 and
0.4 , respectively, in our circuit implementation.
Because the on-resistance of the pMOS and nMOS power
transistors is very low, power dissipation and heat generation
increase due to the shoot-through current that occurs when two
transistors are turned on simultaneously. To avoid the occurrence of this shoot-through current, we have used a gate-driver
block with nonoverlapping time. The nonoverlapping time prevents the shoot-through condition by forcing both transistors
off. The gate driver block is composed of a nand gate, a nor
gate, two dead-time controllers, and two final buffers. Because
the final buffer size of the gate driver is still significantly large
to drive the power transistors, we have used dead-time controllers with nonoverlapping time for the buffers. In order to
achieve sufficient design margin for process, voltage and temperature (PVT) corners, we designed the nonoverlapping time of
the dead-time controllers as 3.8 ns in typical conditions. Therefore, nonoverlapping time of the gate driver is 8 ns, about twice
the dead-time controllers nonoverlapping time.
V. MEASUREMENT RESULTS
The class-D amplifier is fabricated using a standard 0.18- m
1Poly-4Metal CMOS process with metalinsulatormetal
(MIM) capacitors and threshold voltage of 0.45 and 0.43 V
for pMOS and nMOS, respectively, and its die photograph is
shown in Fig. 7. The power supply rails are used as a 1-bit

KANG et al.: CLASS-D AUDIO AMPLIFIER USING 1-BIT FOURTH-ORDER DELTA-SIGMA MODULATION

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TABLE III
PERFORMANCE COMPARISON

Fig. 8. Measured PSD of the class-D output.

Fig. 7. Die photograph of the class-D amplifier. The active area of the chip is
1200 m 1350 m.

DAC output voltage, which is defined as a full scale of the input

signal.
Fig. 8 shows the measured PSD of the final class-D output.
With a headphone load resistance of 32- [1] and a 4.3 dB,
1-kHz sine wave as an input, we measured the class-D amplifier
chip using the audio analyzer. The measured peak SNR is 80 dB.
Fig. 9 plots the graph of the total harmonic distortion plus noise
(THD N) versus the input frequency of a 4.3-dB sine wave.
Fig. 10 shows the graph of THD+N versus the input level of a
1-kHz sine wave. The lowest THD N is 0.022% at the 4.3-dB
input level. As the input level goes beyond 1-V
, the class-D
amplifiers performance degrades, and the THD N rises.
Table III summarizes and compares the performances of our
chip and the state-of-the-art class-D amplifiers. As can be seen
from the table, the class-D amplifiers vary in their applications,
test condition, power dissipation, technology, and choice of architecture, making a fair comparison difficult. Although some
class-D amplifiers achieve high efficiency and low THD N, the
power dissipation of the modulator itself is very large also. Our
class-D amplifier demonstrates overall good performance compared to other circuits.

Fig. 9. THD+N versus input frequency.

VI. CONCLUSION
This paper presents the circuit design and measurement results for an integrated class-D audio amplifier fabricated using
a standard 0.18- m CMOS process. The use of a single-bit
fourth-order DFF
modulator, instead of the conventional
pulsewidth modulator, achieves high quality audio performance
with a THD N of 0.022%. An efficiency of 77% can be
achieved with a 32- load using a single power supply of 3 V.

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 55, NO. 8, AUGUST 2008

Fig. 10. THD+N versus input level.

As shown in Table III, the proposed circuit has a small area of

the chip, and the modulator power consumption is smaller than
type. The proposed circuit
that of a class-D amplifier of the
is expected to be useful as a headphone driver for portable
audio applications.
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