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Spring 2010
CS302- Digital Logic Design (Session - 4)
Time: 90 min
Marks: 58
For Teacher's Use Only
Q
1
2
3
No.
Marks
Q No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Marks
Q No.
Marks
Q No.
Marks
Q No.
Marks
Total
Question No: 1
( Marks: 1 )
8-bit
16-bit
32-bit
64-bit
Question No: 2 ( Marks: 1 ) - Please choose one
The decimal 17 in BCD will be represented as _________
11101
11011
10111
11110
Question No: 3 ( Marks: 1 ) - Please choose one
The basic building block for a logical circuit is _______
A Flip-Flop
A Logical Gate
An Adder
None of given options
Question No: 4 ( Marks: 1 ) - Please choose one
The output of the expression F=A.B.C will be Logic ________ when A=1, B=0,
C=1.
Undefined
One
Zero
No Output as input is invalid.
Question No: 5
( Marks: 1 )
________ is invalid number of cells in a single group formed by the adjacent cells in Kmap
2
8
12
16
Question No: 6
( Marks: 1 )
AND
OR
NOT
XOR
Question No: 7 ( Marks: 1 ) - Please choose one
___________ is one of the examples of synchronous inputs.
J-K input
EN input
Preset input (PRE)
Clear Input (CLR)
Question No: 8 ( Marks: 1 ) - Please choose one
___________ is one of the examples of asynchronous inputs.
J-K input
S-R input
D input
Clear Input (CLR)
Question No: 9
( Marks: 1 )
Question No: 10
( Marks: 1 )
__________occurs when the same clock signal arrives at different times at different
clock inputs due to propagation delay.
Race condition
Clock Skew
Ripple Effect
None of given options
0000
1101
1011
1111
Question No: 12
( Marks: 1 )
In a state diagram, the transition from a current state to the next state is determined by
( Marks: 1 )
State assignment
State reduction
Next state table
State diagram
Question No: 14
( Marks: 1 )
________ is used to simplify the circuit that determines the next state.
State diagram
Next state table
State reduction
State assignment
( Marks: 1 )
1
0
A
( Marks: 1 )
Question No: 19
( Marks: 1 )
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the
nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit
first.)
1100
0011
0000
1111
Question No: 20 ( Marks: 1 ) - Please choose one
The address from which the data is read, is provided by _______
Depends on circuitry
None of given options
RAM
Microprocessor
Question No: 21
( Marks: 1 )
Question No: 22
( Marks: 1 )
Look Up Table
Local User Terminal
Least Upper Time Period
None of given options
Question No: 23
( Marks: 1 )
The voltage gain of the Inverting Amplifier is given by the relation ________
Vout / Vin = - Rf / Ri
Vout / Rf = - Vin / Ri
Rf / Vin = - Ri / Vout
Rf / Vin = Ri / Vout
Question No: 24
( Marks: 1 )
Resolution
Accuracy
Quantization
Missing Code
Question No: 25
( Marks: 1 )
Asynchronous up-counter
Asynchronous down-counter
Synchronous up-counter
Synchronous down-counter
Question No: 26
( Marks: 1 )
n+2 (n plus 2)
2n (n multiplied by 2)
2n (2 raise to power n)
n2 (n raise to power 2)
Question No: 27
( Marks: 2 )
input
S
0
0
1
1
Question No: 28
R
0
1
0
1
output
QT +1
QT
0
1
INVALID
( Marks: 2 )
Two state assignments are given in the table below. Identify which state assignment
is best and why?
States
A
B
C
D
State assignment 1
00
01
11
10
State assignment 2
00
01
10
11
Ans:
State assignment 2 is best assignment it Minimizes the number of state variables that dont
change in a group of related states
.
Question No: 29
( Marks: 2 )
( Marks: 2 )
Question No: 32
( Marks: 3 )
Question No: 33
( Marks: 3 )
to charge and discharge a capacitor. The capacitor can not retain the charge, therefore it
has to be periodically charged
through a refresh cycle.
Question No: 35
Q0
1
1
1
0
0
0
Next State
Q2
1
0
0
1
1
0
Q1
1
0
1
0
1
1
Q0
1
1
0
0
0
1
( Marks: 5 )
Question No: 36
( Marks: 5 )
Ans:
Performances characteristics of D/A converters are determined by five parameters
are as follow:
1. Accuracy
2. Setting time
3. Monotonicity
4. Linearity
5. Resolution
FINALTERM EXAMINATION
Fall 2009
CS302- Digital Logic Design (Session - 4)
Ref No: 1129612
Time: 120 min
Marks: 75
For Teacher's Use Only
Q
1
2
3
No.
Marks
Q No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Marks
Q No.
Marks
Q No.
Marks
Q No.
Marks
Q No.
Marks
41
Total
( Marks: 1 )
I Only
IV Only
I and IV only
II and III only
Question No: 3 ( Marks: 1 ) - Please choose one
NAND gate is formed by connecting _________
AND Gate and then NOT Gate
NOT Gate and then AND Gate
AND Gate and then OR Gate
OR Gate and then AND Gate
Question No: 4 ( Marks: 1 ) - Please choose one
Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate
the output of the NAND gate will be _____
Zero
One
Undefined
No output as input is invalid
Question No: 5
( Marks: 1 )
The capability that allows the PLDs to be programmed after they have been installed on
a circuit board is called __________
( Marks: 1 )
!
&
#
$
Question No: 7 ( Marks: 1 ) - Please choose one
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop
0
1
Invalid
Input is invalid
Question No: 8
( Marks: 1 )
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flipflop ___________
( Marks: 1 )
In asynchronous digital systems all the circuits change their state with respect to a
common clock
True
False
Question No: 11
( Marks: 1 )
( Marks: 1 )
Question No: 14
( Marks: 1 )
Following Is the circuit diagram of mono-stable device which gate will be replaced by
the red colored rectangle in the circuit.
AND
NAND
NOR
XNOR
Question No: 15
( Marks: 1 )
In ________ outputs depend only on the combination of current state and inputs.
Mealy machine
Moore Machine
State Reduction table
State Assignment table
Question No: 16
( Marks: 1 )
________ is used to simplify the circuit that determines the next state.
State diagram
Next state table
State reduction
State assignment
( Marks: 1 )
( Marks: 1 )
( Marks: 1 )
2
4
8
16
Question No: 21
( Marks: 1 )
1
0
A
( Marks: 1 )
1110
0111
1000
1001
Question No: 24
( Marks: 1 )
( Marks: 1 )
In order to synchronize two devices that consume and produce data at different rates,
we can use _________
( Marks: 1 )
If the FIFO Memory output is already filled with data then ________
Question No: 27
( Marks: 1 )
The process of converting the analogue signal into a digital representation (code) is
known as ___________
Strobing
Amplification
Quantization
Digitization
Question No: 28
( Marks: 1 )
is an example of ______________
( Marks: 1 )
Q2 :=Q1 OR X OR Q3
The above ABEL expression will be
Q2:= Q1 $ X $ Q3
Q2:= Q1 # X # Q3
( Marks: 1 )
The top of the stack contains the value 5 and bottom of the stack contains the
value 6, a pop (read data from stack) operation was executed, which value
would be read?
Question No: 33
( Marks: 2 )
What kind of devices use the shift register based First In First Out (FIFO)
memory?
Ans:
FIFOs are used commonly in electronic circuits for buffering and flow control
which is from hardware to software. In hardware form a FIFO primarily consists
of a set of read and write pointers, storage and control logic. Storage may be
SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of nontrivial size a dual-port SRAM is usually used where one port is used for writing
and the other is used for reading.
Question No: 34
( Marks: 2 )
Ans:
A negative edge triggered flip-flop generates an output pulse in response to a
negative edge of a clock signal. A first set of nodes receives data input signals,
and a second set of nodes receives select input signals for selecting one data
input signal as a selected data input signal. The clock node receives the clock
signal which has a positive edge and a negative edge. A header circuit connects
to the second set of nodes and to the clock node, and integrates the clock signal
with the select input signals to generate at least one control signal. A pulse
generator circuit connects to the first set of nodes, the header circuit and the
output node. The pulse generator circuit generates an output pulse on the output
node in response to a control signal and the selected data input signal.
The operation and truth table for a negative edge-triggered flip-flop are the same
as those for a positive except that the falling edge of the clock pulse is the
triggering edge.
Propagation Delay Time - is the interval of time required after an input signal
has been applied for the resulting output change to occur.
Set-Up Time - is the minimum interval required for the logic levels to be
maintained constantly on the inputs (J and K, or S and R, or D) prior to the
triggering edge of the clock pulse in order for the levels to be reliably clocked into
the flip-flop.
Hold Time - is the minimum interval required for the logic levels to remain
on the inputs after the triggering edge of the clock pulse in order for the levels to
be reliably clocked into the flip-flop.
( Marks: 3 )
A serial-in/serial-out shift register has a clock input, a data input, and a data output from
the last stage. In general, the other stage outputs are not available Otherwise, it would be
a serial-in, parallel-out shift register..
The waveforms below are applicable to either one of the preceding two versions of the
serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift
register temporarily stores 3-bits of data and delays it by three clock periods from input to
output.
Question No: 38
( Marks: 5 )
A flash analogue to digital converter is the fastest type of converter we use. Like
the successive approximation converter it works by comparing the input signal to
a reference voltage, but a flash converter has as many comparators as there are
steps in the comparison. An 8-bit converter, therefore, has 2 to the power 8, or
256, comparators.
The resistor net and comparators provide an input to the combinational logic
circuit, so the conversion time is just the propagation delay through the network it is not limited by the clock rate or some convergence sequence. It is the fastest
type of ADC available, but requires a comparator for each value of output (63 for
6-bit, 255 for 8-bit, etc.) Such ADCs are available in IC form up to 8-bit and 10-bit
flash ADCs (1023 comparators) are planned. The encoder logic executes a truth
table to convert the ladder of inputs to the binary number output.
Question No: 39 ( Marks: 5 )
Explain the next-state table with the help of a table for any sequential circuit.
Ans
State Table
The state table representation of a sequential circuit consists of three sections
labelled present state, next state and output. The present state designates the
state of flip-flops before the occurrence of a clock pulse. The next state shows
the states of flip-flops after the clock pulse, and the output section lists the value
of the output variables during the present state.
Present state
Q1Q2
00
01
10
11
11
11
10
10
01
00
11
10
0
0
0
0
0
0
1
1
Ans:
The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as
synchronous inputs because they have effect on the outputs (Q and not-Q) only in step, or
in sync, with the clock signal transitions. These extra inputs that I now bring to your
attention are called asynchronous because they can set or reset the flip-flop regardless of
the status of the clock signal. Typically, they're called preset and clear:
When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of
any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop
will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock.
So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get
an invalid state on the output, where Q and not-Q go to the same state, the same as our
old friend, the S-R latch! Preset and clear inputs find use when multiple flip-flops are
ganged together to perform a function on a multi-bit binary word, and a single line is
needed to set or reset them all at once.
Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or
active-low. If they're active-low, there will be an inverting bubble at that input lead on the
block symbol, just like the negative edge-trigger clock inputs.
Sometimes the designations "PRE" and "CLR" will be shown with inversion bars above
them, to further denote the negative logic of these inputs:
Data signals
Method of how information is transferred; usually it is transferred in binary code
in signals or pulses.
A phase lock oscillator includes a phase discriminator that develops an error
signal by comparing a clock from a voltage controlled oscillator with incoming
random data bits. In the absence of data, the phase lock oscillator is inactive.
However, when data is sensed, a logic and delay network in the phase
discriminator develops an error voltage of suitable polarity and amplitude,
indicative of the lead or lag between the data and clock signals. The error voltage
is applied to the voltage controlled oscillator to modify the frequency and phase
of the clock. Furthermore, first and second integrations are provided by the
phase discriminator and an integrator respectively so that the steady state phase
error is held close to zero.
It is known that spurious variations in the mechanical or electrical parameters of
a storage system cause unwanted displacement and shift of the signal being
processed, thus necessitating frequency and phase compensation. To this end,
synchronizing systems, servosystems, phase lock oscillator circuits, separation
circuits and the like are employed.
FINALTERM EXAMINATION
Fall 2009
CS302- Digital Logic Design (Session - 4)
Ref No: 1129612
Time: 120 min
Marks: 75
For Teacher's Use Only
Q
1
2
3
No.
Marks
Q No.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Marks
Q No.
Marks
Q No.
Marks
Total
Q No.
33
Marks
Q No.
Marks
41
34
35
36
37
38
39
40
( Marks: 1 )
I Only
IV Only
I and IV only
II and III only
Question No: 3 ( Marks: 1 ) - Please choose one
NAND gate is formed by connecting _________
AND Gate and then NOT Gate
NOT Gate and then AND Gate
AND Gate and then OR Gate
OR Gate and then AND Gate
Question No: 4 ( Marks: 1 ) - Please choose one
Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate
the output of the NAND gate will be _____
Zero
One
Undefined
No output as input is invalid
Question No: 5
( Marks: 1 )
The capability that allows the PLDs to be programmed after they have been installed on
a circuit board is called __________
( Marks: 1 )
!
&
#
$
Question No: 7 ( Marks: 1 ) - Please choose one
If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop
0
1
Invalid
Input is invalid
Question No: 8
( Marks: 1 )
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flipflop ___________
( Marks: 1 )
In asynchronous digital systems all the circuits change their state with respect to a
common clock
True
False
Question No: 11
( Marks: 1 )
( Marks: 1 )
Question No: 14
( Marks: 1 )
Following Is the circuit diagram of mono-stable device which gate will be replaced by
the red colored rectangle in the circuit.
AND
NAND
NOR
XNOR
Question No: 15
( Marks: 1 )
In ________ outputs depend only on the combination of current state and inputs.
Mealy machine
Moore Machine
State Reduction table
State Assignment table
Question No: 16
( Marks: 1 )
________ is used to simplify the circuit that determines the next state.
State diagram
Next state table
State reduction
State assignment
( Marks: 1 )
( Marks: 1 )
( Marks: 1 )
2
4
8
16
Question No: 21
( Marks: 1 )
1
0
A
( Marks: 1 )
1110
0111
1000
1001
Question No: 24
( Marks: 1 )
( Marks: 1 )
In order to synchronize two devices that consume and produce data at different rates,
we can use _________
( Marks: 1 )
If the FIFO Memory output is already filled with data then ________
Question No: 27
( Marks: 1 )
The process of converting the analogue signal into a digital representation (code) is
known as ___________
Strobing
Amplification
Quantization
Digitization
Question No: 28
( Marks: 1 )
Asynchronous up-counter
Asynchronous down-counter
Synchronous up-counter
Synchronous down-counter
Question No: 29 ( Marks: 1 )
(A + B)(A + B + C)(A + C)
is an example of ______________
( Marks: 1 )
Q2 :=Q1 OR X OR Q3
The above ABEL expression will be
Q2:= Q1 $ X $ Q3
Q2:= Q1 # X # Q3
( Marks: 1 )
The top of the stack contains the value 5 and bottom of the stack contains the
value 6, a pop (read data from stack) operation was executed, which value
would be read?
Question No: 33
( Marks: 2 )
What kind of devices use the shift register based First In First Out (FIFO)
memory?
Ans:
FIFOs are used commonly in electronic circuits for buffering and flow control
which is from hardware to software. In hardware form a FIFO primarily consists
of a set of read and write pointers, storage and control logic. Storage may be
SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of nontrivial size a dual-port SRAM is usually used where one port is used for writing
and the other is used for reading.
Question No: 34
( Marks: 2 )
Ans:
A negative edge triggered flip-flop generates an output pulse in response to a
negative edge of a clock signal. A first set of nodes receives data input signals,
and a second set of nodes receives select input signals for selecting one data
input signal as a selected data input signal. The clock node receives the clock
signal which has a positive edge and a negative edge. A header circuit connects
to the second set of nodes and to the clock node, and integrates the clock signal
with the select input signals to generate at least one control signal. A pulse
generator circuit connects to the first set of nodes, the header circuit and the
output node. The pulse generator circuit generates an output pulse on the output
node in response to a control signal and the selected data input signal.
The operation and truth table for a negative edge-triggered flip-flop are the same
as those for a positive except that the falling edge of the clock pulse is the
triggering edge.
Propagation Delay Time - is the interval of time required after an input signal
has been applied for the resulting output change to occur.
Set-Up Time - is the minimum interval required for the logic levels to be
maintained constantly on the inputs (J and K, or S and R, or D) prior to the
triggering edge of the clock pulse in order for the levels to be reliably clocked into
the flip-flop.
Hold Time - is the minimum interval required for the logic levels to remain
on the inputs after the triggering edge of the clock pulse in order for the levels to
be reliably clocked into the flip-flop.
( Marks: 3 )
A serial-in/serial-out shift register has a clock input, a data input, and a data output from
the last stage. In general, the other stage outputs are not available Otherwise, it would be
a serial-in, parallel-out shift register..
The waveforms below are applicable to either one of the preceding two versions of the
serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift
register temporarily stores 3-bits of data and delays it by three clock periods from input to
output.
Question No: 38
( Marks: 5 )
A flash analogue to digital converter is the fastest type of converter we use. Like
the successive approximation converter it works by comparing the input signal to
a reference voltage, but a flash converter has as many comparators as there are
steps in the comparison. An 8-bit converter, therefore, has 2 to the power 8, or
256, comparators.
The resistor net and comparators provide an input to the combinational logic
circuit, so the conversion time is just the propagation delay through the network it is not limited by the clock rate or some convergence sequence. It is the fastest
type of ADC available, but requires a comparator for each value of output (63 for
6-bit, 255 for 8-bit, etc.) Such ADCs are available in IC form up to 8-bit and 10-bit
flash ADCs (1023 comparators) are planned. The encoder logic executes a truth
table to convert the ladder of inputs to the binary number output.
Question No: 39 ( Marks: 5 )
Explain the next-state table with the help of a table for any sequential circuit.
Ans
State Table
The state table representation of a sequential circuit consists of three sections
labelled present state, next state and output. The present state designates the
state of flip-flops before the occurrence of a clock pulse. The next state shows
the states of flip-flops after the clock pulse, and the output section lists the value
of the output variables during the present state.
Present state
Q1Q2
00
01
10
11
11
11
10
10
01
00
11
10
0
0
0
0
0
0
1
1
Ans:
The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as
synchronous inputs because they have effect on the outputs (Q and not-Q) only in step, or
in sync, with the clock signal transitions. These extra inputs that I now bring to your
attention are called asynchronous because they can set or reset the flip-flop regardless of
the status of the clock signal. Typically, they're called preset and clear:
When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of
any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop
will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock.
So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get
an invalid state on the output, where Q and not-Q go to the same state, the same as our
old friend, the S-R latch! Preset and clear inputs find use when multiple flip-flops are
ganged together to perform a function on a multi-bit binary word, and a single line is
needed to set or reset them all at once.
Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or
active-low. If they're active-low, there will be an inverting bubble at that input lead on the
block symbol, just like the negative edge-trigger clock inputs.
Sometimes the designations "PRE" and "CLR" will be shown with inversion bars above
them, to further denote the negative logic of these inputs:
Data signals
Method of how information is transferred; usually it is transferred in binary code
in signals or pulses.
A phase lock oscillator includes a phase discriminator that develops an error
signal by comparing a clock from a voltage controlled oscillator with incoming
random data bits. In the absence of data, the phase lock oscillator is inactive.
However, when data is sensed, a logic and delay network in the phase
discriminator develops an error voltage of suitable polarity and amplitude,
indicative of the lead or lag between the data and clock signals. The error voltage
is applied to the voltage controlled oscillator to modify the frequency and phase
of the clock. Furthermore, first and second integrations are provided by the
phase discriminator and an integrator respectively so that the steady state phase
error is held close to zero.
It is known that spurious variations in the mechanical or electrical parameters of
a storage system cause unwanted displacement and shift of the signal being
processed, thus necessitating frequency and phase compensation. To this end,
synchronizing systems, servosystems, phase lock oscillator circuits, separation
circuits and the like are employed.
( Marks: 1 )
AND, OR
NAND, NOR
NAND, XOR
NOT, XOR
Question No: 3
( Marks: 1 )
One
Two
Three
Four
Question No: 4
( Marks: 1 )
True
False
Question No: 5
( Marks: 1 )
$
#
!
&
Question No: 6
( Marks: 1 )
True
False
Question No: 7
( Marks: 1 )
( Marks: 1 )
Comparator
Multiplexer
Demultiplexer
Parity generator
Question No: 9
( Marks: 1 )
( Marks: 1 )
( Marks: 1 )
True
False
Question No: 12
( Marks: 1 )
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
4
8
12
16
True
False
Question No: 14 ( Marks: 1 ) - Please choose one
The output of the expression F=A+B+C will be Logic ________ when A=0, B=1,
C=1. the symbol+ here represents OR Gate.
Undefined
One
Zero
10 (binary)
Question No: 15
( Marks: 1 )
The Extended ASCII Code (American Standard Code for Information Interchange) is a
_____ code
2-bit
7-bit
8-bit
16-bit
Question No: 1 ( Marks: 1 ) - Please choose one
The maximum number that can be represented using unsigned octal system is _______
1
7
9
16
Question No: 2 ( Marks: 1 ) - Please choose one
If we add 723 and 134 by representing them in floating point notation i.e. by first,
converting them in floating point representation and then adding them, the value of
exponent of result will be ________
0
1
2
3
Question No: 3 ( Marks: 1 ) - Please choose one
The diagram given below represents __________
Demorgans law
Associative law
Product of sum form
Sum of product form
Question No: 4 ( Marks: 1 ) - Please choose one
The range of Excess-8 code is from ______ to ______
+7 to -8
+8 to -7
+9 to -8
-9 to +8
Question No: 5
A non-standard POS is converted into a standard POS by using the rule _____
AA = 0
A+B = B+A
Question No: 6
The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
4
8
12
16
Question No: 7 ( Marks: 1 ) - Please choose one
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator.
What are the output levels?
A > B = 1, A < B = 0, A = B = 0
A > B = 0, A < B = 1, A = B = 1
Question No: 8 ( Marks: 1 ) - Please choose one
A particular Full Adder has
3 inputs and 2 output
3 inputs and 3 output
2 inputs and 3 output
2 inputs and 2 output
Question No: 9 ( Marks: 1 ) - Please choose one
The function to be performed by the processor is selected by set of inputs known as
________
Function Select Inputs
MicroOperation selectors
OPCODE Selectors
None of given option
Question No: 10
2
1
3
4
Question No: 11
4
8
12
16
Question No: 13
Demorgans Law
Distributive Law
Commutative Law
Associative Law
Question No: 14 ( Marks: 1 ) - Please choose one
2's complement of any binary number can be calculated by
adding 1's complement twice
adding 1 to 1's complement
subtracting 1 from 1's complement.
calculating 1's complement and inverting Most significant bit
Question No: 15 ( Marks: 1 ) - Please choose one
The binary value 1010110 is equivalent to decimal __________
86
87
88
89
Question No: 16
_________
A.B.C
Question No: 2
( Marks: 1 )
The Extended ASCII Code (American Standard Code for Information Interchange) is a
_____ code
2-bit
7-bit
8-bit
16-bit
Question No: 3
( Marks: 1 )
Addition
Subtraction
Multiplication
Division
Question No: 4 ( Marks: 1 ) - Please choose one
NOR gate is formed by connecting _________
OR Gate and then NOT Gate
NOT Gate and then OR Gate
AND Gate and then OR Gate
OR Gate and then AND Gate
Question No: 5
( Marks: 1 )
Generally, the Power dissipation of _______ devices remains constant throughout their
operation.
TTL
CMOS 3.5 series
CMOS 5 Series
Power dissipation of all circuits increases with time.
Question No: 6 ( Marks: 1 ) - Please choose one
Two 2-bit comparator circuits can be connected to form single 4-bit comparator
True
False
Question No: 7
( Marks: 1 )
When the control line in tri-state buffer is high the buffer operates like a ________ gate
AND
OR
NOT
XOR
Question No: 8
( Marks: 1 )
22
10
44
20
Question No: 9
( Marks: 1 )
!
&
#
$
Question No: 10
( Marks: 1 )
Similar
Different
Similar with some enhancements
Depends on the type of PALs input size
Question No: 11
( Marks: 1 )
. (a dot)
$ (a dollar symbol)
; (a semicolon)
endl (keyword endl)
Question No: 12
( Marks: 1 )
4
8
12
16
Question No: 13 ( Marks: 1 ) - Please choose one
"Sum-of-Weights" method is used __________
to convert from one number system to other
to encode data
to decode data
to convert from serial to parralel data
Question No: 14
( Marks: 1 )
Circuits having a bubble at their outputs are considered to have an active-low output.
True
False
Question No: 15 ( Marks: 1 )
(A + B)(A + B + C)(A + C)
is an example of ______________
AND
OR
NOT
XOR
Question No: 17
( Marks: 2 )
For what values of A, B, C and D, value of the expression given below will be logic 1. Explain at
least one combination.
A.B + A.B.C.D
Ans:
Ans:
The Adjacent 1s Detector accepts 4-bit inputs.
If two adjacent 1s are detected in the input, the output is set to high.
input combinations will be
1. 0011,
2. 0110,
3. 0111,
4. 1011,
5. 1100,
6. 1101,
7. 1110 and
8. 1111
the output function is a 1.
Question No: 19
( Marks: 2 )
Ans:
1.
2.
3.
4.
5.
6.
01 00,
10 00,
10 01,
11 00,
11 01 and
11 10
Demorgans law
Associative law
Product of sum form
Sum of product form
How can a PLD be programmed?
PLDs are programmed with the help of computer which runs the programming
software. The computer is connected to a programmer socket in which the PLD is
inserted for programming. PLDs can also be programmed when they are installed
on a circuit board
Explain the difference between 1-to-4 Demultiplexer 2-to-4 Binary Decoder?
The circuit of the 1-to-4 Demultiplexer is similar to the 2-to-4 Binary Decoder
described earlier figure 16.9. The only difference between the two is the addition
of the Data Input line, which is used as enable line in the 2-to-4 Decoder circuit
figure
Explain with example how noise affects Operation of a CMOS AND Gate circuit.
Two CMOS 5 volt series AND gates are connected together. Figure 7.3 The first
AND gate has both its inputs connected to logic high, therefore the output of the
gate is guaranteed to be logic high. The logic high voltage output of the first AND
gate is assumed to be 4.6 volts well within the valid VOH range of 5-4.4 volts.
Assume the same noise signal (as described earlier) is added to the output signal
of the first AND gate.
Implementing the circuit directly from the function table based on the SOP form
requires 8 AND gates for the 8 product terms (minterms) with an 8-input OR gate.
Figure 13.3.
The total gate count is
One 8 input OR gate
Eight 4 input AND gates
Ten NOT gates
The expression can be simplified using a Karnaugh map, figure 13.4, and then the
simplified expression can be implemented to reduce the gate count. The
simplified expression
isAB + CD +BC . The circuit implemented using the expression AB + CD +BC
has reduced
to 3 input OR gate and 2 input AND gates.
The simplified Adjacent 1s Detector circuit uses only four gates reducing the cost,
the
size of the circuit and the power requirement. The propagation delay of the circuit
is of the order of two gates
FINALTERM EXAMINATION
Spring 2010
CS302- Digital Logic Design
Time: 90 min
Marks: 58
Question No: 1
A 8-bit serial in / parallel out shift register contains the value 8, _____ clock signal(s)
will be required to shift the value completely out of the register.
1
2
4
8
Question No: 2 ( Marks: 1 ) - Please choose one
A frequency counter ______________
Counts pulse width
Counts no. of clock pulses in 1 second
Counts high and low range of given clock pulse
None of given options
Question No: 3 ( Marks: 1 ) - Please choose one
In a sequential circuit the next state is determined by ________ and _______
State variable, current state
Current state, flip-flop output
Current state and external input
Input and clock signal applied
Question No: 4 ( Marks: 1 ) - Please choose one
The divide-by-60 counter in digital clock is implemented by using two cascading
counters:
Mod-6, Mod-10
Mod-50, Mod-10
Mod-10, Mod-50
Mod-50, Mod-6
Question No: 5 ( Marks: 1 ) - Please choose one
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output
state is maintained.
True
False
Question No: 6 ( Marks: 1 ) - Please choose one
Flip flops are also called _____________
Bi-stable dualvibrators
Bi-stable transformer
Bi-stable multivibrators
Bi-stable singlevibrators
Question No: 7 ( Marks: 1 ) - Please choose one
The minimum time for which the input signal has to be maintained at the input of flipflop is called ______ of the flip-flop.
Set-up time
Hold time
Pulse Interval time
Pulse Stability time (PST)
Question No: 8 ( Marks: 1 ) - Please choose one
74HC163 has two enable input pins which are _______ and _________
ENP, ENT
ENI, ENC
ENP, ENC
ENT, ENI
Question No: 9 ( Marks: 1 ) - Please choose one
____________ is said to occur when multiple internal variables change due to change in
one input variable
Clock Skew
Race condition
Hold delay
Hold and Wait
Question No: 10 ( Marks: 1 ) - Please choose one
Given the state diagram of an up/down counter, we can find ________
The next state of a given present state
The previous state of a given present state
Both the next and previous states of a given state
The state diagram shows only the inputs/outputs of a given states
Question No: 11 ( Marks: 1 ) - Please choose one
The _____________ input overrides the ________ input
Asynchronous, synchronous
Synchronous, asynchronous
Preset input (PRE), Clear input (CLR)
1
0
A
Vout / Rf = - Vin / Ri
Rf / Vin = - Ri / Vout
Rf / Vin = Ri / Vout
Question No: 19 ( Marks: 1 ) - Please choose one
LUT is acronym for ________
Look Up Table
Local User Terminal
Least Upper Time Period
None of given options
Question No: 20 ( Marks: 1 ) - Please choose one
DRAM stands for __________
Dynamic RAM
Data RAM
Demoduler RAM
None of given options
Question No: 21 ( Marks: 1 ) - Please choose one
The three fundamental gates are ___________
AND, NAND, XOR
OR, AND, NAND
NOT, NOR, XOR
NOT, OR, AND
Question No: 22 ( Marks: 1 ) - Please choose one
Question No: 28
( Marks: 2 )
Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder?
Question No: 29
( Marks: 2 )
Question No: 30
( Marks: 2 )
Question No: 31
( Marks: 3 )
Question No: 32
( Marks: 3 )
Explain Rotate Right Operation of shift register with the help of diagram.
Question No: 33
( Marks: 3 )
You are given the block diagram of 74HC190 integrated circuit up/down counter,
explain the function of labeled inputs/outputs.
Question No: 34
( Marks: 5 )
Draw the state diagram of 3-bit up-down counter, use an external input X, when X
sets to logic 1, the counter counts downwards, otherwise upward.
Question No: 35
( Marks: 5 )
Question No: 36
( Marks: 5 )
FINALTERM EXAMINATION
Spring 2010
CS302- Digital Logic Design (Session - 1)
Time: 90 min
arks: 58
Question No: 1 ( Marks: 1 ) - Please choose one
"A + B = B + A" is __________
Demorgans Law
Distributive Law
Commutative Law
Associative Law
Question No: 2 ( Marks: 1 ) - Please choose one
The diagram given below represents __________
Demorgans law
Associative law
Product of sum form
Sum of product form
Question No: 3 ( Marks: 1 ) - Please choose one
Following is standard POS expression
True
False
Question No: 4 ( Marks: 1 ) - Please choose one
An alternate method of implementing Comparators which allows the Comparators to be
easily cascaded without the need for extra logic gates is _______
Using a single comparator
Using Iterative Circuit based Comparators
Connecting comparators in vertical hierarchy
Extra logic gates are always required.
Question No: 5 ( Marks: 1 ) - Please choose one
Demultiplexer is also called
Data selector
Data router
Data distributor
Data encoder
Question No: 6 ( Marks: 1 ) - Please choose one
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K
flip-flop ___________
Doesnt have an invalid state
Sets to clear when both J = 0 and K = 0
It does not show transition on change in pulse
It does not accept asynchronous inputs
Question No: 7 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________
Low-to-high transition of clock
High-to-low transition of clock
Enable input (EN) is set
Preset input (PRE) is set
Question No: 8 ( Marks: 1 ) - Please choose one
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the
power dissipation of the flip-flop is
10 mW
25 mW
64 mW
1024
Question No: 9 ( Marks: 1 ) - Please choose one
____________ counters as the name indicates are not triggered simultaneously.
Asynchronous
Synchronous
Positive-Edge triggered
Negative-Edge triggered
Question No: 10 ( Marks: 1 ) - Please choose one
74HC163 has two enable input pins which are _______ and _________
ENP, ENT
ENI, ENC
ENP, ENC
ENT, ENI
Question No: 11 ( Marks: 1 ) - Please choose one
The divide-by-60 counter in digital clock is implemented by using two cascading
counters:
Mod-6, Mod-10
Mod-50, Mod-10
Mod-10, Mod-50
Mod-50, Mod-6
Question No: 12 ( Marks: 1 ) - Please choose one
In a state diagram, the transition from a current state to the next state is determined by
Current state and the inputs
Current state and outputs
Previous state and inputs
Previous state and outputs
1
0
A
Dynamic RAM
Data RAM
Demoduler RAM
None of given options
Question No: 20 ( Marks: 1 ) - Please choose one
in ____________, all the columns in the same row are either read or written.
Sequential Access
MOS Access
FAST Mode Page Access
None of given options
Question No: 21 ( Marks: 1 ) - Please choose one
FIFO is an acronym for __________
First In, First Out
Fly in, Fly Out
Fast in, Fast Out
None of given options
Question No: 22 ( Marks: 1 ) - Please choose one
In order to synchronize two devices that consume and produce data at different rates, we
can use _________
Read Only Memory
Fist In First Out Memory
Flash Memory
Fast Page Access Mode Memory
Question No: 23 ( Marks: 1 ) - Please choose one
A frequency counter ______________
Counts pulse width
Counts no. of clock pulses in 1 second
Counts high and low range of given clock pulse
None of given options