Mos Slides

Chapter 1:
MOSFET operation
Outline
Introduction
Long-channel transistor
Small-geometry effects
Small-signal behavior at low frequencies
Capacitors and parasitic resistors
Evaluation of MOS performance in Matlab
Outline
Introduction
Microelectronics obeys Moores law

= Exponential growth of # transistors on a chip
[www.intel.com]
Roadmap according to this law: International

Technology Roadmap for Semiconductors (ITRS),
see http://public.itrs.net
4
ITRS predicts CMOS downscaling until

2020
1400
Technology
generation
2004
90 nm
2007
2009
65 nm
45 nm
2011
32 nm
2013
22 nm
2015
14 nm
year of
production
Cutoff frequency f [GHz]
1st
1200
ITRS 2003
1000
fT is a measure for
the transistor speed
(see later)
800
600
400
200
100
80
60
40
Gate length [nm]
20
Upgrade of technology yields reduction in area per function and

energy consumption per logical operation
CMOS speed increases CMOS is also used nowadays for
radio-frequency (RF) applications
5
digital
CMOS has replaced bipolar and GaAs in

various wireless products
antenna
Commercial CMOS radio ICs

for GSM, DECT, Bluetooth, GPS, WLAN,
CMOS prototype
for 60GHz
wireless
communication
(UC Berkeley,
2007)
Ideal MOS transistor in saturation is

a (voltage-)controlled current source
|iTHROUGH|
(A)
saturation
increasing |VGS|
|VCONTROL|=|VCONTROL7| (> |VCONTROL6|)

|VCONTROL|=|VCONTROL1|
|VOVER| (V)
iTHROUGH
-
vOVER
ITHROUGH
vOVER
vCONTROL
+
vCONTROL
ITHROUGH
vCONTROL
Symbols for an n-MOS transistor

Drain
normal current
flow IDS
Gate
Bulk
Source
Source
normal operation: iDS
(A)
VGS > 0
VDS 0
VSB 0
VGS=VGS7 (> VGS6)
saturation
VDS (V)
More positive VGS
Gate
More complete:
Drain
VGS=VGS6 (> VGS5)

VGS=VGS5 (> VGS4)
VGS=VGS4 (> VGS3)
VGS=VGS3 (> VGS2)
VGS=VGS2 (> VGS1)
VGS=VGS1
8
Symbols for a p-MOS transistor

Source
Gate
normal current
flow IDS
More complete:
Source
Gate
Bulk
Drain
|iDS|
normal operation: (A)
VGS < 0
VDS 0
VSB 0
saturation
|VDS| (V)
More negative VGS
Drain
|VGS|=|VGS7| (> |VGS6|)
|VGS|=|VGS6| (> |VGS5|)

|VGS|=|VGS5| (> |VGS4|)
|VGS|=|VGS4| (> |VGS3|)
|VGS|=|VGS3| (> |VGS2|)
|VGS|=|VGS2| (> |VGS1|)
|VGS|=|VGS1|
9
Real transistor characteristics

IDS
(A)
6
not really flat
IMEC 90 nm CMOS process
-3
x 10
W = 10 m
L= 90 nm
VGS=1.2 V
VGS=1.125 V
VGS=1.05 V
VGS=0.975 V
VGS=0.9 V
VGS=0.825 V
VGS=0.75 V
2
VGS=0.675 V
VGS=0.6 V
1
00
0.2
0.4
0.6
VDS (V)
0.8
VGS=0.525 V
VGS=0.45 V
V
GS=0.375
VGS=0.3
VV
=0.225
=0.15
=0.075
1.2 =0
10
The simple quadratic MOS model
if |VGS| < |VT|: IDS = 0

this is oversimplified, as it assumes that in moderate
and weak inversion, the current is zero, which is not true
if |VGS| sufficiently above |VT|:

Non-saturation (|VDS| < |VDSAT| = |VGS VT|):
IDS
W
(VGS VT ) VDS 21 VDS2
= C 'ox
L
Saturation (|VDS| > |VDSAT|):
IDS
W
2
= C 'ox
(VGS VT ) (1 + VDS )
2L
= oversimplification
reality is much more complex, as we will see
11
Small-signal equivalent circuit

of an ideal MOS transistor
(in saturation)
+
vcontrol
Ithrough = gm.vcontrol
-
gm: transconductance
Zin =
Zout =
12
The reality is less ideal

coupling
input-output
+
vcontrol
Zin
gm . vcontrol
Zout
and many more effects

13
Cross-section of an n-MOS transistor

Lmask
gate
contact
source
STI
n+
contact
silicide
poly
Si
Leff
oxide
trench
metallization not shown
n-
silicide
p bulk
shallow
trench
isolation
tox
n-
drain
silicide
oxide
trench
n+
p
p
This is a so-called planar bulk device
14
Cross-section of a p-MOS up to
contacts
L
gate
contact
contact
silicide
poly
Si
source
silicide
oxide
trench
p+
p-
tox
p-
drain
silicide
p+
oxide
trench
n-well
p-type substrate
15
Triple-well process gives n-MOS

transistors their own bulk
L
gate
contact
contact
silicide
poly
Si
source
silicide
oxide
trench
n+
n-
tox
n-
drain
silicide
n+
oxide
trench
p-well
n-well
p-type substrate
16
Further processing steps until metal eight

400 nm
Metal 8
Metal 7
Metal 6
Metal 5
Metal 4
Metal 3
Metal 2
via contact
Metal 1
contact
p-MOS
n-MOS
17
Top view of a MOS transistor

(1 gate finger)
W
source
gate
drain
metal 1
active region
polysilicon
18
Layout of a MOS transistor

with multiple fingers
W / # fingers
source
L
drain
gate
source
drain
source
19
Outline
Introduction
20
MOS two-terminal structure

induced channel not yet connected to the outside world
terminal 1
+ VGB
-
gate material
gate oxide
induced channel
depletion zone
p-type Si (bulk)
terminal 2
L
21
MOS structure: a field-effect device,

controlled by gate-bulk voltage difference
-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
VT: threshold voltage
gate material
gate oxide
source
n+
+ VGB
-
positive gate charge
depletion zone (negative charge)
n+
drain
p-type Si (bulk)
Electrons in the silicon are attracted to the interface with the oxide
This happens more when VGB increases
For small VGB values, well below VT, charge made up by the electrons that are
attracted to the interface is macroscopically invisible compared to the charge of the
depletion zone, even if their concentration per volume unit is higher than the concentration
of charges in the depletion zone. If this concentration is higher, then we speak about
an inversion situation
22

-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
23

-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
24

-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
gate material
gate oxide
source
n+
depletion zone
+ VGB
-
n+
drain
p-type Si (bulk)
25

-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
gate material
gate oxide
source
n+
depletion zone
+ VGB
-

induced channel
n+
drain
p-type Si (bulk)
26

-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
gate material
gate oxide
source
n+
depletion zone
+ VGB
-

induced channel
n+
drain
p-type Si (bulk)
27

-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
gate material
gate oxide
source
n+
depletion zone
+ VGB
-

induced channel
n+
drain
p-type Si (bulk)
28

-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
gate material
gate oxide
source
n+
depletion zone
+ VGB
-

induced channel
n+
drain
p-type Si (bulk)
29

-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
gate material
gate oxide
source
n+
depletion zone
+ VGB
-

induced channel
n+
drain
p-type Si (bulk)
30

-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
gate material
gate oxide
source
n+
depletion zone
+ VGB
-

induced channel
n+
drain
p-type Si (bulk)
31

-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
gate material
gate oxide
source
n+
depletion zone
+ VGB
-

induced channel
n+
drain
p-type Si (bulk)
32
Drain-to-source voltage brings induced

channel into movement: current!
-0.1 0 0.1
0.2
-0.2
-0.3
0.3
0.4
-0.4
VGB-VT
0.5
-0.5
(V)
VGS
source
n+
+
-
gate material
gate oxide
current
depletion zone
+ V
SB
p-type Si (bulk)
VGS=VGB-VSB

induced channel moving
drain
n+
+ VDS > 0
33
There are three inversion regimes:

weak, moderate and strong inversion
notation of inversion charge per unit area: QI
weak inversion:
inversion charge macroscopically invisible compared to depletion
charge
QI increases exponentially with VGB
strong inversion:
inversion charge clearly present, forms a well conducting strip
underneath the gate oxide, cfr. parallel-plate capacitance (C = Q/V
or per unit area: C = Q/V)
Here: Cox=QI/(VGB-VT)
VT is the threshold that has to be surmounted by VGB to come into
strong inversion
Moderate inversion:
situation in between
QI dependence on VGB makes transition between exponential and
linear dependence
34
Expression of VT
VT 0 = VFB + 0 + 0
subscript 0
means: VT without
body bias
(see also further)
thermal voltage
kT/q
(25.8 mV at room
temperature)
VFB: flat-band voltage
acceptor concentration
NA
+ a few times Ut
0 = U t ln
ni
intrinsic concentration
in Si (1.2 x 1010 cm-3)
2 Si qN A
C 'ox
VT0 decreases as oxide gets thinner ( decreases)

easier gate control when oxide is thinner
VT0 increases as doping level increases
( and 0 increase) VT0 can be adjusted with doping level NA
35
VT is customized with ion implantations

gate
silicide
poly
Si
source
silicide
n+
drain
n-
n-
silicide
n+
p
p
STI
bulk
without these implants |VT| would be too low

36
VT implants cause large variability

on VT for small downscaled devices
# atoms in channel of
downscaled devices is not
much anymore
difference of a few atoms
causes a visible shift of VT
(over)simplified
picture of a MOS
transistor
2008: Physical gate length
= 22nm (65nm node)
2016: Physical gate length =

9nm = 30x30x30 atoms
(22nm node)
Courtesy: Asenov TAD workshop at IMEC, 2005
37
Body effect counteracts the gate control

source of free electrons
used here to contact the
channel to bring it on a
certain voltage VCB
wanted
gate operation
VGC
+
-
gate
oxide
channel
depletion zone
n+
bulk (or body)
Channel affected by gate control
and by body control
one finds:
VT = VT 0 +
0 + VCB 0
Counteracting
operation from
the body
+ V
CB
-
channelbulk
voltage
body effect is proportional to body effect coefficient

more pronounced for higher bulk doping
less pronounced for thinner oxide (gate is closer to channel,better gate control)
38
For VDS > 0 inversion level changes over the

channel
we assume that source side of the channel is strongly inverted
The further you go in the channel into the direction of the drain, the higher the voltage
difference VCB between a place in the channel and the bulk.
body effect is more pronounced as you move in the channel towards the drain
VT increases as you move towards the drain
inversion level decreases as you move towards the drain
the induced pn junction (p-side = bulk, n-side = inversion layer) is more inversely
biased thicker depletion zone
VGS
source
n+
+
-
gate
gate oxide
+ V
SB
-
VCB
current
depletion zone
drain
n+
p-type Si (bulk)
+ VDS > 0
-
39
Terminology on inversion
level and VT of a transistor
Inversion level of a transistor corresponds to inversion level
at the source end
Inversion level at drain end is lower than at source end as soon
as VDS > 0 V or, in other words, when VDB>VSB, there is
more body effect at the drain end than at the source end
the VT of a transistor corresponds to VT at the source end
40
Drain-to-source current as a function of

VGS shows 3 inversion regimes
I
DS
(A)
10-5
10-6
10-7
10-8
data from 90nm process

(IMEC)
VT = 0.4 V
almost quadratic
dependence
leakage
current when
transistor is off
10-9
exponential
dependence
10-10
10-11
subthreshold slope
ideally 60 mV/decade
10-12
-0.5
-0.1
-0.4
0
-0.3
0.1
weak inversion
-0.2
0.2
-0.1
0.3
0
0.1
0.2 VGS-VT
0.6 VGS (V)
0.4
0.5
=VT
strong inversion
moderate inversion
41
What is the boundary between

the 3 inversion regimes ?
weak moderate: transition from
exponential dependence of IDS on VGS
to non-exponential
moderate strong: VOV = 0.2 V
42
Drain current IDS as a function of VDS

-3
iDS
(A)
1.4
x 10
VGS=VGS7
VGS7> VGS6> VGS1
1.2
VGS=VGS6
Increase of
inversion level
at source end
0.8
VGS=VGS5
0.6
VGS=VGS4
0.4
VGS=VGS3
0.2
VGS=VGS2
VGS=VGS1
0.5
1.5
2.5
VDS (V)
43
MOS is a controlled current source in

the saturation region (VDS > VDSAT)
x 10 -3
IDS
(A)
1.4
VGS=VGS7
VGS7> VGS6> VGS1
1.2
Nonsaturation
or triode region saturation
: onset of
saturation
This occurs
at VDS = VDSAT
VGS=VGS6
0.8
VGS=VGS5
0.6
VGS=VGS4
0.4
VGS=VGS3
0.2
VGS=VGS2
saturation voltage
Clearly, VDSAT
is a function of
VGS (at least
in strong inversion)
VGS=VGS1
0
0.5
1.5
VDS (V)
2.5
44
MOS is a controlled resistor for small VDS

0.8
VGS=VGS5
At small VDS:
VGS cannot increase the current,
0.6 of I (V )
VGS can only change the slope
DS
DS
VGS=VGS4
IDS
(A)
VDS = 0V: MOS is a purely
passive device, namely a
voltage-controlled resistor
with small-signal value rds0:
rds 0
IDS
=
VDS
0.4
VGS=VGS3
0.2
VGS=VGS2
VDS =0
slope for VGS4

= 1/rds0 for VGS4
VGS=VGS1
0
0
0.5
1.5
VDS (V)
45
IDS in strong inversion

IDS
W
(VGS VT ) VDS a2 VDS2
= C 'ox
L
with a 1 +
and
2 0 + VSB
VT = VT 0 +
0 + VSB 0
This is the SPICE level 3 model for the drain current

Simplification: a = 1
IDS
W
(VGS VT ) VDS 21 VDS2
= C 'ox
L
This is the SPICE level 1 current model

This is a simple equation but not accurate for short channel lengths
We observe a linear dependence on VGS linear region or triode region
46
Dependence of electric field on position in

the channel (strong inversion)
Idrift(x) = W (-QI)E
must be independent of x
QI is the inversion layer charge per unit area
we know that |QIsource|>|QIdrain|
Eat drain > Eat source

Since v = E
we find that electrons at the drain end have a higher
velocity than at the source end
47
Saturation in strong inversion

Physical interpretation: Drain end of the channel
comes into weak inversion when VDB is increased
This happens at VDS = VDSAT

One finds in strong inversion:
VDSAT
VGS VT
=
a
for a =1, we find
VDSAT = VGS - VT
48
Saturation of a MOS transistor

depletion layer
(strong inversion)
not shown for
simplicity
source
source
gate material
gate oxide
channel
VDS1 < VDSAT
gate material
gate oxide
channel
VDS2 = VDSAT
source
gate material
gate oxide
channel
VDS3 > VDSAT
source
gate material
gate oxide
channel
VDS4 > VDS3
legend in the channel:

weak inversion
moderate inversion
strong inversion
drain
drain
drain
drain
49
Physical interpretation of
saturation in strong inversion
saturation means: IDS does not change when VDS(which is assumed to
be > VDSAT) changes
When part of the channel in the vicinity of the drain end is weakly
inverted, then this part of the channel can be represented as a very
poor conductor, almost an insulator (in which we can neglect the
presence of the electrons that form the drain current). Now, when the
drain voltage changes, which is at the right side of that insulator, then
at the left side of that insulator, nothing is felt of this change.
50
IDS in saturation, strong inversion:

square-law model
Substitute VDS = VDSAT into eq. of IDS in triode region:
IDS
W
2
= C 'ox
(VGS VT )
2aL
square-law model
Shorthand notation, using the overdrive voltage VOV=VGS-VT:
IDS
W
2
= C 'ox
VOV
2aL
51
Incorrectness in the simplified model:

electron velocity goes to at onset of saturation
Indeed,
I DS = I drift = W ( Q' I ) E
goes to zero
at VDS=VDSAT
this will then go
to to have a
nonzero IDS
v = E
v at drain end
This is physically impossible. We will correct this later
52
Channel length modulation in strong inversion

1. Situation at VDS = VDSAT:
source
gate material
gate oxide
channel
VDSAT
drain
: saturation point
Average horizontal electrical field in strongly inverted part of channel= VDSAT/L
2. Situation for VDS > VDSAT:

L<L
gate material
gate oxide
channel
source
VDSAT
driving force for drift current
drain
VDS-VDSAT
Average horizontal electrical field in strongly inverted part of channel= VDSAT/L
Driving force for drift current is now higher more current

53
Due to Channel-Length Modulation

(CLM), IDS depends on VDS
IDS
(A)
1.4
x 10
-3
1.2
current increases
for VDS > VDSAT
due to CLM
nonsaturation saturation
0.8
ideal current
source behavior
0.6
IDS
0.4
0.2
W
2
= C 'ox
(VGS VT ) (1 + VDS )
2aL
= IDSAT . (1+. VDS)
= (over)simplified SPICE level 1 model
0.5
VDSAT
1.5
2.5
VDS (V)
54
CLM less pronounced for

longer channels
.. since decrease of channel length due to
CLM is relatively less important for a
longer channel
a longer transistor behaves as a more
ideal current source than a short transistor
(but it is slower, see later when we compute fT)
55
Zoom into weak and moderate inversion

-4
IDS
(A)
10
weak inv.
moderate inv.
-5
10
VGS=0.5V
Log scale
VGS=0.4V
VT = 0.47V
-6
10
VGS=0.3V
-7
10
VGS=0.2V
-8
10
VGS=0.1V
-9
10
VDSAT in
weak inv.
VGS=0V
-10
10
0.5
1.5
VDS (V)
2.5
In weak inversion we see:

1. vertical distance between curves is constant for the same VGS
this corresponds to an exponential dependence of current on VGS
2. VDSAT is independent of VGS
56
Weak inversion: negligible drift current

Current mechanism is diffusion
driving force is the gradient in concentration of inversion charge QI
I diff
VGS
(Q' Idrain Q' Isource ) exp
nU t
weak inversion slope
VGS
exp
nU t
VGD
exp
nU t

VDS
1 exp

nU t
= 1 as soon as
VDS > a few Ut
dependence on VDS
vanishes saturation
VDSAT in weak inversion is a few times Ut
57
Saturation of a MOS transistor

in weak inversion
Physical interpretation:
|QI| at drain decreases exponentially as VDB (or VDS) increases
inversion charge at drain is negligible as soon as VDS > a few times Ut
then the concentration gradient does not change anymore
|QI|
|QI source|
in saturation:
|QI drain| << |QI source|
Slope = driving force
for diffusion current
|QI drain|
0
source
end
L
drain
end
QI drain - QI source -QI source

IDS (proportional to
QI drain - QI source )
does not change
anymore with VDS
58
Expression of IDS in weak

inversion, long channel
IDS
VGS VM
VDS
W
2
1 exp
= C'ox
Ut exp
L 2 2F + VSB
nU
U
t
t
with VM = VT a few times Ut (e.g. 6 Ut)

and F = Ut ln(NA/ni)
59
Note about the value of the weak

inversion slope
Weak inversion slope n is slightly dependent
on bias and channel length
For deep submicron processes it is around
1.4 1.2
With downscaling it comes closer to one for
long-channel devices
60
Drain current in moderate

inversion
Both diffusion and drift current are present
Dependence on VGS is in the transition between
exponential (weak inversion) and quadratic (strong
inversion)
A closed-form expression cannot be obtained for the
current
iteration is required, but the form of the drain
current is
IDS = Cox (W/L) f(VGS, VDS, VSB)
61
Comparison of drift and diffusion current over the

inversion levels
10 -2
10 -3
10 -4
10 -5
diffusion
drift
10 -6
10 -7
10 -8
10 -9
10 -10
10 -11
10 -12
-0.5
-0.3
-0.1
0.1
0.3
0.5
VGS-VT (V)
0.7
0.9
1.1
1.3
weak inversion (Idrift << Idiffusion)

moderate inversion (Idrift Idiffusion)
strong inversion (Idrift >> Idiffusion)
62
Bias voltages are reduced to allow

proper operation of downscaled CMOS
1.2
ITRS 2003
1
V
[Volt]
0.8
DD
0.6
0.4
V
0.2
VDD is scaled down to

- prevent breakdown of
gate oxide that is getting
thinner with downscaling
- limit the kinetic energy
of electrons, that would
damage the gate oxide
(see also further)
0
100
80
60
40
Gate length [nm]
20
To keep n-MOS in saturation:

VDS > VGS VT
hardly scales down
With downscaling it becomes more and more difficult to stack
more than two transistors in saturation between the low VDD and ground
63
Moderate inversion plays a large

role in downscaled technologies
Regions of inversion do not narrow down with scaling
and VDD decreases relatively more than VT
1.2
ITRS 2003
1
[Volt]
0.8
VGS
range
0.6
V
DD
strong inversion
almost 50 %
of VGS range
is moderate inv.
VT
0.2 V 0.4
moderate inversion
0.2
0
weak inversion
100
80
60
40
Gate length [nm]
20
64
In every inversion region IDS is

proportional to .Cox.(W/L)
In all regions of inversion we can write
cannot be chosen
(fixed by technology)
design choice
(determines the
inversion level)
design choice
determined by
specification on the current
weaker dependence
than on VGS, at least
in saturation;
guessed, or
determined from
the rest of the
circuit
IDS increases exponentially with VGS in weak inversion

quadratically with VGSin strong inversion (saturation)
transition between exp(VGS) and quadratic dependence in moderate inversion
65
Required width for a given

current
From IDS = Cox (W/L) f(VGS, VDS, VSB)
we find the required width for a given IDS:
IDS L
W=
Cox f(VGS, VDS, VSB)
W decreases exponentially with increasing VGS in weak inversion
quadratically with increasing VGS in strong inversion
transition between exp(-VGS) and VGS-2 dependence in moderate inversion
66
IDS(VGS) and W(VGS) for a given current

iDS (A)
10-4
10-6
drain current for a given width

10-8
10-10
10-12
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.1
0.2
V
W (m)
10
10
10
10
10
0.3
0.4
(V)
0.5
0.7
0.8
0.9
1.1
1.2
OV
width for a given drain current

W=
0.6
IDS L
Cox f(VGS, VDS, VSB)
the lower the inversion level, the wider a

transistor needs to be to conduct a specified IDS
-2
-4
-6
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

V OV (V)
1.1 1.2
67
Sizing of a MOS transistor based

on a specification for the current
1. typically, we choose L
2. next we choose the inversion level
3. based on the current for a given
reference width and the current spec,
we find the width for the transistor
the lower the inversion level, the wider the
transistor will be
68
Outline
Introduction
69
Small-dimension effects
Long and wide channels:
IDS W
1
IDS
L
(if we neglect CLM)
This is no longer true for short and narrow channels

short-channel and narrow-channel effects
Gate oxide gets thinner with downscaling
thin gate oxide effects
70
Classification of most important

small-geometry effects
Thin gate oxide effects:
- mobility degradation due to vertical electrical field
- poly gate depletion
- gate leakage
Short channel effects:
- velocity saturation
- drain-induced barrier lowering
- impact ionization (not treated here)
Narrow channel effect: see slides further
71
Mobility degradation due to vertical electrical field
source
gate material
gate oxide
channel
Ey
Ex
drain
Electric field that acts on electrons in the channel has 2 components:

- Horizontal field Ex (drift field)
- Vertical field Ey (due to gate operation, see 2-terminal structure)
electrons are accelerated not exactly horizontally, but also slightly
vertically
electrons want to enter the gate oxide, but this is impossible
they undergo more collisions
This is modeled by a degradation of the mobility
72
Simplified modeling of mobility degradation

in strong inversion:
eff =
1 + (VGS VT )
< 0
proportional to 1/tox
More mobility degradation for higher gate overdrive

(logical, since then the vertical electric field is higher)
73
Velocity saturation
Absolute value of the velocity of electrons in Si is about 105 m/s
at room temperature. This is called the saturation velocity vsat
zero electrical field
low horizontal electrical field Ex

Ex opposite to x direction
velocity vector of an electron
s
o
u
r
c
e
x
Average velocity in x direction = 0
d
r
a
i
n
x
Average velocity in x direction = E << vsat
(averaged over many electrons)

74
Velocity saturation (continued)

At high horizontal electrical fields Ex average
velocity cannot be higher than vsat
Then v is no longer proportional to E
v
(m/s)
v = E
5
10
10
10 5
10
10
EC
10
10
EC: critical electrical field
E (V/m)
75
Velocity saturation causes a decrease of IDS

Velocity saturation plays a larger role than mobility reduction
One can derive an approximate expression for IDS
in strong inversion, nonsaturation:
IDS = eff
1
W
1
C 'ox [(VGS VT ) VDS 2 a VDS ]
VDS
L
1+
L EC
<1
Velocity saturation
more severe as L decreases
with EC=vsat/eff
critical electrical field
76
Combination of mobility degradation

and velocity saturation into one
model (strong inversion)
IDS
Strong inversion (VOV 0.2 V), triode region:

0
1
W
1
=
C 'ox [(VGS VT ) VDS 2 a VDS ]
V
1 + (VGS VT )
L
1 + DS
L EC
Strong inversion (VOV 0.2 V), saturation region:
IDSAT =
1 + (VGS
1
W
2
C 'ox
(VGS VT )
VDSAT
2aL
VT )
1+
L EC
(1)
Note: velocity saturation is usually more important than mobility

degradation
77
Further simplification in saturation

eq. (60):
IDSAT =
1 + (VGS
1
W
2
C 'ox
(VGS VT )
VDSAT
2aL
VT )
1+
L EC
1
both of the form
1+ x
1
1
1
using
1+ x 1+ y 1+ x + y
and VDSAT VGS-VT and ECvsat/0
we find from eq. (1) on previous slide
IDSAT =
0
(VGS VT )
1 + +
v sat L
W
2
C 'ox
(VGS VT )
2aL
78
For very short channels, deep strong

inversion: MOS in saturation becomes
a linear device
if
0
vsat L
(VGS VT ) + >> 1
IDSAT
W v sat C 'ox
(VGS VT )
2a
IDSAT linearly dependent on VGS VT !!

gm becomes independent of VGS - VT
79
Velocity saturation redefines VDSAT

Saturation condition now becomes:
electrons attain a speed of vsat at the drain end
This is more realistic than the model without
velocity saturation where the speed goes to
One can compute a new value for VDSAT for strong inversion:
<1
VDSAT
(
VGS VT )
=
[1 + (VGS VT )]
0
(VGS VT )
1 + +
2av sat L

This is smaller than the earlier value of VDSAT = (VGS-VT)/a

since with a finite velocity, saturation is reached earlier
than with an infinite velocity
VGS VT
Note that limL VDSAT =
a
80
Hot electrons: electrons with

saturation velocity
Electron speed in the channel (qualitatively)
vsat
source
drain
Hot electrons at drain end have high kinetic energy (mv2/2):

- they collide with atoms, hereby generating new electron/hole pairs
- they can enter the gate oxide under influence of the vertical electric field
This can be destructive for a transistor
81
Effect of hot electrons is lowered using

lowly-doped drain (LDD) regions
gate
silicide
poly
Si
source
silicide
oxide
n+
drain
n- R
IDS
n- R
silicide
n+
p
p
LDD regions: lowly doped, hence highly resistive

voltage drop IDS R decreases
voltage drop over the channel
p
horizontal electrical field decreases
82
Drain-induced barrier Lowering

(DIBL)
Barrier (for inversion) is lowered thanks to the fact that the

space charge layers (- - -), which are present by the sourcebulk and drain bulk p-n junctions, intersect with the zone
that needs to be depleted before we have a channel
83
DIBL (continued)
Situation at VDS = 0V
: intersection region; this is already depleted by

presence of p-n junction of source/bulk and drain/bulk
The intersection region is relatively important for short channels
Gate action does not have to deplete anymore the intersection region
barrier (for inversion) is lowered
84
DIBL (continued 2)
Situation at VDS > 0V
Intersection region is larger at the drain side for VDS > 0V

This explains the name drain-induced for this effect
The channel is now not only controlled by the gate voltage,
but also by the drain voltage
DIBL: more pronounced for shorter channels,
less pronounced if gate oxide is thinner
(gate is closer to the channel, yielding better gate control)
85
DIBL is limited with pocket implants

gate
silicide
poly
Si
source
silicide
oxide
n+
tox
n-
n-
drain
silicide
n+
p
p
pocket implants
p
(also called halo implants)
= highly doped regions into which the extension of the

space charge layer of the source-bulk (drain-bulk) diode
is kept limited
86
VT (V)
0.5
DIBL is modeled by making VT

dependent on L and VDS
with pocket implants
0.4
VT (V)
0.54
0.52
0.3
0.2
data for 0.18 m CMOS
without pocket implants

(qualitatively)
0.1
0.5
0.48
0.46
0.44
0.42
10
L (normalized to Lmin)
For long channels: dependence

of VT on L and VDS is small
L=0.18m
0.4
VT ~ (L ) VDS
: DIBL coefficient (> 0)
0.38
0.36
0.34
0
L=2m
0.2 0.4 0.6 0.8
1.2 1.4 1.6
1.8
VDS (V)
87
DIBL is a serious scaling problem

Drain-source voltage starts to control the
channel
One of the causes of increased leakage current at VGS
= 0 V:
VGS VT (VDS )
IDS exp
nUt
decrease of VT due to DIBL at

VGS=0 V yields exp. increase of IDS
Can be reduced by making the influence of the

gate on the channel stronger
Thinner gate oxide (gate is closer to the channel)
Problem: gate oxide downscaling causes more and more
gate leakage
Multi-gate devices (e.g. FinFETs)

88
Slope of IDS versus VDS in saturation

is determined both by CLM and DIBL
For VDS > VDSAT:
small VDS values: CLM dominates over DIBL
larger VDS values: DIBL dominates over CLM
Both effects become less important as channel length increases
IDS-VDS curves are flatter for longer transistors
than for short ones
89
Narrow-channel effect causes

decrease of VT
W
fringing
field
oxide
trench
gate
gate
oxide
Si bulk
oxide
trench
Extra fringing field lines contribute to depletion of the channel,

while they have not been taken into account previously
gate operation more efficient than previously calculated
This is quantified by a lower VT
90
Narrow-channel effect is modeled

by making VT dependent on W
0.5
L = 0.18 m
V (Volt)
0.45
0.18 m CMOS
0.4
0.35
L = 2 m
0.3
0.25
0.2
0.3
1.0
10
W (micrometer)
Narrow-channel effect negligible for W > 2 m in this technology

in 0.18 m CMOS: IDS is linearly dependent on W for W > 2 m
91
Poly-gate depletion decreases IDS

Gate stack for n-MOS:
In doped polysilicon the free
carriers can move under the
influence of a potential difference,
just as in crystalline silicon, leaving
behind a depleted zone
depleted zone in
n-type polysilicon
inversion layer
= extra insulating
layer that adds to oxide
layer
silicided
polysilicon
n-type polysilicon
tox
depletion zone
Similar for p-MOS structure
higher effective tox lower Cox lower IDS

effect is not present for metal gate
92
Gate leakage current caused by

thin gate oxide
tox decreases with downscaling
nowadays gate oxide is just a few atomic layers thick
leaky gate oxide
direct tunneling current of electrons through oxide
current density ~ exp(-tox)
Further downscaling involves use of high-k oxides

with (= k) > SiO2
effective oxide thickness (EOT) < physical tox
e.g. 90 nm CMOS: SiON gate oxide, tox= 2 nm, EOT = 1.5 nm
93
Gate leakage current flows into source

(IGS), drain (IGD) and bulk (IGB)
IGDO
IGSO
IGC
IGCS
IGB
IGCD
gate-to-channel current IGC is split over source and drain

IGS = IGCS + IGSO
IGD = IGCD + IGDO
94
Gate leakage for 90 nm

|IGD| (A)
10
10
10
10
10
-9
-10
90 nm CMOS
W = 10 m
L = 90 nm
n-MOS with VGS = 0 V
-11
-12
-13
0.2
0.4
0.6
0.8
1.2
VDS (V)
95
Evaluation of IDS in 0.18 m CMOS (1)

L = 0.18 m, W/L = 10/0.18
1.5
x 10
iDS (VSB = 0 V, W = 10m, n-MOS of UMC CMOS 180 nm)

VGS=0.20
-3
VGS=0.30
VGS=0.40
VGS=0.50
iDS (A)
VGS=0.60
VGS=0.70
VGS=0.80
0.5
0
0
VGS=0.90
0.2
0.4
0.6
0.8
1
|VDS (V)|
1.2
1.4
1.6
1.8
Note: VT0 0.5 V

96

iDS (VSB = 0 V, W = 200m, n-MOS of UMC CMOS 180 nm)
-3
2.5
x 10
VGS=0.20
VGS=0.30
VGS=0.40
L = 4 m, W/L = 10/0.18
VGS=0.50
VGS=0.60
1.5
iDS (A)
VGS=0.70
VGS=0.80
VGS=0.90
0.5
0
0
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
|VDS (V)|
Longer channel flatter curves in saturation

larger current than for L=0.18m due to less velocity saturation
97

L = 0.18 m, W/L = 10/0.18
IDS (A) (log. scale)
-2
10
-4
10
-6
10
-8
10
-10
10
straight line
= exp. behavior
(weak inversion)
-12
10
0.2
0.4
0.6
0.8
VGS (V)
1.2
1.4
1.6
1.8
Note: VT0 0.5 V

98
Evaluation of VDSAT in 0.18 m CMOS

|VDSAT|(n-MOS of UMC CMOS 180 nm, VSB = 0 V, VDS = 0.9 V)
L =180.00nm
L =885.00nm
L =1.59m
L =2.29m
L =3.00m
VOV
1.2
1
|VDSAT| (V)
Long channel
slope < 1
since a > 1
0.8
0.6
45
level 1:
VGS-VT
0.4
0.2
-0.4
-0.2
a few Ut
in weak inversion
0.2
0.4
0.6
|VGS - VT| (V)
0.8
1.2
far below VGS-VT

due to velocity sat.
99
100
Outline
Introduction
Small-signal equivalent circuit at low
frequencies
101
Small-signal schematic of a MOS transistor

at low frequencies
G
D
gm.vgs
gmb.vsb
go
S
B
iDS = f(vGS, vDS, vSB) = IDS + ids
DC
AC, small-signal
ids = gm.vgs + go.vds gmb.vsb
i DS
gm =
v GS
with vGS = VGS + vgs

vDS = VDS + vds
vSB = VSB + vsb
i DS
i DS
g0 =
= 1/ro=1/rds=gds g mb =
v SB
v DS
102
Low-frequency simplified smallsignal schematic for vsb = 0 V

drain
gate
+
vgs
gmvgs
ro
source
103
0.8
IDS
(A)
At VDS = 0 V: gm = 0, go 0
regardless of the inversion region
At VDS = 0V: IDS = 0 for any VGS
IDS/ VGS= 0 gm=0
0.6
VGS=VGS4
Small-signal equivalent circuit:
0.4
VGS=VGS3
drain
gate
vin
0.2
gmvin
ro
VGS=VGS2
0
0
source
VGS=VGS1
0.5
VDS (V)
1.5
2.5
104
gm in strong inversion, triode region

From level 3 expression of IDS :
IDS

W
2
a
(VGS VT ) VDS 2 VDS
gm =
=
C 'ox
VGS VGS
L
W
= C 'ox
VDS
L
This is only an approximation (for VOV 0.2V),

but trends remain valid:
gm is linearly proportional to W/L
gm=0 when VDS = 0 no active circuit anymore

105
gm in strong inversion, saturation

I DS
W

2
gm =
=
(VGS VT )
C 'ox
VGS
VGS
2aL
long-channel
approximation
W
W
= C 'ox
(VGS VT ) = C 'ox
VOV
aL
aL
(1)
only approximately valid for VOV 0.2 V

Eq. (1) can be reworked to
2 I DS
gm =
VOV
W
= 2 C 'ox
I DS
aL
(2)
(3)
106
gm/IDS in strong inversion, saturation

from eq. (2):
gm
2
=
I DS VOV
(for VOV 0.2 V)
The further in stronger inversion, the less economical

the transistor operates, since more current is required for a
given gm
At the edge of strong inversion: Vov = 0.2 V gm/IDS = 10 V-1
e.g. : we need a gm of 1 mS at VOV= 0.2 V we need a current of 0.1 mA
107
gm in strong inversion with severe

velocity saturation
With strong velocity saturation we found:
IDSAT
W v sat C 'ox
(VGS VT )
2a
W vsat C 'ox
independent of Vov and L
gm =
2a
gm
1
=
I DS VOV
108
gm and gm/IDS in weak inversion

I DS
VGS
exp
nU t
g m = I DS / VGS
VGS
1
gm
exp
nU t
nU t
gm
1
=
I DS nU t
109
gm/IDS is maximal in weak

inversion
strong inversion (VOV 0.2 V):
gm
2
=
I DS VOV
maximum value is 10 (for VOV = 0.2 V)

weak inversion:
gm
1
=
I DS nU t
close to 30 (for n = 1.3)
moderate inversion: transition between weak inversion

value and 2/VOV
110
gm increases with the inversion level

-2
10
-4
10
long-channel transistor
-6
gm(S)
10
-8
10
-10
10
-12
10
-0.6
-0.4
-0.2
0.2
0.4
0.6
0.8
1.2
VOV(V)
111
but gm/IDS decreases with

increasing inversion level
almost constant
in weak
inversion
long-channel transistor
gm/IDS (V-1)
10
proportional to Vov-1 in
strong inversion
10
-0.6
-0.4
-0.2
0.2
0.4
0.6
0.8
1.2 VOV (V)

112
Required width for a given gm

we know that
I DS
W
= C 'ox
f (VGS , VDS , VSB )
L
f: increases exponentially with VGS in weak inversion;

increases quadratically with VGS in strong inversion;
transition from exponential to quadratic in moderate inversion
W f
g m = C 'ox
L VGS
f/VGS: increases exponentially with VGS in weak inversion;

increases linearly with VGS in strong inversion;
transition from exponential to linear in moderate inversion
g m specified L
required W =
f
C 'ox
VGS
just as with the sizing of a transistor for a

specified current, we see that the required W
to realize a given gm decreases when the
inversion level increases
W decreases exponentially with increasing VGS in weak inversion

and with VGS-1 in strong inversion;
transition between exp(-VGS) and VGS-1 dependence in moderate inversion
113
Sizing of a MOS transistor based

on a specification for gm
similar procedure as for the sizing based on a specification for IDS
1. typically, we choose L
2. next we choose the inversion level
3. based on gm for a given reference
width and the spec on gm, we find the
width for the transistor
the lower the inversion level, the wider the
transistor will be
114
Evaluation of gm/IDS in 0.18 m CMOS

gm/I DS(n-MOS of UMC CMOS 180 nm, VSB = 0 V, VDS = 0.9 V)
40
35
Difference due to nshort channel > nlong channel
L =180nm
L = 2.00m
gm/IDS (V-1)
30
25
20
15
10
5
0
-0.5
weak inv.
max. and
constant
mod. inv.
0.5
1.5
VGS - VT (V)
strong inv.
115
Study of go
Large in the triode region
Much smaller in saturation
Nonzero due to CLM and DIBL
Dependent both on VGS and VDS
can be decreased by increasing the channel length
3
x 10
-7
go (VSB = 0 V, W = 10m, L = 0.18m, n-MOS of UMC CMOS 180 nm)

VGS=0.20
2.5
go (A/V)
saturation
1.5
1
0.5
0
0
0.2
0.4
0.6
1
0.8
VDS (V)
1.2
1.4
1.6
1.8
116
Value of go at VDS= 0 V in strong

inversion
I DS
g0 =
=
VDS VDS
2
a
(VGS VT ) VDS 2 VDS
C 'ox
L
for VDS = 0 V :
W
g 0 = C 'ox (VGS VT )
L
This is the same expression as for gm in strong inversion, saturation
We will use that when we will calculate the thermal noise from a MOS
transistor.
117
gm/go is the intrinsic gain of the transistor

maximum voltage gain vout/vin is
obtained for RL
This max. voltage gain is called
the intrinsic gain
VDD
RL
vout
M1
vin
small-signal circuit for RL :
vin
v out
gm
=
v in
g o + 1 / RL
vout
gate
gm vin
drain
go
source, bulk
v out g m
intrinsic gain =
=
v in
go
118
Evaluation of gm/go in 0.18 m CMOS

gm/go (VSB = 0 V, W = 10m, L = 0.18m, n-MOS of UMC CMOS 180 nm)
35
30
VGS=0.20
VGS=0.30
20
VGS=0.40
g /g (-)
25
15
VGS=0.50
VGS=0.60
10
VGS=0.70
VGS=0.80
VGS=0.90
0
0.2
0.4
0.6
1
0.8
VDS (V)
1.2
1.4
1.6
note: VT0 0.5 V119
gm/go decreases with downscaling

Channels become shorter
DIBL and CLM are more pronounced
e.g. 90 nm CMOS
n-MOS W=10 m, L = 90 nm
gm/go 20
measured
modeled
15
VDS=1.2 V
10
VDS=0.6 V
Technology
node
(gm/go)max
for Lmin (n-MOS)
180 nm
25 - 30
90 nm
10 - 15
65 nm and
beyond
< 10
0
0.4
0.6
0.8
1.0
1.2
VGS (V)
120
Bulk transconductance gmb < gm

gm/gmb (VSB = 0 V, W = 10m, L = 0.18m, n-MOS of UMC CMOS 180 nm)
7.1
7
6.9
mb
6.7
g /g
6.8
(-)
VGS=0.20
VGS=0.30
VGS=0.40
VGS=0.50
6.6
VGS=0.60
6.5
VGS=0.70
6.4
VGS=0.90
note:
VT0 0.5 V
VGS=0.80
0.2
0.4
0.6
0.8
1.2
1.4
1.6
VDS (V)
gm/gmb= 6 to 7 in this 0.18 m technology, gate control is

6 7 times stronger than body control
This ratio tends to increase with downscaling
121
122
Outline
Introduction
Small-signal equivalent circuit at low
frequencies
123
Capacitors in a MOS transistor

Associated to charge storage
small-signal operation: C = |q/v|=|Q/V|
Intrinsic capacitors
= capacitors that depend on the physical operation of
a MOS transistor, without taking into account its
connection to the outside world and inevitable
structures due to fabrication
Extrinsic capacitors
= capacitors that only depend on the connection of
the transistor to the outside world and on inevitable
structures due to fabrication
124
There are five intrinsic capacitors

Cgsi : between gate and source
Cgdi : between gate and drain
Cgbi : between gate and bulk
Cbsi : between bulk and source
Cbdi : between bulk and drain
125
Measurement of intrinsic capacitors

QG
QI
VG +
strong inversion situation

nonsaturation
+ + + + + + + + + +
gate oxide
B
VS +
+
QB
VB
QG = W QG' ( x )dx
0
VD
QB = W QB' ( x )dx
0
x=0
x=L
We will not elaborate the expressions

of QG and QB
We will apply a V and measure the resulting Q

at gate and bulk
Note that QI + QB + QG (+ Qox) = 0 (charge neutrality)
not shown
126
Applying VS identifies Cgsi

QG
QI
VG +
+ + + + + + + + + +
gate oxide
B
VS +
+
VB QB
QG+QG
+
VD
QI
VG +
+ + + + + + + + + +
gate oxide

VS +
+
+
+VS
V
V
D
B QB +QB
VS with constant VG OXIDE QG
Cgsi
QG
=
VS
VG ,VD ,VB
127
and Cbsi
QG
QI
QG+QG
VG +
+ + + + + + + + + +
gate oxide
B
VS +
+
VB QB
+
VD
QI
VG +
+ + + + + + + + + +
gate oxide

VS +
+
+
+VS
V
V
D
B QB +QB
VS with constant VB depletion zone extends (at least in mod.

and strong inv.)
QB more negative
Cbsi
QB
=
VS
VG ,VD ,VB
128
Definition of Cgdi, Cbdi and Cgbi

Cgdi and Cbdi are similar to Cgsi and Cbsi:
Cgdi
QG
=
VD
and
VG ,VS ,VB
Cbdi
QB
=
VD
VG ,VS ,VB
Cgbi: VB depletion zone narrows

QB less negative QG decreases
Cgbi
QG
=
VB
VG ,VS ,VD
129
Expressions of intrinsic capacitances in

strong inversion, VDS = 0
QG
+ + + + + + + + + +
gate oxide
QI
long channel
QB
B
Cgsi
Cgdi
1 '
= Cox WL
2
1 '
= Cox WL
2
Cbsi = Cbdi
1 '
= Cbc WL
2
'
: capacitance per unit area of the
Cbc
reverse
biased field-induced junction formed
by the inversion layer and the substrate:
C =
'
bc
Cox equally divided

between source and drain
Cgbi = 0
2 0 + VSB
'
Cox
bulk is invisible due to

shielding by inversion layer 130

strong inversion, saturation
QG
+ + + + + + + + + +
gate oxide
QI
Cgsi
2 '
= Cox WL
3
Cgdi = 0
Cgbi
< Cox !!
a 1
= Cox
3a
< Cbc
VD has no influence on
QG and QB
'
Cbc
WL
=
'
Cbc
31 + '
Cox
long channel
QB
Cbsi
2 '
= Cbc WL
3
Cbdi = 0
> 0 since bulk is visible at
drain side, due to absence of
inversion layer there
131

weak inversion, saturation
QG
QI
macroscopically
invisible
+ + + + + + + + + +
long channel
gate oxide

D
QB

B
C gsi = 0
Cbsi = 0
C gdi = 0
Cbdi = 0
C gbi = Cox' WL in series with Cchannel - bulk

in weak inversion: the only intrinsic capacitance is Cgbi
132
Proportional to W, expressed per unit width
- between gate and source (Cgso W)
[F/m]
- between gate and drain (Cgdo W)

[F/m]
Junction capacitors
depend on layout
- between source and bulk (Cjs)
- between drain and bulk (Cjd)
133
Extrinsic parts of Cgs and Cgd: Cgso and

Cgdo
They have 3 components,
each proportional to W
gate
Ctop
silicide
poly
Si
Cof: outer fringing

capacitance
source
silicide
tox
n-
n-
COV: overlap
capacitance
134
Total Cgs and Cgd: sum of intrinsic

and extrinsic parts
Cgs = Cgsi + Cgso
Cgd = Cgdi + Cgdo
135
Cbs and Cbd have intrinsic and

extrinsic part
Cbs = Cjs + Cbsi
junction
capacitance
intrinsic (see
previous slides)
Cbd = Cjd + Cbdi

junction
capacitance
intrinsic (see
previous slides)
Usually:
Cjs >> Cbsi
Cjd >> Cbdi
Junction capacitors dominate

intrinsic source-bulk and drain-bulk
capacitors
136
Extrinsic source-bulk and drain-bulk capacitors

have bottom plate and sidewall components
gate
silicide
poly
Si
STI
source
tox
n-
silicide
Cjswg
n+
drain
STI
silicide
n+
bulk
Cjsw
Cj
p
p
Cj: bottom plate capacitance (F/m2)
Cjsw: sidewall capacitance (F/m)
Cjswg: sidewall capacitance (F/m) at gate side
137
source
Sidewall capacitances are proportional to

perimeter of source/drain regions
drain source
drain
source
pdg: perimeter of the drain at the gate side
gate
gate
gate
gate
psg: perimeter of the source at the gate side
ps: perimeter of the source enclosed by STI

pd: perimeter of the drain enclosed by STI
lsos
lsogd
lsogs
lsogd
lsos
lsos: length of the source diffusion not between 2 poly stripes

lsogs: length of the source diffusion between 2 poly stripes
lsod: length of the drain diffusion not between 2 poly stripes (not present in this picture)
lsogd: length of the drain diffusion between 2 poly stripes
These distances are determined by the layout rules
138
source
Bottom plate capacitances are proportional

to area of source/drain regions
drain source
drain
source
as: area of source region
gate
gate
gate
gate
ad: area of drain region
139
Total extrinsic source-bulk

capacitance
C js = C j as + C jsw ps + C jswg psg
depend on VSB, since these are
junction capacitances
General expression for a junction capacitance:
C junction =
C junction V
inverse = 0
Vinverse
1 +
V
j
mj
Vj: junction potential (0.2 0.9 V)

mj: grading coefficient (0.3 0.5)
140
Total extrinsic drain-bulk

capacitance
Similar to Cjs:
C jd = C j ad + C jsw pd + C jswg pdg
141
Evaluation of Cgs in 0.18 m CMOS

normalized Cgs VSB = 0 V, L = 0.18m,n-MOS of UMC CMOS 180 nm, C'ox = 8.21fF/m2
1
strong inversion, saturation:

extrinsic + 2/3 Cox WL
triode
region
Cgs/(C'oxWL)
0.8
weak inversion:
only extrinsic
0.6
VDS=0.00
VDS=0.45
0.4
VDS=0.90
VDS=1.35
VDS=1.80
0.2
0
0
0.2
0.4
0.6
VT
0.8
1
VGS (V)
1.2
1.4
1.6
1.8
142
Evaluation of Cgd in 0.18 m CMOS
normalized Cgd VSB = 0 V, L = 0.18m,n-MOS of UMC CMOS 180 nm, C'ox = 8.21fF/m2
1
Cgd/(C'oxWL)
0.8
0.6
VDS=0.00
triode
region
VDS=0.45
VDS=0.90
VDS=1.35
VDS=1.80
0.4
0.2
0
0
0.2
0.4
weak inversion:
only extrinsic
0.6
VT
0.8
1
1.2
VGS (V)
1.4
1.6
strong inversion, saturation:

only extrinsic
1.8
143
Evaluation of Cgb in 0.18 m CMOS

normalized Cgb VSB = 0 V, L = 0.18m,n-MOS of UMC CMOS 180 nm, C'ox = 8.21fF/m2
0.25
Cgb/(C'oxWL)
0.2
weak inversion:
series connection of Cox
and depletion layer capacitance
VDS=0.00
VDS=0.45
strong inversion: series

connection of only a
small part of oxide
and depletion layer
capacitance
VDS=0.90
0.15
VDS=1.35
VDS=1.80
0.1
0.05
0.2
0.4
VT
0.6
0.8
1
|VGS| (V)
1.2
1.4
1.6
144
Capacitances in a MOS transistor

in saturation: summary
weak inversion
Cgb Cox
2 2 / 4 + VGB VFB
Cgs
Cgso W
Cgd
Cgdo W
strong inversion
+ Cgbo W
a 1
+ Cgbo W
Cox
3a
2
3
This image cannot currently be displayed.
Cox + Cgso W
Cgdo W
Cbs junction cap.
junction cap. +
Cbd junction cap.
junction cap.
2
3
Cox
2 0 + VSB
145
Speed of a MOS transistor is

expressed with cutoff frequency fT
Cutoff frequency fT = frequency at which the current gain of a

MOS transistor has dropped to an absolute
value of 1
iout
Cgd
1
Iin
Cgs+Cgb
g m v1
AC
short
circuit
i out
gm
current gain:
i in
(Cgs + Cgd + Cgb )
Cgg
146
Expression for fT
gm
gm
= 1 for f =
2 f Cgg
2 Cgg
gm
fT =
2 Cgg
fT depends on gm and hence on Vov:

10
f T (Hz)
10
10
10
10
12
10
180 nm CMOS:
fT in the vicinity
of 60 GHz
8
-0.4
-0.2
0.2
0.4
0.6
V
VT (V)
VGS -(V)
ov
0.8
1.2
1.4
147
fT increases when L decreases

Strong inversion, saturation:
W
g m = C 'ox
VOV and C gg C gs 23 C 'ox W L
aL
VOV
fT
2
2 aL
3
2
downscaling with L-2
with strong velocity saturation, fT only downscales with L-1:
W v sat C 'ox
gm =
2a
technology max. fT (GHz)

90 nm
150
65 nm
185
45 nm
280
v sat
fT
2 aL
3
4
downscaling with L-1
148
Parasitic resistors in source, drain

and bulk path are usually negligible
Usually much smaller than other resistors in the circuits
D'
G'
Rg
Cgd
G
Cgs
Rd
D
gmb
gm
drain
ro
Cgb
S
Rs
Csb
B
Rb
source
Cdb
S'
bulk
Rjs
Rjd
Rsub
B'
149
Gate resistance can play a role

at RF frequencies
e.g. input transistor of a low-noise amplifier:
small-signal
equivalent
input impedance
matching network
RG
Cgs+Cgb
at low frequencies: RG << 1/( (Cgs+Cgb))

at high frequencies: RG comparable to 1/( (Cgs+Cgb))
150
Gate resistance forms distributed RC

line with gate-channel capacitance
W
source
Rgate
gate
drain
diffusion
polysilicon
metal 1
1 W
RG
3 L
due to distributed
nature
Sheet resistance of
gate material
(polysilicon: 8/)
151
Double-sided gate contact

reduces RG with factor four
W
source
gate
Rgate
gate
drain
1 W
RG
12 L
152
Small-signal model of a MOS

transistor that is valid up to fT/10
gate
Cgb
Cgs
drain
Cgd
gmvgs
gmbvsb
ro
source
Cbd
Cbs
bulk
but this model is often used to higher frequencies
note: we neglected RG, RS, RD, RB
153
For higher frequencies: use of

transcapacitances
= non-reciprocal capacitances
Qx Qy
Vy
Vx
effect of voltage change at terminal x

on charge at terminal y effect of
voltage change at terminal y on
charge at terminal x
This can be modeled using

capacitors and
transcapacitances (= reactive
transconductances)
vcontrol
This means that CxyCyx

e.g. CgdiCdgi
+
sCxvcontrol
-
Cx: transcapacitance
154
Model with transcapacitances is

OK until fT/2
gate
Cgb
Cgs
drain
Cgd
gmbvsb Cmb
dv sb
dt
gmvgs Cm
dv gs
dt
ro
Cbd
source
Cbs
Cmx
Csd
dv gb
dt
bulk
long channel, strong inversion, saturation:
4
Cm =
Cox
15
Cmb =
Cmx = 0
Csd = 0
2 0 + VSB
Cm
155
Beyond fT/2: use of non-quasistatic

model
Non-quasistatic behavior: charge in the
channel cannot follow the voltage
variations at gate, source, drain or bulk
156
Outline
Introduction
157
Matlab table for MOS

transistors
large table
iD(vGS, vDS, vSB, L)
gm(vGS, vDS, vSB, L)
determined for one W, denoted by Wref
Example:
table for 0.18 m CMOS process
go (vGS, vDS, vSB, L)
Wref = 10 m
gmb (vGS, vDS, vSB, L)
based on simulations with BSIMv3
49 VGS values
Cgs (vGS, vDS, vSB, L)
49 VDS values
9 VSB values
VT(vGS, vDS, vSB, L)
11 L values
size: 100 MB for n-MOS + p-MOS
VDSAT(vGS, vDS, vSB, L)
extrinsic junction capacitors:
2
Sv, white(vGS, vDS, vSB, L) [V /Hz]
not in the table
computed separately, based on
Sv, 1/f(vGS, vDS, vSB, L) [V2/Hz]
number of fingers
158
Table-based transistor sizing

in
Matlab
Example: we need g = 0.01 S for transistor M in 90 nm process
m
n1
In Matlab: Mn1.w = mosWidth(Mn1, gmSpec, L, vgs, vds, vsb)

gm (S)
0.01
gmSpec = 0.01 S
L = 90 nm
0.008
design choice
VGS = 0.6 V
0.0069
design choice
0.006
VDS = 0.6 V
estimate or known
0.004
VSB = 0 V
from circuit topology
0.002
This yields:
0.01
W of Mn1= 10
0.0069
VGS=0.9
= 14.5 m
0
0
VGS=1.05
VGS=1.2
VGS=0.75
90 nm CMOS IMEC
VSB = 0 V
L = 0.09 m
W = 10 m
VGS=0.6
VGS=0.45
VGS=0.3
0.2
0.4
0.6
0.8
1.2
VDS (V)159
DC operating point can be

computed completely in Matlab
using interpolation in tables
only iteration required for transistors with body effect
Fixed-point iteration, very few steps required (5)
agreement with Spice DC solution better than 2 %

enables Matlab-based circuit design
Designer stores his/her considerations in a design plan (=
Matlab file)
Design plans make use of approximate expressions for
poles, zeros, gain, offset, noise,
Design plan can be reused
for different specs

for different technologies (simply load a different table)
Allows for accurate power estimation

Successfully applied to opamps, charge pumps, VCOs,
active filters, crystal oscillators
160
General procedure to size a

transistor (1/2)
1. Choose channel length for transistor(s)
2. Choose inversion level of transistor(s) by specifying
overdrive voltage Vov = VGS - VT
For strong inversion Vov should be > 0.2 V (for n-MOS)
For moderate inversion Vov < 0.2 V (for n-MOS)
For weak inversion Vov is certainly < 0, but limit between
weak and moderate inversion can differ from technology to
technology
3. Determine W using a specification for a parameter

such as gm, IDS, , in combination with estimates for
the terminal voltages VGS, VDS, and VSB
An estimate of VGS is derived from the chosen VOV and an
estimate of VT, since VGS = Vov + VT
161
General procedure to size a

transistor (2/2)
4. Choose number of fingers and multiplicity of the transistor

1. If necessary, the lengths lsos, lsogs, lsogd and lsod of the diffusion areas
can also be specified
2. if nothing specified, then the default value is used for the multiplicity and the
length of the diffusion areas
W / nFingers
L
source
drain
gate
source
drain
source
lsos
lsogd
lsogs
lsogd
lsos
5. At this moment, the transistor is completely determined. Now

the rest of the parameters can be determined
6. Check whether the transistor is saturated
(if this was assumed)
162
Sizing of a MOS transistor in 0.18 m

CMOS with specification on gm
Specification: gm = 2 mS
Given voltages: VDS = 0.6 V, VSB = 0 V
We choose L = Lmin
We choose VOV = 0 V (moderate inversion)
163
From Vov and VT(VDS) we find VGS

VT (V) 0.54
0.53
0.52
L = 0.18 m
VSB = 0V
0.51
0.5
0.49
0.48
0.47
0.46
0.45
0.2
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VDS (V)
Vov = 0.0 V and VT = 0.5 V VGS = Vov + VT = 0.5 V

164
Determination of W based on spec

for gm
gm
1.5
[S]
1.25
x 10
-3
W = 10 m
L = 0.18 m
VGS = 0.5 V
VSB = 0 V
0.853 mS
0.75
We need gm = 2 mS
W = 10 m
0.5
0.25
0.853
0
0
0.2
= 23.45 m
This is an acceptable width
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VDS [V]
165
All other operating point parameters can

now be determined except for junction caps
Example: IDS = (current for Wref) W/Wref
IDS
[A]
1.2
depends on amount of
fingers
x 10 -4
W = 10 m
L = 0.18 m
VGS = 0.5 V
VSB = 0 V
0.8
0.6
0.0511 mA
0.4
0.2
0.2
0.4
0.6
0.8
1.2
Since W = 23.45 m, IDS = 0.0511 mA 23.45/10 = 0.12 mA
1.4
1.6
1.8
VDS [V]
166
Triode region
go
[mS]
Similar for go
CLM dominates
DIBL dominates
0.6
0.5
W = 10 m
L = 0.18 m
VGS = 0.5 V
VSB = 0 V
0.4
0.3
0.2
0.1
34 S
0
0
0.2
0.4
0.6
0.8
1.2
1.4
Since W = 23.45 m, go = 23.45/10 34 S = 80 S
1.6
VDS [V]
Wref
N.B.: gm/go = 2 mS/0.08 mS = 25
167
Capacitors Cgs, Cgd, Cgb, Cdbi and Csbi

C
[F]
1.2
x 10
-14
Cdbi (Csbi): intrinsic part of Cdb (Csb)
8.51 fF
W = 10 m
L = 0.18 m
VGS = 0.5 V
VSB = 0 V
Cgs
Cgd
CsbI
CdbI
Cgb
0.8
0.6
0.4
0.2
0 0
Cgs = Cgs
0.2
W = Wref
0.4
0.6
0.8
1.2
1.4
1.6
1.8
VDS [V]
W
23.45
= 8.51 fF
= 20 fF
Wref
10
Similarly we find: Cgd =8.79 fF, Cgb = 4 fF, Cdbi= 2.62 aF, Csbi = 1.53 fF
168
Junction capacitor depends on areas,

perimeters, and voltage over junction
extrinsic part
of Cdb
CdbE = ad
extrinsic part
of Csb
CsbE = as
C j0
VDB
1 +
PB
mj
C j0
VSB
1 +
PB
mj
+ pd
+ ps
C jsw0
VDB
1 +
PBSW
mjsw
C jsw0
VSB
+
1
PBSW
mjsw
+ pdg
+ psg
C jswg 0
VDB
1 +
PBSWG
mjswg
C jswg 0
VSB
+
1
PBSWG
mjswg
bottom-plate
sidewall capacitances
capacitances
Cj0, Cjsw(g)0, PB, PBSW(G), mj and mjsw(g) depend on the CMOS process
For an nMOS in a typical 0.18 m process:
cj0: 1 mF/m2
cjsw0: 13.4 nF/m
cjswg0: 13.4 nF/m
pb: 0.813 V
pbsw: 0.88 V
pbswg: 0.88 V
mj: 0.443
mjsw: 0.33
mjswg: 0.33
For an pMOS: similar values (but pb, pbsw, pbswg < 0)
169
Computation of CdbE and CsbE as a

function
of
number
of
fingers
20
CdbE
[fF]
10
CsbE
[fF]
number of fingers
number of fingers
20
10
source
drain
S
D
D D
S
S
D
S
D
S
170
Comparison of parasitic capacitors: Cgs is

the largest in moderate/strong inversion
25
C
[fF]
4 fingers
20
15
10
Cgs
Cgd
Cgb
Cdb
Csb
Dominance of Cgs is even more pronounced in strong inversion
171
Check for saturation: VDS > VDSAT ?

VDSAT
[V]
1.6
1.4
L = 0.18 m
VDS = 0.6 V
VSB = 0V
1.2
1
0.8
0.6
0.4
0.2
0.09 V
0
-0.2
-0.4
-0.5
0.5
VDS = 0.6 V > VDSAT = 0.09 V
1.5
Vov [V]
OK !
172

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Chapter 1:

Microelectronics obeys Moores law

Roadmap according to this law: International

ITRS predicts CMOS downscaling until

Cutoff frequency f [GHz]

Upgrade of technology yields reduction in area per function and

CMOS has replaced bipolar and GaAs in

Commercial CMOS radio ICs

Ideal MOS transistor in saturation is

|VCONTROL|=|VCONTROL7| (> |VCONTROL6|)

|VCONTROL|=|VCONTROL6| (> |VCONTROL5|)

Symbols for an n-MOS transistor

VGS=VGS7 (> VGS6)

More positive VGS

VGS=VGS6 (> VGS5)

Symbols for a p-MOS transistor

More negative VGS

|VGS|=|VGS6| (> |VGS5|)

Real transistor characteristics

not really flat

IMEC 90 nm CMOS process

The simple quadratic MOS model

if |VGS| < |VT|: IDS = 0

if |VGS| sufficiently above |VT|:

Saturation (|VDS| > |VDSAT|):

Small-signal equivalent circuit

The reality is less ideal

and many more effects

Cross-section of an n-MOS transistor

metallization not shown

Triple-well process gives n-MOS

Further processing steps until metal eight

Top view of a MOS transistor

Layout of a MOS transistor

MOS two-terminal structure

MOS structure: a field-effect device,

VT: threshold voltage

positive gate charge

depletion zone (negative charge)

MOS structure: a field-effect device,

positive gate charge

MOS structure: a field-effect device,

positive gate charge

MOS structure: a field-effect device,

positive gate charge

MOS structure: a field-effect device,

positive gate charge

MOS structure: a field-effect device,

positive gate charge

MOS structure: a field-effect device,

positive gate charge

MOS structure: a field-effect device,

positive gate charge

MOS structure: a field-effect device,

positive gate charge

MOS structure: a field-effect device,

positive gate charge

MOS structure: a field-effect device,

positive gate charge

Drain-to-source voltage brings induced

positive gate charge

There are three inversion regimes:

VFB: flat-band voltage

VT0 decreases as oxide gets thinner ( decreases)