NEXT GENERATION SET TOP BOX

H.265/HEVC decoder solution for the Set Top Box industry

Presented by,
H.265 decoder

Deepak
Guided by,

Dr D. R. Sk

Outline
Objective
Outcomes
Introduction
Motivation

Problem Statement
Block diagram of HEVC
Simulation and analysis
Proposed System Design
Implementation Details
Conclusions
References

Objectives
To design:
A system capable of decoding the next generation video standards(HEVC)

A all in one solution Set-Top-Box by combining traditional broadcasting and

modern internet applications

A smart home system with the implementation of IOT

Outcomes
Able to deliver high quality video which can be played in SDTV, HDTV,4k and

8k televisions.
Improves the coding efficiency
Last but not the least, it can make life easy with its smart features.

INTRODUCTION

History in brief
Analog broadcasting

continuously variable signal

Digital Broadcasting

binary on/off bitssequences of 0s

and 1s
Advantages:
over-the-air digital signals dont
weaken over distance
no ghosts caused by interference
no fuzziness or snow in the picture
Requires less bandwidth to
broadcast

Why set top box ?

Market survey

The stair case to Quality Heaven

Source: N. Narita, M.Kanazawa, and F.Okano, Optimum screen parameters for ultrahigh definition and wide-screen image systems:
Study of screen aspect ratios and maximum pixels with still images, J. Inst. Television Eng. Jpn.,vol 56, no. 3,pp. 437-446,2013

Motivation
Video exceeds half of internet traffic and will
grow to 86 percent by 2016. Increase in
applications, content, fidelity, etc. Need
higher coding efficiency !
Ultra-HD 4k broadcast expected for Japan in
2015. London Olympics Opening and
Closing Ceremonies shot in Ultra-HD 8k.
Need higher throughput !
25x increase in mobile data traffic over next
five years. Video is a must have on portable
devices. Need lower power !

Sources: Cisco Visual Networking Index

Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update

CAN WE HAVE A BETTER

TECHNOLOGY ?

News & Events !!

HEVC (HIGH EFFICIENCY VIDEO

CODING)
H.265

Problem Statement
HEVC based decoder design for Set Top Box application
The modern advancements in video compression gives us the idea of squeezing more pixels through

bandwidth-limited channels which is critical in the rapid growth of video usage.

As we go for higher coding efciency, greater resolution and more sophisticated multimedia applications,

the computational complexity and the pixel processing rate will grow exponentially.
The High Efciency Video Coding (HEVC) standard was developed in January 2013 to address these

challenges. But a suitable and efficient hardware design to support HEVC encoding and decoding is still
under research.
The main objective of this project is to make hardware to support HEVC decoding and to build a Set-Top-

Box using the same. Here, the system design is challenging because it incorporates the real time issues
like memory, power and cost.

History of the standards

Source: ISCAS Tutorial 2014

Block diagram of a HEVC encoder with built-in decoder

H.265/HEVC vs H.264/AVC Decoder

Larger and flexible coding
block size

Decoded Pixels

Picture Buffer
Larger
interpolation Filter

Motion
Compensation
Encoded
bitstream

Entropy
Decoder

Intra
Prediction

Q-1 + T-1

More prediction
Modes

Larger
transforms and
more sizes

Sample
Adaptive
Offset
De-blocking
Filter

Fewer
Edges

High level parallelization features

Picture level parallelization
Slice level parallelization
Block level parallelization
Wavefront parallel processing (WPP)

Tiles

Simulation and analysis :

Software used : Elecard StreamEye HEVC Analyzer

Fig-1 : First frame of the imported HEVC Video

Simulation and analysis : continued

Fig-2: Blocks and partition scheme of HEVC

Simulation and analysis : continued

Fig-3: Prediction type analysis

Simulation and analysis : continued

Red Intra prediction

Blue Inter prediction
(with only 1 reference)
Green Inter prediction
(Bi-directional)
White Skip blocks

Fig-3 : Prediction analysis of 21st frame

Simulation and analysis : continued

Fig-3 : Residual Picture

Residual picture = Original frame Predicted frame

Simulation and analysis : continued

Fig-3 : Motion vectors estimation

Project Plan
Work to do

Months

Literature Study-1 (Concept & Basics)

August

Software analysis and simulation

September

Literature Study-2 (Algorithm and architecture)

October

Decoder Design and simulation

November

Hardware design for decoder

December

Literature Study-3 ( Set top box design)

January

Interfacing and System Integration

February and March

ASIC/FPGA based Design

April

Detailed Design and testing

May

Proposed System Design

Set Top Box with HEVC decoder

More number of interfaces for

several multi-media applications

Some salient features of IPTV

Internet of Things

Software and hardware implementation details

MATLAB Implementation
Hardware Modeling in Verilog HDL
FPGA prototype Implementation
Cadence ASIC implementation

Conclusion
HEVC has an unique nested quadtree-based block partitioning feature that

helps in better prediction and coding

Half of the coding efciency improvements of HEVC relative to H.264/MPEG-4

AVC for HD video material is obtained solely by introducing this exible block
partitioning concept for improved prediction and transform coding.
Furthermore, the two novel picture partitioning features of tiles and wavefront

parallel processing can improve the parallel-processing friendliness of HEVC

in order to meet the increased demand in computational complexity

References
Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, Ajay Luthra, Overview of the

H.264/AVC Video Coding Standard, IEEE Transaction on Circuits and Systems for
Video Technology, Vol. 13, No. 7, July 2003

G. J. Sullivan,et al."Overview of the High Eciency Video Coding (HEVC) standard,

IEEE Transactions on Circuits and Systems for Video Technology, 2012

V. Sze, M. Budagavi,G. J. Sullivan (Editors),High Eciency Video Coding (HEVC):

Algorithms and Architectures, Springer, 2014

Andr Borin Soares, Alexsandro Cristvo Bonatto, and Altamiro Amadeu Susin,

Development of a SoC for Digital Television Set-Top Box: Architecture and System
Integration Issues, Hindawi Publishing Corporation, International Journal of
Reconfigurable Computing, Article ID 783501, 10 pages, 2013

THANK YOU