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Why does the present VLSI circuits use MOSFETs instead of BJTs explain?
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What are the various regions of operation of MOSFET? How are those regions used? Explain?
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Explain:
a.) Clock Race
b.) Single Phase Clocking
c.) Double Phase Clocking
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Explain the following effects and how would you eliminate them.
a.) Hot electron effect.
b.) Latchup problem
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Explain:
a.) Mobility of electrons
b.) Mobility of holes
c.) Stage Ratio
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Differentiate between:
a.) Testing and Verification
b.) Latch and Flip Flop
c.) Depletion mode devices and Enhancement mode devices
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Explain elextron migration. What would you do if you want to eliminate it?
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Explain:
a.) Elmore delay algorithm
b.) False and multi cycle paths
c.) Metastability
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What do you mean by negative biased instability? How can you avoid it?
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What factors would you consider while choosing a technology library for a design?
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Situation:
a.) You want to equate rise and fall times in a inverter. How would you do that?
b.) A resistor is added in series with the drain in a mos transistor. What would happen?
c.) Suppose Vds is increased over saturation. What would happen?
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What will be the effect of increase in the number of contacts and vias in the interconnect layers?
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25. Explain
a.) Body bias
b.) Charge sharing on a bus
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In the I-V characteristics curve, what does flat or constant saturation curve signify?
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Can both pmos and nmos transistors pass good 1 and good 0? Explain?
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. You want to reduce charge sharing in dynamic logic. What are the different methologies you can use?
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Explain setup and hold time violations? How can they be eliminated?
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What is the effect of increasing thickness and increasing length on the resistance of a metal layer?
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You want to change the voltage for less delay. What limitation you might face? How would you achieve this?
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You are given NAND gates and NOR gates, which of them would you take? Why?
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39. Explain Noise margin in an inverter. How would you overcome it?
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40. What is the effect of delay, rise and fall times with increase in load capacitance?
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Why is size of pmos transistor chosen to be close to three times of an nmos transistor?
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a.) What are the substrates of pmos and nmos transistors connected to?
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b.) What would happen if the connections are interchanged with each other?
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45. While trying to drive a huge load, driver circuits are designed with number of stages with a gradual increase in sizes. Why is it done?
Why can't you use just one big driver gate?
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Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later
than signal B. To optimize delay of the two series NMOS inputs A and B which one would
you place near to the output?
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For CMOS logic, give the various techniques you know to minimize power consumption?
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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a
Bus?
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Why do we gradually increase the size of inverters in buffer design? Why not give the
output of a circuit to one large inverter?
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What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you
avoid Latch Up?
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How does Resistance of the metal lines vary with increasing thickness and increasing
length?
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What are the limitations in increasing the power supply to reduce delay?
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What is Synthesis?
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What is DFT ?
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What is LVs and why do we do that. What is the difference between LVS and DRC?
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What are different types of FPGA programming modes?what are you currently using ?
how to change from one to another?
79. What is minimum and maximum frequency of dcm in spartan-3 series fpga?
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What is FPGA ?
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A good question on Layouts. Give 5 important Design techniques you would follow when
doing a Layout for Digital Circuits?
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All of us know how an inverter works. What happens when the PMOS and NMOS are
interchanged with one another in an inverter?
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In CMOS technology, in digital design, why do we design the size of pmos to be higher
than the nmos.What determines the size of pmos wrt nmos. Though this is a simple
question try to list all the reasons possible?
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Why do we gradually increase the size of inverters in buffer design when trying to drive a
high capacitive load? Why not give the output of a circuit to one large inverter?
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what is slice,clb,lut?
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synthesize to?
8. Differences between functions and Procedures in VHDL?
9. Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?
Verilog
What is the difference between $display and $monitor and $write and $strobe?
What is the difference between bit wise, unary and logical operators?
Write a verilog code to swap contents of two registers with and without a temporary register?
What is the difference between inter statement and intra statement delay?
why?
In a pure sequential circuit is it necessary to mention all the inputs in sensitivity disk? If yes, why? If not, why?
Will case always infer priority register? If yes how? Give an example.