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may have anywhere between about 32 and 200+ channels they can monitor, each channel
monitoring one digital line.
Displays logic states: The vertical display on the analyzer displays the logic state as a high of
low state. The signals enter the various channels and are converted into a high or low state for
further processing within the analyzer. It provides a logic timing diagram of the various lines
being monitored.
Does NOT display analogue information : These test instruments do not present any analogue
information, and in this way they differ from an oscilloscope. They are purely aimed at
monitoring the logic operation of the system. If any analogue information is required, then an
oscilloscope must be used in addition.
logic analyzer types:
Modular logic analyzers : This type of logic analyzer is probably what may be thought of as
the most typical form of test instrument, although it is the highest cost option providing the
highest level of functionality. It comprises a chassis and the various modules - including channel
modules. The number of modules being larger for the higher channel counts.
Portable logic analyzers : In a number of instances there may be a need for a smaller analyzer,
possibly for restricted budgets or for field service. These test instruments incorporate all
elements of the analyzer into a single box for ease of transportation.
PC based logic analyzers: There is a growing number of PC based logic analyzers. These
consist of an analyzer unit that is connected to a PC. This form of PC based instrument uses the
processing power of the PC combined with its display to reduce the cost of the overall system.
A logic analyzer is like an oscilloscope that is used to view multiple digital binary
waveforms. We use logic analyzer for precise hardware troubleshooting, especially for timing
issues. While we focus on microcontrollers here, logic analyzers can be used for any type of
digital circuit that has a binary output. We can set the threshold values for the logic highs and
lows in the logic analyzer software. In the LA2124 Logic Analyzer we use in this demo and the
EE3176 labs, the threshold is set at 1.40 V, so a signal voltage > 1.40 volts is a logical one, while
a voltage less than 1.40 V is a logical 0. This is a 24 channel analyzer that can hold 128Kbytes of
data in the buffer, and samples at rates up to 100 M samples/sec (50 MHz bandwidth). It hooks
up to the parallel port of your PC, and displays the data on the CRT. The 24 channels are
displayed simultaneously, so we can easily see timing relations between the different digital
sources. We can also set up complicated trigger events with the logic analyzer that are not
possible with the oscilloscope.
Although the operation of a logic analyzer may appear to be fairly complicated at first
sight, a methodical approach to the use of one enables it to be set up correctly and to be used
effectively. Once the probes are connected, the logic analyzer is programmed with the names of
each signal. The analyzer can also associate several signals into groups so that they can be
manipulated more easily.
With the basic set-up of the logic analyzer complete the capture mode for the data needs to be
chosen. This can be set to one of two modes:
Timing mode : Using this mode signals are sampled at regular intervals based on an internal or
external clock.
The output of a Logic Analyzer is usually in one of two forms. Most commonly, we use a timedomain display, where the binary waveforms from one or more digital sources is viewed as a
function of time. An example screenshot from the LA-2124 Timing View is shown below:
Note that the time division of the grid (dashed vertical lines) above is 10 useconds ("u" for
micro) per division. So, for the Channel 0 waveform, the first pulse train starts at 11 usec, with
the first few pulses having a 2 usec period .
State mode : Here one or more of the signals are defined as clocks, and data is sampled on the
edges of these clocks.
We can also view the logic analyzer output in the "state" domain. This gives us the binary output
in terms of 0's and 1's.:
we can group channels into logical groups that make sense for the problem at hand. In the
view above, Group 1 is formed from Channels 0-7, with Channel 0 being the leftmost bit and
Channel 7 being the rightmost bit in that group. So, at 1 usec., Channel 0 has binary value "0",
Channel 1 = 0, ..., Channel 7 = 0. At 11 usec., Channels 0,1 and 3 turn "on" and are binary 1s,
while the others are binary 0s. This state view corresponds to the time domain view above, so we
can directly compare them.
Once the logic analyzer mode is chosen then the trigger condition can be set. The
analyzer trigger condition may vary from a very simple signal edge to a set of conditions that
must be met across a variety of lines. The complex trigger conditions aid in locating problems
that occur when a particular set of conditions occur.With the trigger condition set, the logic
analyzer can be set to run, triggering once only, or repeatedly. The data that is captured can then
be displayed and analysed.
By using a logic analyzer is it possible to be able to look at these lines in a practicable
fashion and be able to trigger on a preset pattern of a given number of lines. In this way the
events that happen after a predetermined occurrence can be viewed for investigation. This is
invaluable in enabling fault finding of complex software driven circuits.
Triggering :
Specifications:
The specification for a logic analyzer covers many areas of its performance, but there are a
number of parameters that are key to ensuring that it will meet the majority of its operational
requirements and be fit for the purpose for which it was intended.
Logic analyzer speed
One of the major requirements for any logic analyzer is the speed of the instrument. With today's
high speed circuits it will be necessary to the logic analyzer to typically deliver sub nano-second
resolution.
The speed of the logic analyser is chiefly governed by the timing resolution. This is the smallest
time element that the analyser can see. If the resolution is too coarse then it will not be possible
to see many of the fast occurrences happening in the circuits.
The speed of the analyzer must be such that it is able to capture and display a variety of scenarios
ranging from transient glitches, any variety of software instructions which may lead to problems
occurring, timing violations, or set-up conditions. It is often within these areas that the difficult
problems can be found, and it is here that the capability of the logic analyzer is needed. Without
sufficient speed many of these elements will not be seen.
Logic analyzer channels
Today's digital circuits are becoming more complicated, and they are normally software driven.
This means that it is important to ensure that sufficient channels are available within the logical
analyzer. Often high end processor designs require between 50 and 150 channels to cover all the
lines that are relevant to the testing. If a logic analyzer with insufficient number of inputs is
purchased, then this will considerably hamper testing.
Unfortunately, increasing the number of channels in a logic analyzer considerably increases the
complexity of the instrument..
To help reduce this problem, most logic analyzers have only a proportion of their channels that
support the full specification in terms of speed in resolution. As it is un-necessary for all the
channels to be able operate at the maximum spec, reducing the performance of some simplifies
the circuitry and reduces the requirements for memory and processing.
Logic analyzer memory
In order that the logic analyzer can display the information it retrieves, it must store it in
memory. If only a small amount of memory is available then it will only be able to store short
sequences, and this may be insufficient to analyze all the events occurring. Additionally a greater
the number if inputs, longer sequences that need to be stored, and greater levels of resolution
increase the requirement for memory. As memory can be expensive, it is necessary to gain a
sensible balance between memory requirements and cost for the logic analyzer.often memory
requirements may be reduced by turning off some functions such as time stamping, etc that may
be essential for some debugging.