1.

INTRODUCTION

VHDL stands for VHSIC Hardware Description Language. VHSIC is an

abbreviation for Very High Speed Integrated Circuit, a project sponsored by the US Government
and Air Force begun in 1980 to advance techniques for designing VLSI silicon chips and to
develop very high speed integrated circuits. VHDL is an IEEE standard. It is a hardware
description language used in electronic design automation to describe digital and mixed-signal
systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used
as a general purpose parallel programming language. It has become now one of the industrys
standard languages used to describe and simulate complex digital systems. The other widely used
hardware description language is Verilog. Both are powerful languages that allow us to describe
and simulate complex digital systems. A third HDL language is ABEL (Advanced Boolean
Equation Language) which was specifically designed for Programmable Logic Devices (PLD).
ABEL is less powerful than other two languages and is less popular in industry.
VHDL is though similar to other programming languages, there are some important
differences. A hardware description language is inherently parallel i.e. commands, which
correspond to logic gates are executed (computed) in parallel as soon as new input arrives. It also
allows incorporation of timing specifications (gate delays) as well as to describe a system as an
interconnection of different components.
VHDL can wear many hats. It is being used for documentation, verification, and
synthesis of large digital designs. This is one the features of VHDL, since the VHDL code can
theoretically achieve all three of these goals, thus saving a lot of efforts. For these purposes, VHDL
can be used to take three different approaches to describe hardware which are structural, data flow,
and behavioral methods. Most of the times mixture of these three methods are employed.
VHDL is designed to fill a number of needs in designing process. A digital electronic
system can be described as a module of inputs and/or outputs. Firstly, is allows description of
structure of a design that is how it is decomposed into sub-designs, and how those sub-designs are
interconnected. Secondly, it allows the specification of the function of designs using familiar
programming language forms. Thirdly, as a result, it allows a design to be simulated before being
1

manufactured, so that designers can quickly can quickly compare alternatives & test for
correctness without the delay & expenses of hardware prototyping.

VHDL allows you to specify:

1. The components of a circuit.
2. Their interconnection.
3. The behavior of the components in terms of their input and output signals.

2. HISTORY

VHDL was originally developed at the behest of the U.S Department of Defense in
order to document the behavior of the ASICs that supplier companies were including in equipment.
The idea of being able to simulate the ASICs from the information in this
documentation was so obviously attractive that logic simulators were developed that could read
the VHDL files. The next step was the development of logic synthesis tools that read the VHDL,
and output a definition of the physical implementation of the circuit.
Due to the Department of Defense requiring as much of the syntax as possible to be
based on Ada, in order to avoid re-inventing concepts that had already been thoroughly tested in
the development of ADA, VHDL borrows heavily from the ADA programming language in both
concepts and syntax.
The initial version of VHDL, designed to IEEE standard 1076-1987, included a wide
range of data types, including numerical (integer and real), logical (bit and Boolean), character and
time, plus arrays of bit called bit_vector and of character called string.
A problem not solved by this edition, however, was "multi-valued logic", where a
signal's drive strength (none, weak or strong) and unknown values are also considered. This
required IEEE standard 1164, which defined the 9-value logic types: scalar std_logic and its
vector version std_logic_vector.
The updated IEEE 1076, in 1993, made the syntax more consistent, allowed more
flexibility in naming, extended the character type to allow ISO-8859-1 printable characters,
added the XNOR operator, etc.
Minor changes in the standard (2000 and 2002) added the idea of protected types
(similar to the concept of class in C++) and removed some restrictions from port mapping rules.

In addition to IEEE standard 1164, several child standards were introduced to extend
functionality of the language. IEEE standard 1076.2 added better handling of real and complex
data types. IEEE standard 1076.3 introduced signed and unsigned types to facilitate arithmetical
operations on vectors. IEEE standard 1076.1 (known as VHDL-AMS) provided analog and mixedsignal circuit design extensions.
Some other standards support wider use of VHDL, notably VITAL (VHDL Initiative
towards ASIC Libraries) and microwave circuit design extensions.
In June 2006, the VHDL Technical Committee of Accellera (delegated by IEEE to
work on the next update of the standard) approved so called Draft 3.0 of VHDL-2006. While
maintaining full compatibility with older versions, this proposed standard provides numerous
extensions that make writing and managing VHDL code easier. Key changes include incorporation
of child standards (1164, 1076.2, 1076.3) into the main 1076 standard, an extended set of operators,
more flexible syntax of case and generate statements, incorporation of VHPI (interface to C/C++
languages) and a subset of PSL (Property Specification Language). These changes should improve
quality of synthesizable VHDL code, make testbenches more flexible, and allow wider use of
VHDL for system-level descriptions.
In February 2008, Accellera approved VHDL 4.0 also informally known as VHDL
2008, which addressed more than 90 issues discovered during the trial period for version 3.0 and
includes enhanced generic types. In 2008, Accellera released VHDL 4.0 to the IEEE for balloting
for inclusion in IEEE 1076-2008. The VHDL standard IEEE 1076-2008 was published in January
2009.

3. LEVELS OF REPRESENTATION & ABSTRACTION

A digital system can be represented at different level of abstraction. This keeps the
description and design of complex system manageable. The highest level of abstraction is the
behavioral level that describes a system in terms of what it does (or how it behaves) rather than
in terms of its components and interconnection between them. A behavioral description specifies
the relationship between the input and output signals. This could be a Boolean expression or a
more abstract description such as the Register Transfer or Algorithm level. As an example, let us
consider a simple circuit that warns car passengers when the door is open or the seatbelt is not used
whenever the car key is inserted in the ignition lock, at the behavioral level it could be expressed
as,
Warning = Ignition_on AND (Door_open OR Seatbelt_off)
The structural level, on the other hand, describes a system as a collection of gates
and components that are interconnected to perform a desired function. A structural description
could be compared to a schematic of interconnected logic gates. It is a representation that is usually
closer to the physical realization of a system. For the example above, the structural representation
is shown in the figure:

Door

Warning

Ignition
Seat Belt

VHDL allows one to describe a digital system at the structural or the behavioral level.
The behavioral level can be further divided into two kinds of styles: DATA FLOW and
ALGORITHMIC. The data flow representation describes how data moves through the system.
This is typically done in terms of data flow registers (Register transfer level). The data flow model
makes use of concurrent statements that are executed in parallel as soon as data arrives at the input.
On the other hand, sequential statements are executed in the sequence that they are specified.
VHDL allows both concurrent and sequential signal assignments that will determine the manner
in which they are executed.
In many cases, it is not appropriate to describe a module structurally. One such case
is a module which is at the bottom of the hierarchy of some other structural description. For
example, if we are designing a system using IC packages bought from an IC shop, we do not need
to describe the internal structure of an IC. In such cases, a description of the function performed
by the module is required, without reference to its actual internal structure. Such a description is
called functional or behavioral description. To illustrate this, suppose that the function of the entity
F is the exclusively OR function. Then a behavior description of F could be the Boolean function.
Y = B + AB
More complex behaviors cannot be described purely as a functions of inputs. In
systems with feedback, the outputs are also a function of time. VHDL solves this problem by
allowing description of behavior in the form of an executable program.

4. DISCRETE TIME EVENT MODEL

Once the structure and behavior of a model have been specified, it is possible to
simulate the module by executing its behavior description. This is done by simulating the passage
of time in discrete steps. At some simulation time, a module input may be simulated by changing
the value on an input port. The module reacts by running the code of its behavioral description and
scheduling new values to be placed on the signals connected to its output ports at some later
simulated time. This is called scheduling a transaction on that signal. If the new value is different
from the previous value on the signal, an event occurs, and other modules with the input ports
connected to the signal may be activated,
The simulation starts with an initialization phase, and then proceeds by repeating a
two stage simulation cycle. In the initialization phase, all the signals are given initial values, the
simulation time is set to zero, and each modules behavior program is executed. This usually results
in transaction being scheduled on output signals for some later time.
In the first stage of simulation cycle, the simulated time is advanced to the earliest
time at which a transaction has been scheduled. All transactions scheduled for that time are
executed, and this may cause events to occur on some signals. In the second stage, all modules
which react to events occurring in the first stage have their behavior program executed. These
programs will usually schedule further transactions on their input signals. When all of the behavior
programs have finished executing, the simulation cycle repeats. If there are no more scheduled
transactions, the whole transactions completed.
The purpose of simulation is to gather information about the changes in system state
over time. This can be done by running the simulation under the control of a simulation monitor.
The monitor allows signals and other state information to be viewed or stored in a trace file for
later analysis. It may also allow interactive stepping of the simulation process, much like an
interactive program debugger.

5. VHDL DESIGN FLOW

INITIAL DESIGN FLOW

LOGIC OPTIMIZATION

TECHNOLOGY MAPPING

PLACEMENT

ROUTING

PROGRAMMING UNIT

CONFIGURED FPGA
FIGURE: Design Flow of an Integrated Circuit

The starting point of design process is the initial logic entry of the circuit that is to be
implemented. The step typically involves drawing a schematic capture program, entering a VHDL
description, or specifying Boolean expressions.
Regardless of the initial design entry, the circuit description is usually translated into
a standard form such as Boolean expressions. The Boolean expressions are then processed by a
logic optimization tool, which manipulate the expressions. The goal is to modify these expression
to optimize the area or speed of the final circuit. A combination of both are and delay requirements
may also be considered. This optimization usually performs the equivalent of an algebraic
minimization of the Boolean expressions and it is appropriate when implementing a logic circuit
in any medium, not just FPGAs.
The optimized Boolean expressions must next be transformed into a circuit of FPGA
logic blocks. A technology mapping program does this. The mapper may attempt to minimize the
total number of blocks required, which is known as area optimization. Alternatively, the object
may be to minimize the number of stages of logic blocks in time-critical paths, which is called
delay optimization.
Having mapped the circuit into logic blocks, it is necessary to decide where to place
each block in the FPGAs array. A placement program is used to solve this problem. Typical
placement algorithm attempt to minimize the total length of interconnect required for the resulting
placement.
The final step in the CAD system is performed by the routing software, which assigns
the FPGA wire segment and chooses programmable switches to establish the required connection
among logic blocks. The routing software must ensure the 100% of the required connections are
formed, otherwise the circuit cannot be realized in a single FPGA. Moreover it is often necessary
to do routing such that the propagation delays in time-critical connections are minimized.
Upon successful completion of the placement and routing steps, the CAD systems
output is fed to programming unit, which configures the final FPGA chip. The entire process of
implementing a circuit in an FPGA can take from few minutes to about an hour, depending on
which FPGA is being used.

6. VHDL TERMS
The terms, which are of reference and common usage in VHDL programming, are as
follows:
Entity: A hardware abstraction of digital system is called entity. All designs
are expressed in entities.
Architecture: All entities that can be simulated have architecture description.
The architecture describes the behavior of entity.
Configuration: A configuration is used to bind a component instance to an
entity architecture pair. A configuration like parts list for a design.
Package: A package is a collection of commonly used data types and
subprograms used in a design. Package is just like a tool box that contains tools
used to build designs.
Bus: The term bus usually to mind a group of signals.
Attribute: An attribute is data attached to VHDL objects or predefined data
above VHDL objects.

Process: A process is a basic unit of execution in VHDL source code. All

operations that are performed in a simulation of a VHDL description are broken
into single or multiple processes.

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7. BASIC STRUCTURE OF VHDL FILE

A digital system in VHDL consists of a design entity that can contain other entities
that are then considered components of top-level entity. Each entity is modeled by an entity
declaration and an architecture body. One can consider the entity declaration as the interface to the
outside world that defines the input and output signals, while the architecture body contains the
description of the entity and is composed of interconnected entities, processes and components, all
operating concurrently, as schematically shown in figure below. In a typical design there will be
many such entities connected together to perform the desired function.

Figure: A VHDL entity consisting of an interface (entity declaration) and a body

(architecture description)
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VHDL uses reserved keywords that cannot be used as signal names or identifiers.
Keywords and user-defined identifiers are case sensitive. Lines with comments start with two
adjacent hyphens (--) and will be ignored by the compiler. VHDL also ignores line breaks and
extra spaces. VHDL is a strongly typed language which implies that one has always to declare
the type of every object that can have a value, such as signals, constants and variables.

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8. ENTITY DECLARATION
The entity declaration defines the NAME of the entity and lists the input and output
ports. The general form is as follows,
entity NAME_OF_ENTITY is [(generic generic_declarations);]
port (signal_names: mode type;
signal_names: mode type);
end [NAME_OF_ENTITY];
An entity always starts with the keyword entity, followed by its name and the keyword
is. Next are the port declarations using the keyword port. An entity declaration always ends with
the keywords end, optionally [] followed by the name of the entity.

The NAME_OF_ENTITY is a user-selected identifier.

signal_names consists of a comma separated list of one or more user-selected

identifiers that specify external interface signals.

mode: is one of the reserved words to indicate the signal direction.

in: indicates the signal is an input.

out: indicates that the signal is an output of the entity whose values can be read
by other entities that use it.

buffer: indicates that the signal is an output of the entity whose value can be
read inside the entities architecture.

inout: the signal can be input or an output.

type: a built-in or user-defined signal type. Examples of types are bit,

bit_vector, Boolean, character, std_logic and std_ulogic.

bit: can have the value 0 and 1.

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bit_vector: is a vector of bit values (e.g. bit_vector(0 to 7)).

std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9

values to indicate the value and strength of a signal. Std_ulogic and std_logic
are preferred over the bit or bit_vector types.

Boolean: can have the value TRUE and FALSE.

Integer: can have a range of integer values.

real: can have a range of real values.

character: any printing character.

time: to indicate time.

generic: generic declarations are optional and determine the local constants
used for timing and sizing (e.g. bus widths) the entity. A generic can have a
default value.

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9. ARCHITECTURE BODY
The internal details of an entity are specified by an architecture body using any of the
following modeling styles:
1. As a set of interconnected components (to represent structure),
2. As a set of concurrent assignment statements (to represent dataflow),
3. As a set of sequential assignment statements (to represent behavior),
4. Any combination of the above three.
9.1 Structural Style of Model
In the structural style of modeling, an entity is described as a set of interconnected
components. Such a model for the HALF_ADDER entity, is described in an architecture body as
shown below.

Figure: HALF ADDER

entity HALF_ADDER is
port (A, B: in BIT; SUM, CARRY: out BIT);
end HALF_ADDER;
architecture HA_STRUCTURE of HALF_ADDER is
component XOR2
port (X, Y: in BIT; Z: out BIT);
end component;
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component AND2
port (L, M: in BIT; N: out BIT);
end component;
begin
X1: XOR2 port map (A, B, SUM);
A1: AND2 port map (A, B, CARRY);
end HA_STRUCTURE;
The name of the architecture body is HA_STRUCTURE. The architecture body is
composed of two parts: the declarative part (before the keyword begin) and the statement part
(after the keyword begin). Two component declarations are present in the declarative part of the
architecture body. These declarations specify the interface of components that are used in the
architecture body. The components XOR2 and AND2 may either be predefined components in a
library, or if they do not exist, they may later be bound to other components in a library.
The declared components are instantiated in the statement part of the architecture body
using component instantiation statements. XI and A1 are the component labels for these
component instantiations. The first component instantiation statement, labeled XI, shows that
signals A and B (the input ports of the HALF_ADDER), are connected to the X and Y input ports
of a XOR2 component, while output port Z of this component is connected to output port SUM of
the HALF_ADDER entity.
Similarly, in the second component instantiation statement, signals A and B are
connected to ports L and M of the AND2 component, while port N is connected to the CARRY
port of the HALF_ADDER. Note that in this case, the signals in the port map of a component
instantiation and the port signals in the component declaration are associated by position (called
positional association). The structural representation for the HALF_ADDER does not say anything
about its functionality. Separate entity models would be described for the components XOR2 and
AND2, each having its own entity declaration and architecture body.

16

9.2 Dataflow Style of Model

In this modeling style, the flow of data through the entity is expressed primarily using
concurrent signal assignment statements. The structure of the entity is not explicitly specified in
this modeling style, but it can be implicitly deduced. Consider the following alternate architecture
body for the HALF..ADDER entity that uses this style.
architecture HA_CONCURRENTof HALF_ADDER is
begin
SUM <= A XOR B ;
CARRY <= A AND B ;
end HA_CONCURRENT;
The dataflow model for the HALF_ADDER is described using two concurrent signal
assignment statements . In a signal assignment statement, the symbol <= implies an assignment of
a value to a signal. The value of the expression on the right-hand-side of the statement is computed
and is assigned to the signal on the left-hand-side, called the target signal. A concurrent signal
assignment statement is executed only when any signal used in the expression on the right-handside has an event on it, that is, the value for the signal changes.
9.3 Behavioral Style of Model
In contrast to the styles of modeling described earlier, the behavioral style of modeling
specifies the behavior of an entity as a set of statements that are executed sequentially in the
specified order. This set of sequential statements, that are specified inside a process statement, do
not explicitly specify the structure of the entity but merely specifies its functionality. A process
statement is a concurrent statement that can appear within an architecture body. For example,
consider the following behavioral model for the TWO INPUT AND GATE.

entity AND2 is
17

port (in1, in2 : in std_logic; out1: out std_logic);

end AND2;
architecture behavioral of AND2 is
begin
out1<=in1 and in2;
end behavioral;

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10. LEXICAL ELEMENTS

Identifiers
An identifier in VHDL is used as reserved word and as programmer defined names.

They must conform to the rule:

identifier ::=letter { [underline] letter_or_digit }
Note that case of letters is not considered significant, so the identifiers cat and Cat are
same. Underline characters in identifiers are significant, so This_Name and This Name are
different identifiers.

Character set
The character set in VHDL87 is 128 characters, in VHDL93 it is 256
characters. The character set is divided into seven groups
Uppercase letters, Digits, Special characters, the space characters, Lowercase
letters, other special characters and format effector.

Separators
Separators are used to separate lexical elements. An example is the space character

(SPACE).

Delimiters
A delimiter is one of the following characters or character combinations:
& ( ) * + , - . / : ; < = > | [ ] => ** := /= >= <= <>

Literals
A literal is a written value of a type. There are in total five different kinds of literals.
1. Numerical literals:
Numerical literals of universal_integer do not include a point, literals of

universal_real do include a point, while literals of physical types may include a point and must
include a unit.
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All numerical literals may include:

_ to increase readability, e.g.: 1_000
E or e to include an exponent, e.g.: 5E3 (i.e. 5000).
# to describe a base, e.g.: 2#1010# (i.e. 10). It is possible to have a base
between 2 and 16.
A physical type must include a space between its value and its unit, e.g.:
1 ns
2. Enumeration literals:
[e.g.: BIT, BOOLEAN, CHARACTER]
Enumeration literals are graphical characters or identifiers , e.g.:
(reset, start, a, A).
3. String literals:
[e.g.: STRING)
String literals are one-dimensional arrays including character literals. They always
begin end end with a (the character may be included in the literal,
but must then be doubled, e.g.: A character).
4. Bit string literals
[e.g: BIT_VECTOR, STD_LOGIC_VECTOR*]
Bit string literals are one-dimensional arrays including extended digits. They always
begin and end with a .
It is possible to include a base for a bit string literal. There are three bases:
B - Binary (possible values: 0 - 1).
O - Octal (possible values: 0 - 7). Each value is replaced by three values (0 or 1).
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X - Hexadecimal (possible values: 0 - 9, A - F, a - f). Each value is replaced by four

values (0 or 1).
A bit string literal may include _ to increase readability, e.g.: 0100_
0111.
5. The NULL literal:
[NULL]
The NULL literal is only used for access types, i.e. pointers and imply that the pointer
is empty, i.e. not pointing anywhere.

DATA objects: Signals, Variables and Constants:

Every data object belongs to one of the following three classes:
1. Constant: An object of constant class can hold a single value of a given type. This

value is assigned to the object before simulation starts and the value cannot be changed during the
course of the simulation.
2. Variable: An object of variable class can also hold a single value of a given type.
However in this case, different values can be assigned to the object at different times using a
variable assignment statement.
3. Signal: An object belonging to the signal class has a past history of values, a current
value, and a set of future values. Future values can be assigned to a signal object using a signal
assignment statement.

Constant Declarations:
Examples of constant declarations are
constant RISE_TIME: TIME := 10ns;
constant BUS_WIDTH: INTEGER := 8:

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The first declaration declares the object RISE_TIME that can hold a value of type
TIME (a predefined type in the language) and the value assigned to the object at the start of
simulation is 10 ns. The second constant declaration declares a constant BUS_WIDTH of type
INTEGER with a value of 8.

Variables:
Examples of variable declarations are
variable CTRL_STATUS: BIT_VECTOR(10 downto 0);
variable SUM: INTEGER range 0 to 100 := 10;
variable FOUND, DONE: BOOLEAN;
The first declaration specifies a variable object CTRL_STATUS as an array of II

elements, with each array element of type BIT. In the second declaration, an explicit initial value
has been assigned to the variable SUM. When simulation starts, SUM will have an initial value
of 10. If no initial value is specified for a variable object, a default value is used as an initial value.
This default value is T'LEFT, where T is the object type and LEFT is a predefined attribute of a
type that gives the leftmost value in the set of values belonging to type T. In the third declaration,
the initial values assigned to FOUND and DONE at start of simulation is FALSE (FALSE is the
leftmost value of the predefined type, BOOLEAN). The initial value for all the array elements of
CTRL_STATUS is '0'.

Signals:
Here are some examples of signal declarations.
signal CLOCK: BIT;
signal DATA_BUS: BIT_VECTOR(0 to 7);
signal GATE_DELAY: TIME := 10 ns;
The interpretation for these signal declarations is very similar to that of the variable

declarations. The first signal declaration declares the signal object CLOCK of type BIT and gives

22

it an initial value of '0' ('0' being the leftmost value of type BIT). The third signal declaration
declares a signal object GATE_DELAY of type TIME that has an initial value of 10 ns.

Data Types
Every data object in VHDL can hold a value that belongs to a set of values. This set of

values is specified by using a type declaration. A type is a name that has associated with it a set of
values and a set of operations. Certain types, and operations that can be performed on objects of
these types, are predefined in the language. For example, INTEGER is a predefined type with the
set of values being integers in a specific range provided by the VHDL system. The minimum range
that must be provided is -(231 - 1) through +(231 - 1). All the possible types that can exist in the
language can be categorized into the following four major categories:
1. Scalar types: Values belonging to these types appear in a sequential order.
2. Composite types: These are composed of elements of a single type (an array type) or elements
of different types (a record type).
3. Access types: These provide access to objects of a given type (via pointers).
4. File types: These provides access to objects that contain a sequence of values of a given type.

Composite Types
A composite type represents a collection of values. There are two composite types: an

array type and a record type. An array type represents a collection of values all belonging to a
single type; on the other hand, a record type represents a collection of values that may belong to
same or different types. An object belonging to a composite type, therefore, represents a collection
of sub objects, one for each element of the composite type. An element of a composite type could
have a value belonging to either a scalar type, a composite type, or an access type. For example, a
composite type may be defined to represent an array of an array of records. This provides the
capability of defining arbitrarily complex composite types.

Operators

23

The predefined operators in the language are classified into the following five
categories:
1. Logical operators, e.g.: and, or, nand, nor, xor, not
2. Relational operators, e.g.: =, /= , <, <=, >, >=
3. Adding operators, e.g.: +, -, &
4. Multiplying operators, e.g.: *, /, mod, rem
5. Miscellaneous operators, e.g.: abs, **

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11. SEQUENTIAL STATEMENTS

In this section, first some aspects related to processes are described, such as process
specification, process execution, wait statement, and the difference between combinational and
sequential processes. Then the sequential statements that may appear in a process or subprogram
are presented: sequential signal assignment, variable assignment, if statement, case statement, loop
statements (loop, while loop, for loop, next, exit), and the sequential assert statement. Besides
these statements, other sequential statements are the procedure call statement and the return
statement from a procedure or function.
11.1 Processes
A process is a sequence of statements that are executed in the specified order. The
process declaration delimits a sequential domain of the architecture in which the declaration
appears. Processes are used for behavioral descriptions.
SYNTAX : [name:] process [(sensitivity_list)]
[type_declarations]
[constant_declarations]
[variable_declarations]
[subprogram_declarations]
begin
sequential_statements
end process [name];
The process declaration is contained between the keywords process and end process.
A process may be assigned an optional name for simpler identification of the process in the source
code. The name is an identifier and must be followed by the ':' character. This name is also useful
for simulation, for example, to set a breakpoint in the simulation execution. The name may be
repeated at the end of the declaration, after the keywords end process.

25

The optional sensitivity list is the list of signals to which the process is sensitive. Any
event on any of the signals specified in the sensitivity list causes the sequential instructions in the
process to be executed, similar to the instructions in a usual program. As opposed to a
programming language, in VHDL the end process clause does not specify the end of process
execution. The process will be executed in an infinite loop. When a sensitivity list is specified, the
process will only suspend after the last statement, until a new event is produced on the signals in
the sensitivity list. Note that an event only occurs when a signal changes value. Therefore, the
assignment of the same value to a signal does not represent an event.
When the sensitivity list is missing, the process will be run continuously. In this case,
the process must contain a wait statement to suspend the process and to activate it when an event
occurs or a condition becomes true. When the sensitivity list is present, the process cannot contain
wait statements.
11.2 Wait Statement
Instead of a sensitivity list, a process may contain a wait statement. The use of a wait
statement has two reasons:
To suspend the execution of a process;
To specify a condition that will determine the activation of the suspended process.
When a wait statement is encountered, the process in which appears that statement
suspends. When the condition specified in the wait statement is met, the process resumes and its
statements are executed until another wait statement is encountered. The VHDL language allows
several wait statements in a process. When used to model combinational logic for synthesis, a
process may contain only one wait statement. If a process contains a wait statement, it cannot
contain a sensitivity list.
There are three forms of the wait statement:

wait on sensitivity_list;

wait until conditional_expresion;

wait for time_expression;

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11.3 If Statement
The if statement selects one or more statement sequences for execution, based on the
evaluation of a condition corresponding to that sequence. The syntax of this statement is the
following:
if condition then statement_sequence
[elsif condition then statement_sequence...]
[else statement_sequence]
end if;
11.4 Case Statement
Like the if statement, the case statement selects for execution one of several alternative
statement sequences based on the value of an expression. Unlike the if statement, the expression
does not need to be Boolean, but it may be represented by a signal, variable, or expression of any
discrete type (an enumeration or an integer type) or a character array type (including bit_vector
and std_logic_vector). The case statement is used when there are a large number of possible
alternatives. This statement is more readable than an if statement with many branches, allowing to
easily identify a value and the associated statement sequence.
The syntax of the case statement is the following:
case expression is
when options_1 =>
statement_sequence
...
when options_n =>
statement_sequence
[when others =>
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statement_sequence]
end case;
11.5 Loop Statement
The simple loop statement has the following syntax:
[label:] loop
statement_sequence
end loop [label];
The statement has an optional label that may be used to identify the statement. The
loop statement has the effect of repeating the statements within the statement body an unlimited
number of times. With this statement, the only possibility to end the execution is to use an exit
statement
11.5.1 While loop Statement
The while loop statement is a conditional loop statement. The syntax of this statement
is the following:
[label:] while condition loop
statement_sequence
end loop [label];
The condition is tested before each execution of the loop. If the condition is true, the
sequence of statements within the loop body is executed, after which the control is transferred to
the beginning of the loop. The loop execution terminates when the condition tested becomes false,
in which case the statement that follows the end loop clause is executed.
Example : process
variable count: integer := 0;
begin
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wait until clk = '1';

while level = '1' loop
count := count + 1;
wait until clk = '0';
end loop;
end process;
11.5.2 For loop Statement
For the repeated execution of a sequence of statements a fixed number of times, the
for loop statement may be used. Example :
for i in 1 to 10 loop
i_square (i) <= i * i;
end loop;
11.6 Next Statement
There are cases when the statements remaining in the current iteration of a loop must
be skipped and the execution must be continued with the next iteration. In these cases the next
statement may be used. The syntax of this statement is the following:
next [label] [when condition];
11.7 Exit Statement
There are situations when the execution of a loop statement must be stopped
completely, either as a result of an error occurred during the execution of a model or due to the
fact that the processing must be terminated before the iteration count exceeds its range. In these
situations, an exit statement may be used. The syntax of this statement is the following:
exit [label] [when condition];

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12. CONCLUSION
12.1 CAPABILITIES OF VHDL

Implementation of any circuit idea like complete robot design.

Microprocessor of your own configuration.

Direct hardware interaction.

12.2 SPECIAL FEATURES OF VHDL

Portability

Each level of abstraction

Not technology specific

IEEE & ANSI standardized

Large projects can be easily designed

12.3

ADVANTAGES

OF

VHDL

OVER

OTHER

PROCEDURAL

LANGUAGES:

Main difference between VHDL and other programming languages like C/C++ are:

VHDL is a parallel language while C/C++ is procedural language. Sequential

language. Each statement occurring in VHDL is executed concurrently i.e. all
statements run simultaneously. In C/C++ each statement is executed in sequential
order and its own turn. In VHDL, explicit constructs exist for explicit sequential
steps.

VHDL is a strongly typed language. It doesnt allow any mismatching of types,

though type conversion is permitted.

VHDL allow use of explicit time delay, which is not applicable in procedural
language. In procedural languages, the right hand side value is assigned to the left
hand side as soon as statement is executed.

VHDL model cannot be implemented in real time application directly like other
procedural languages. It is simulated and synthesized using in built system clock.

30

REFERENCES
Here's a list of suggested texts for learning more about VHDL.

1) Douglas L. Perry, VHDL, Tata Mc Graw Hill, International Edition 1999.

2) XILINX INC, XILINX Foundation Series User Reference Guide.
3) XILINX INC, XILINX Software Sampler Quick Start Guide.
4) J. BHASKAR, A VHDL PRIMER, Pearson Education Asia, Third Edition
1999.

5) S. M. KANG & YUSUF LEBLEBICI, CMOS Digital Integrated Circuits,

analysis and design, WCB Mc Graw Hill, International Edition 1999.

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