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Shift Register
SequentialLogic/Circuits:
ShiftRegister
Combinational
logic
Memory
outputs
Memory
elements
Inputs
Registers
A register is a memory device that can be used to
store more than one-bit information
A register is usually realized as several flip-flops
with common control signals that control the
movement of data to and from the registers
.
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Shift Registers
Registers
An n-bit register is a collection of n D flip-flops with a
common clock used to store n related bits.
Example:
74LS175 4-bit register
74LS175
1D
D
CLR
2D
D
CLR
3D
CLK
/CLR
D
CLR
4D
D
CLR
/1Q
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
1Q
CLK
CLR
LSI
1 LSI
2Q
/2Q
1D
3Q
2D
/3Q
4Q
/4Q
3D
4D
1Q
1Q
2Q
2Q
3Q
3Q
4Q
4Q
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
RSI
74LS175
When a 1 is on D, Q
becomes a 1 at
triggering edge of CLK
or remains a 1 if already
in the SET state
When a 0 is on D, Q
becomes a 0 at
triggering edge of CLK or
remains a 0 if already in
the RESET state
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SO
CLK
SRG n
>
SI
CLK
Serial Out
CLK
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Clock
CLK
1Q
2Q
>
SI
SRG n
1Q
2Q
SO
nQ
CLK
nQ
CLK
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Example:
Thestatesof4bitregister(SRG4)forthedatainputandclocks
waveforms.
CLOCK
LOAD/SHIFT
Serial in
1D
1Q
CLK
S
2D
2Q
CLK
Parallel to Serial
Converter
Load/Shift=1
D i Qi
Load/Shift=0
Qi Qi+1
ND
S
L
NQ
Serial out
CLK
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CLOCK
LOAD/SHIFT
Serial In
1D
2Q
NQ
CLK
ND
General Purpose:
Makes any kind of
(left) shift register
1Q
CLK
S
2D
D
CLK
Datacanbeshiftedleft
Datacanbeshiftedright
Aparallelloadmaybepossible
74HC194isanbidirectionaluniversalshiftregister
Modes:
Hold
Load
Shift Right
Shift Left
10
9
7
6
5
4
3
2
CLK
CLR
S1
S0
LIN
D
C
B
A
RIN
74x194
QD
QC
QB
QA
12
13
14
15
Mode
S1 S0
0
0
0
1
1
0
1
1
QA*
QA
RIN
QB
A
Next state
QB* QC*
QB QC
QA QB
QC QD
B
C
QD*
QD
QC
LIN
D
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Serial output
connected back
to serial input
The complement
of the output (Q)
is fedback into
1st FF.
Assume initial
state:
1010000000
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CTL
CLK
CLOCK
Transmitter
Control
Circuits
Parallel
Data from
A-to-D
converter
n
Control
/SYNC
>
Circuits
Serial DATA
One bit
x6
x5
y7
y6
y5
x0
...
Receiver
>
Parallelto-serial
converter
x7
Parallel
Data to
D-to-A
converter
Serial-toparallel
converter
n
y0
...
Cin A
FA
Cout
CLK
CLR
B
S
>
CLEAR_C
z7
z6
z5
...
...
0
z0