Sei sulla pagina 1di 8

9/16/2015

Shift Register

SequentialLogic/Circuits:
ShiftRegister

Sequential Logic Circuits


Combinational
outputs

Combinational
logic

Memory
outputs

Memory
elements

Inputs

Sequential circuit = Combinational logic + Memory Elements

Basic shift register function


Serial in/Serial out shift registers (SISO)
Serial in/Parallel out shift registers (SIPO)
Parallel in/Serial out shift registers (PISO)
Parallel in/Parallel out shift registers
(PIPO)
Bidirectional shift registers
Shift register applications

Registers
A register is a memory device that can be used to
store more than one-bit information
A register is usually realized as several flip-flops
with common control signals that control the
movement of data to and from the registers
.

Current State of A sequential Circuit:


Value stored in memory elements (value of state variables).
State transition:
A change in the stored values in memory elements thus changing
the sequential circuit from one state to another state.

9/16/2015

Shift Registers

Registers
An n-bit register is a collection of n D flip-flops with a
common clock used to store n related bits.
Example:
74LS175 4-bit register

74LS175
1D

D
CLR

2D

D
CLR

3D

CLK
/CLR

D
CLR

4D

D
CLR

Multi-bit register that moves stored data bits left/right ( 1


bit
position
per clock
Shift
Left iscycle)
towards MSB

/1Q

Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

1Q

CLK
CLR

LSI

1 LSI

2Q
/2Q

1D

3Q

2D

/3Q
4Q
/4Q

3D
4D

1Q
1Q
2Q
2Q
3Q
3Q
4Q
4Q

Shift Right (or Shift Up) is towards MSB


RSI

Q3 Q2 Q1 Q0

Q3 Q2 Q1 Q0

RSI

74LS175

Basic Shift Register Functions


consist of an arrangement of flip-flops
important in applications involving storage and
transfer of data (data movement) in digital system
used for storing and shifting data (1s and 0s)
entered into it from an external source and
possesses no characteristic internal sequence of
states.
D flip-flops are use to store and move data

The flip-flop as a storage element

When a 1 is on D, Q
becomes a 1 at
triggering edge of CLK
or remains a 1 if already
in the SET state

When a 0 is on D, Q
becomes a 0 at
triggering edge of CLK or
remains a 0 if already in
the RESET state

9/16/2015

Basic data movement in shift registers


(Four bits are used for illustration. The bits move in the
direction of the arrows.)

Serial In, Serial Out Shift Registers


(SISO)
Serial In
Clock

Serial In, Serial Out Shift Registers


(SISO)

SO

For a n-bit SRG:


Serial Out = Serial In delayed
by n clock period

CLK

Serial In / Serial Out Shift Registers


(SISO)
Serial In /Parallel Out Shift Registers
(SIPO)
Parallel In / Serial Out Shift Registers
(PISO)
Parallel In / Parallel Out Shift Registers
(PIPO)

SRG n
>
SI

CLK

Types of Shift Registers

Serial Out

4-bit shift register example:


Serial in: 1 0 1 1 0 0 1 1 1 0
Serial out: - - - - 1 0 1 1 0 0
Clock:

CLK

9/16/2015

Serial In, Serial Out Shift Registers


(SISO)

Serial In, Parallel Out Shift registers


(SIPO)
Serial In

Clock

CLK

1Q

2Q

>
SI

SRG n
1Q
2Q
SO

nQ

Serial to Parallel Converter

CLK

nQ

Example: 4-bit shift register


serin: 1 0 1 1 0 0 1 1 1 0
1Q: - 1 0 1 1 0 0 1 1 1
2Q: - - 1 0 1 1 0 0 1 1
3Q: - - - 1 0 1 1 0 0 1
4Q: - - - - 1 0 1 1 0 0
clock:

CLK

9/16/2015

Serial In, Parallel Out Shift registers


(SIPO)

Example:

Thestatesof4bitregister(SRG4)forthedatainputandclocks
waveforms.

Data bits entered serially (right-most bit first)


Difference from SISO is the way data bits are taken out of the register in
parallel.

Assume the register initially contains all 1s

Output of each stage is available

Parallel In, Serial Out Shift Registers


(PISO)

4-bit parallel in/serial out shift register (PISO)

CLOCK
LOAD/SHIFT

Serial in

1D

1Q

CLK

S
2D

2Q

CLK

Parallel to Serial
Converter
Load/Shift=1
D i Qi
Load/Shift=0
Qi Qi+1

ND

S
L

NQ

Serial out

CLK

9/16/2015

Parallel In, Parallel Out Shift Register


(PIPO)

Parallel In, Parallel Out Shift Register (PIPO)

CLOCK
LOAD/SHIFT

Serial In

1D

2Q

NQ

CLK

ND

General Purpose:
Makes any kind of
(left) shift register

1Q

CLK

S
2D

D
CLK

Bi-directional Shift Registers

Immediately following simultaneous entry of all data


bits, it appears on parallel output.

Bi-directional Universal Shift Registers


11

Datacanbeshiftedleft
Datacanbeshiftedright
Aparallelloadmaybepossible
74HC194isanbidirectionaluniversalshiftregister

Modes:
Hold
Load
Shift Right
Shift Left

10
9

7
6
5
4
3
2

CLK
CLR
S1
S0
LIN
D
C
B
A
RIN

74x194

QD
QC
QB
QA

12

13
14
15

4-bit Bi-directional Universal (4-bit) PIPO


Function
Hold
Shift right/up
Shift left/down
Load

Mode
S1 S0
0
0
0
1
1
0
1
1

QA*
QA
RIN
QB
A

Next state
QB* QC*
QB QC
QA QB
QC QD
B
C

QD*
QD
QC
LIN
D

9/16/2015

Four-bit Johnson counters

Five-bit Johnson counters

Serial output
connected back
to serial input
The complement
of the output (Q)
is fedback into
1st FF.

A 10-bit ring counter

Shift Register Applications


State Registers

Shift registers are often used as the state register in a sequential


device. Usually, the next state is determined by shifting right and
inserting a primary input or output into the next position (i.e. a
finite memory machine)
Very effective for sequence detectors

Serial Interconnection of Systems

keep interconnection cost low with serial interconnect

Assume initial
state:
1010000000

Bit Serial Operations


Bit serial operations can be performed quickly through device
iteration
Iteration (a purely combinational approach) is expensive (in terms
of # of transistors, chip area, power, etc).
A sequential approach allows the reuse of combinational
functional units throughout the multi-cycle operation

9/16/2015

Shift Register Applications Example:


Serial Interconnection of Systems

CTL
CLK

CLOCK
Transmitter

Control
Circuits

Parallel
Data from
A-to-D
converter
n

Shift Register Applications Example:


8-Bit Serial Adder

Control

/SYNC

>

Circuits

Serial DATA
One bit

x6

x5

y7

y6

y5

x0
...

Sequential Implementation of:


Z[7..0] = X[7..0] + Y[7..0]

Receiver

>

Parallelto-serial
converter

x7

Parallel
Data to
D-to-A
converter

Serial-toparallel
converter
n

y0
...

Cin A
FA
Cout

CLK
CLR

B
S
>

CLEAR_C

z7

z6

z5

...
...

0
z0

Shift Register Applications Example:


The shift register as a time-delay device

Shift Register Applications Example:


Simplified logic diagram of a serial-to-parallel converter

Potrebbero piacerti anche