Boolean and Gate

Logic Gates and Boolean algebra
Dr. V. S. Bist, STO (Electronics),

USIC, HNB Garhwal University, Srinagar (Garhwal) 246174, India
E-Mail:vsbist_usic68@yahoo.com
1. Introduction:
A logic gate is an idealized or physical device implementing a Boolean function,
that is, it performs a logical operation on one or more logic inputs and produces a
single logic output. Depending on the context, the term may refer to an ideal logic
gate, one that has for instance zero rise time and unlimited fan-out, or it may refer
to a non-ideal physical device. (see Ideal and real op-amps for comparison)
Logic gates are primarily implemented using diodes or transistors acting
as electronic
switches,
but
can
also
be
constructed
using
electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics,
molecules or even mechanical elements. With amplification, logic gates can be
cascaded in the same way that Boolean functions can be composed, allowing the
construction of a physical model of all of Boolean logic, and therefore, all of the
algorithms and mathematics that can be described with Boolean logic.
In 1854 a British mathematician, George Boole, developed Boolean algebra.
Instead of an algebra that uses numbers, Boolean algebra uses truth values,
true (1) and false (0). By defining sentences using truth values and performing
operations on truth tables. Boolean algebra has had a massive impact on Computer
Science and the language that computers understand is a language of 1s and 0s,
Boolean.
Logic gates are pieces of hardware that perform operations on Boolean inputs,
allowing us to create complex devices out of abstract Boolean algebra. Logic
gates are the fundamental building blocks of hardware and processors will be
made out of billions of them. A logic gate will typically have one or more inputs,
and single output. There are six types of gate that you need to know, they are
AND, OR, NOT, NAND, NOR and XOR.
First, we need a mathematical framework for describing the relationship between
logic gates and binary numbers. That framework is Boolean algebra. This
document of course provides only an introduction to Boolean algebra; refer to
dedicated texts for a detailed discussion of the subject. The English mathematician
George Boole (1815-1864) sought to give symbolic form to Aristotle's system of
logic. Boole wrote a treatise on the subject in 1854, titled An Investigation of the
Laws of Thought, on Which Are Founded the Mathematical Theories of Logic
and Probabilities, which codified several rules of relationship between
mathematical quantities limited to one of two possible values: true or false, 1 or 0.
His mathematical system became known as Boolean algebra.
All arithmetic operations performed with Boolean quantities have but one of two
possible outcomes: either 1 or 0. There is no such thing as "2" or "-1" or "1/2" in
the Boolean world. It is a world in which all other possibilities are invalid by fiat.
As one might guess, this is not the kind of math you want to use when balancing a
checkbook or calculating current through a resistor. However, Claude Shannon of
MIT fame recognized how Boolean algebra could be applied to on-and-off
circuits, where all signals are characterized as either "high" (1) or "low" (0).
Theoretical work to use in a way Boole never could have imagined, giving us a
powerful mathematical tool for designing and analyzing digital circuits.
1
a.
In this section, you will find a lot of similarities between Boolean algebra and
"normal" algebra, the kind of algebra involving so-called real numbers. Just bear
in mind that the system of numbers defining Boolean algebra is severely limited in
terms of scope, and that there can only be one of two possible values for any
Boolean variable: 1 or 0. Consequently, the "Laws" of Boolean algebra often
differ from the "Laws" of real-number algebra, making possible such statements
as 1 + 1 = 1, which would normally be considered absurd. Once you comprehend
the premise of all quantities in Boolean algebra being limited to the two
possibilities of 1 and 0, and the general philosophical principle of Laws depending
on quantitative definitions, the "nonsense" of Boolean algebra disappears.
2. Digital Logic Gates:
A logic gate is a general purpose electronic device used to construct logic circuits.
All logic gates have inputs and outputs. The state of the output is set by the input
states using different rules depending on the type of gate. The different types of
gates have different shaped circuit symbols.
Logic gates the basic components in digital electronics. They are used to create
digital circuits and even complex integrated circuits. For examples, complex
integrated circuits may bring already a complete circuit ready to be used microprocessors and microcontrollers are the best examples-but inside them they
were projected using several logic gates.
A gate is a special type of amplifier circuit designed to accept and generate
voltage signals corresponding to binary 1's and 0's. As such, gates are not
intended to be used for amplifying analog signals (voltage signals between 0 and
full voltage). Used together, multiple gates may be applied to the task of binary
number storage (memory circuits) or manipulation (computing circuits), each
gate's output representing one bit of a multi-bit binary number.
Positive and Negative logic:
We know that, in binary logic, two voltage levels represent the two binary digits,
1 or 0. If the higher of the two voltages represents a 1 and lower voltage represent
a 0, the system is called a positive logic system. On the other hand, if the lower
voltage represents a 1 and the higher voltage represents a 0, we have a negative
logic system.
On a circuit diagram it must be accompanied by a statement asserting that
the positive logic convention or negative logic convention is being used (high
voltage level = 1 or high voltage level = 0, respectively). The wedge is used in
circuit diagrams to directly indicate an active-low (high voltage level = 0) input or
output without requiring a uniform convention throughout the circuit diagram.
This is called Direct Polarity Indication. Both the bubble and the wedge can be
used on distinctive-shape and rectangular-shape symbols on circuit diagrams,
depending on the logic convention used. On pure logic diagrams, only the
bubble is meaningful.
As an example, assume that we have positive 5V and 0V as logic-level voltages.
Let us designate +5V as high level and 0 as low level; then positive and negative
logic can be defined as:
Positive logic:
high = 1
Low = 0
Negative logic:
High = 0
Low = 1
Both positive and negative logic are used in digital systems, but positive logic is
more common.
2
b.
Basic Logic gates

Gates are circuits that are used to combine digital logic levels (ones and zeros)
in specific ways. The basic gates are the AND, OR and Inverter, generally
pronounced as AOI.
Type
Distinctive
shape
Rectangular
shape
Boolean
algebra
Logic Statement
AND
Y=A.B
High output
when both inputs
are high.
OR
Y=A+B
Low output
when both inputs
are low.
NOT
Output is the
complement of
input.
Fig. 1 Basic Logic gates
2.1
AND gate:
Definition:
The AND gate is a logic device that has two or more inputs but one output.
Symbols:
There are three symbols for AND gates: the American (ANSI or 'military') symbol and
the IEC ('European' or 'rectangular') symbol, as well as the deprecated DIN symbol.
MIL/ANSI Symbol
IEC Symbol
DIN Symbol
Fig. 2 different symbol of AND gate

The schematic symbol for two inputs AND gate is shown above. The gate is
produces logic 1 at its output only when all the inputs are high. A logic low is
produces when one or more of the inputs are low.
Truth table:
Table 1 is the truth table of all possible combination of 2 input AND gate.
Inputs
Output
B
A
Y= A.B
0
0
0
0
1
0
1
0
0
1
1
1
Table 1. 2- input AND gate truth table
Logic families:
(a)
(b)
Fig. 3 (a) Resistor Transistor Logic (RTL) circuit and (b) Diode Logic of
input AND gate
2-
Electrical Equivalent circuit:
(a)
(b)
Fig. 4 (a) Electrical analogy (b) easy way drawing of AND gate
The simplified AND gate shown above has two inputs, switch A and switch B.
The bulb Q will only light if both switches are closed. This will allow current to
flow through the bulb, illuminating the filament.
An easy way to remember how an AND gate works is thinking about a circuit to
turn a light bulb on. If both switches are on then the bulb will light up, if any
switch is off then the bulb won't light.
Fig. 5 Electronic Circuit of AND gate

4
This is an AND gate circuit and it can be made quite easily. The example shown
is built from a modular electronics kit. Both switches A and B must be pressed
together for the bulb to light. If you construct this circuit, you may need to alter
the value of the resistors. This will depend on the type of transistors used and
whether to bulb or an LED is used.
Relay Equivalent:
(a)
(b)
Fig. 6 (a) Relay Equivalence of AND (b) AND and NAND gates.
5
In the AND gate circuit, both relays, in series with their own switch buttons are
placed (in parallel) independently from each other, yet connected to the same
source. The lamp (output) circuit is also connected to the same source.
However, the lamp is connected in series with NORMALY OPEN contact of
relay A, then in series with NORMALY open contacts of relay B. So the lamp
will light up only if both contacts will be closed. And it will happen only if
both relays be activated.
Domestic gate concept:
Parallel connected gates in your home. You can enter the home when all gates are
open.
Boolean Equation: Y= A.B
Timing Diagram: Timing diagrams are yet another method of showing the function of
a gate or circuit. If the function of the gate is known, you should be able to draw the
output waveform for a gate given the input waveforms.
Fig. 7 Timing Diagrams for AND gate

Integrated Circuits (ICs):
Figure 8 show the pin outs diagrams and front inside view of IC 7408 (quad 2input AND gate).
(a)
(b)
Fig. 8 (a) pin out diagram (b) front view of 7408

2.
6
Some of the available AND gate ICs are listed in Table 2.

Number
Family
Subfamily
Description
7408
TTL
Standard
Quad 2-input AND
74ACT08 CMOS
Advanced CMOS, TTL Quad 2-input AND
Compatible
74HCT11 CMOS
High-Speed CMOS, TTL Triple 3-input AND
Compatible
4081
CMOS
Standard
Quad 2-input AND
4082
CMOS
Standard
Dual 4-input AND
Table 2.some of the available AND gate ICs
2.4.2 OR gate (Inclusive OR):
Definition:
The OR gate is a circuits that produces high output when any of its inputs are
high.
Symbols:
Fig. 9 shows conventional, IEC and the IEEE symbols for the two-input OR gate
with inputs A and B and output Y and table 3 summarized the operation of the OR
gate using truth table. All possible input combinations are listed by counting in
binary from 00 to 11.
(a)
(b)
Fig. 9. OR gate(a) MIL/ANSI Symbol (b) IEC Symbol

Truth table:
Input
Output
B
A
Y= A+B
0
0
0
0
1
1
1
0
1
1
1
1
Table 3. two- input OR gate truth table
Logic families:
(a)
(b)
Fig. 10. (a) Resistor Transistor Logic (RTL) circuit and (b) Diode Logic of two input
OR gate
7
10
(a)
(b)
Fig. 11. (a) Electrical analogy (b) easy drawing of (a) OR gate
The simplified OR gate shown above has two inputs, switch A and switch B. The
bulb Q will light if either switch A or B are closed. This will allow current to flow
through the bulb, illuminating the filament.
An easy way to remember how an OR gate works is thinking about a circuit to
turn a light bulb on. If one or more switches are on then the bulb will light up, if
both switch are off then the bulb won't light.
Fig. 12. Electronic Circuit of OR gate

This is an OR gate circuit. Either switch A or B must be pressed for the bulb to
light. The switches do not have to be pressed together.
Relay Equivalent: In the OR gate circuit, both relays, in series with their own
switch buttons are placed (in parallel) independently from each other, yet
connected to the same source. The lamp (output) circuit is also connected to the
same source.
However, the lamp is connected in series with NORMALY OPEN contact of
relay A, parallel to the contacts of relay A the normally open contact of relay B is
placed.
So the lamp will light up only if either contact of relay A or the contact of relay B
will be closed. And it will happen if any one of relays be activated.
8
Fig.13. (a) Relay Equivalence of OR

Domestic gate concept: series connected of domestic gates.
Boolean Equation: Y=A+B
Figure 2.13 show the pin outs diagrams and front inside view of IC 7432 (quad 2input OR gate).
(a)
(b)
Fig. 14. (a) pin out diagram (b) front inner view of IC 7432
A variety of forms of OR gates are available in TTL and CMOS. In the TTL
family, the 7432 is a quad (meaning four gates) two-input TTL OR gate IC. The
four are independent. Each can be in a different part of the circuit without
feedback. Power is supplied to the IC through a VCC (+5V) and ground
connection. The 4072 is a dual (meaning two gates) four input CMOS OR gate
IC. The pin out for 7432 and 4072 is shown in Fig. 14.
Some of the available OR gate ICs are listed in following Table
Number
Family
Subfamily
Description
7432
TTL
Standard
Quad 2-input OR
74LS32
TTL
Low-Power
Quad 2-input OR
Schottky
74HC32
CMOS
High-Speed CMOS Quad 2-input OR
4071
CMOS
Standard
Quad 2-input OR
4072
CMOS
Standard
Dual 4-input OR
Table 4. some of the available OR gate ICs
9
2.4.3 Inverter:
Definition: The inverter is a singleinput and single output gate whose output is
the complement of the input. It inverts the signal on the input. Fig.15 (a) shows
conventional and IEC (International Electrochemical Commission) and the IEEE
(Institute of Electrical and Electronics Engineers) symbols for the inverter and
Table 5, summarized the operation in a truth table by listing all possible input and
the corresponding output. In electronics a NOT gate is more commonly called an
inverter. The circle on the symbol is called a bubble, and is used in logic diagrams
to indicate a logic negation between the external logic state and the internal logic
state (1 to 0 or vice versa).
Symbols: There are two symbols for NOT gates: the American (ANSI or 'military')
symbol and the IEC ('European'
deprecated DIN symbol.
MIL/ANSI Symbol
or
'rectangular')
symbol,
as
well
as
the
IEC Symbol
Fig. 15. different logic symbol of NOT gate

The schematic symbol for NOT gate is shown above. The gate is produces
complement output of the input.
Truth table:
Input
output
0
1
1
0
Table 5.NOT gate truth table
Logic families:
Fig. 16. (a) Transistor Logic circuit of NOT gate
10
Fig. 17. Electrical analogy of NOT gate

Switch A is connected parallel to the bulb. When switch is on, switch short the
circuit, current divided into two parts according the current dividing rules, bulb
does not glow. When off position the switch is in open circuit, all current passes
through the bulb, and glow. .
Relay Equivalent:
Relay NOT gate is shown in the Fig.18.
Fig. 18. Relay NOT gate

Domestic gate concept:
Special type of switch controlled gate, when you switch on the gate it will be
closed, you cannot enter the home, if it closed you enter the home.
Boolean Equation:
YA
Inverters are available in 14-pin DIP package in both TTL and CMOS. In the TTL
family, the 7404 is a hex inverter. Hex signifies that six inverters are contained on
the same IC. Each is independent from the others and each can be used in a
different part of the circuit. The supply voltage, Vcc is +5V and is applied to pin
14 with pin 7 connected to ground. The pinouts of all 74XXX04ICs, regardless of
family or subfamily, are the same.
11
(a)
(b)
Fig. 19. (a) pin out diagram (b) front inner view of 7404/05/14
The original CMOS family was numbered 4xxx. For example, the 4069 is a hex
inverter. Most 4xxx ICs have a different pinout from their 74xxx counterparts.
The pinout of the 4069 happens to be same as the 7404. The power pin on the
4xxx series is labeled VDD instead of VCC; and the ground pin is labeled VSS.
VDD can range from +3 volt to +15 volt. Some of the available inverter ICs is
listed in following Table.
Number
7404
74LS04
74ALS04
Family
TTL
TTL
TTL
Subfamily
Standard
Low-Power Schottky
Advanced Low-Power
Schottky
74AC04
CMOS
Advanced CMOS
74HC04
CMOS
High-Speed CMOS
74HCT04
CMOS
High- Speed CMOS,
TTL Compatible
4069
CMOS
Standard
Table 6. Some of the available NOT gate ICs
Description
Hex Inverter
Hex Inverter
Hex Inverter
Hex Inverter
Hex Inverter
Hex Inverter
Hex Inverter
2.5 Other Logic gates:

Type
Distinctive
shape
Rectangular
shape
Boolean algebra
between A & B
XOR
XNOR
Logic
Low output
when both
inputs are
same
High output
when both
inputs are
same
Fig. 20. Other Logic gates
12
2.5.1 Exclusive-OR gates (XOR):

Definition:
An exclusive-OR (Ex-OR) gate is not one of the basic gates, but is constructed
from a combination of the basic gates. The Ex-OR is a two input gate that
produces a 1 on its output when its inputs are different and a 0 if they are the
same.
Symbol: The symbol for an exclusive-OR is shown in Fig. 20. The three previous
gates are fairly direct variations on basic functions: NOT, AND and OR. The
Exclusive-OR (XOR) gate is something quite different. Exclusive-OR gates
output a "high" (1) logic level if the inputs are at different logic levels, either 0
and 1 or 1 and 0. Conversely, they output a "low" (0) logic level if the inputs are
at the same logic levels. The Exclusive-OR (sometimes called XOR) gate has
both a symbol and a truth table pattern that is unique, refer to figure 8.
(a)
(b)
(c)
Fig. 21. different representation of XOR gate

One element conspicuously missing from the set of Boolean operations is that
of Exclusive-OR. Whereas the OR function is equivalent to Boolean addition,
the AND function to Boolean multiplication, and the NOT function (inverter) to
Boolean complementation, there is no direct Boolean equivalent for ExclusiveOR. This hasn't stopped people from developing a symbol to represent it,
though:
13
This symbol is seldom used in Boolean expressions because the identities, laws,
and rules of simplification involving addition, multiplication, and
complementation do not apply to it. However, there is a way to represent the
Exclusive-OR function in terms of OR and AND, as has been shown as: AB' +
A'B
Truth table:
The truth table for an exclusive-OR is shown in table
Input
XOR
gate
Logic families:
B
0
0
1
1
A
0
1
0
1
Output
Y A B
0
1
1
0
Table 7. 2 input
truth table
Fig. 22. (a) Diode Logic circuit XOR gate

Boolean Equation: As a Boolean equivalency, this rule may be helpful in
simplifying some Boolean expressions. Any expression following the AB' + A'B
form (two AND gates and an OR gate) may be replaced by a single Exclusive-OR
gate. Designing an Ex-OR gate, first we write a Boolean expression for the truth
table in Table 7. The output Y AB AB A B
The pinouts for a 7486 (quad two-input Ex-OR) is shown in Fig.23.
(a)
(b)
Fig. 23. (a) pin out diagram (b) front inner view of 7486
14
Following Table Shows the some Ex-OR gate are available in many forms in
TTL and CMOS.
Number
Family
Subfamily
Description
7486
TTL
Standard
Quad 2-input Ex-OR
74ACT86
CMOS
Advanced CMOS, TTL Quad 2-input Ex-OR
compatible
74ALST86 TTL
Advanced
Low-Power Quad 2-input Ex-OR
Schottky
4030
CMOS
Standard
Quad 2-input NAND
4070
CMOS
Standard
Dual 4-input NAND
Table 8. some of the available XOR gate ICs
2.5.2 Exclusive-NOR gates:
Definition:
The Exclusive-NOR Gate function or Ex-NOR for short, is a digital logic gate
that is the reverse or complementary form of the Exclusive-OR function we look
at in the previous section. It is a combination of the Exclusive-OR gate and
the NOT gate but has a truth table similar to the standard NOR gate in that it has
an output that is normally at logic level "1" and goes "LOW" to logic level "0"
when ANY of its inputs are at logic level "1". However, an output "1" is also
obtained if BOTH of its inputs are at logic level "1". For example, A = "1" and B
= "1" at the same time giving us the Boolean expression
of: Q = (A B) = A.B + A.B
An exclusive-NOR (Ex-NOR), sometimes called non exclusive-OR. Ex-NOR
gate is not one of the basic gates, but is constructed from a combination of the
basic gates. The Ex-NOR is a two input gate that produces a 1 on its output when
its inputs are same and a 0 if they are the different.
Symbol:
The symbol for an exclusive-NOR gate is shown in Fig, 24.
Fig. 24. two input XNOR gate
15
The Exclusive-NOR Gate function is achieved by combining standard gates

together to form more complex gate functions and an example of a 2input Exclusive-NOR gate is given below.
Then, the logic function implemented by a 2-input Ex-NOR gate is given as
"when both A AND B are the SAME" will give an output at Q. In general, an
Exclusive-NOR gate will give an output value of logic "1" ONLY when there are
an EVEN number of 1's on the inputs to the gate (the inverse of the Ex-ORgate)
except when all its inputs are "LOW". Then an Ex-NOR function with more than
two inputs is called an "even function" or modulo-2-sum (Mod-2-SUM), not
an Ex-NOR. This description can be expanded to apply to any number of
individual inputs as shown below for a 3-input Exclusive-NOR gate.
We said previously that the Ex-NOR function is a combination of different basic
logic gates Ex-OR and a NOT gate, and by using the 2-input truth table above, we
can expand the Ex-NOR function to: Q = A B = (A.B) + (A.B) which means
we can realize this new expression using the following individual gates.
In the next tutorial about Digital Logic Gates, we will look at the digital Tri-state
Buffer also called the non-inverting buffer as used in both TTL and CMOS logic
circuits as well as its Boolean algebra definition and truth table.
Truth table: The truth table for an exclusive-NOR
Input
Output
Y A B
0
0
1
1
0
1
0
1
0
1
1
0
Table 9. input XNOR gate truth table

Boolean Equation:
In other words, the output of an Exclusive-NOR gate ONLY goes "HIGH" when
its two input terminals, Aand B are at the "SAME" logic level which can be either
at a logic level "1" or at a logic level "0". Then this type of gate gives and output
"1" when its inputs are "logically equal" or "equivalent" to each other, which is
why an Exclusive-NOR gate is sometimes called an Equivalence Gate. The
logic symbol for an Exclusive-NOR gate is simply an Exclusive-OR gate with a
circle or "inversion bubble", ( ) at its output to represent the NOT function.
Then the Logic Exclusive-NOR Gate is the reverse or "Complementary" form of
the Exclusive-OR gate. The Boolean equation for that Exclusive NOR is
Y AB AB A B . It can also be written as
Y A B =
Timing Diagram
16
Fig. 25. Timing Diagrams for XNOR gate

Commonly available Exclusive-NOR gate IC's include: TTL logic types
(74LS2660 and CMOS logic types (CD 4077) both are quad 2-input.ExNOR gates are used mainly in electronic circuits that perform arithmetic
operations and data checking such as Adders, Subtractors or Parity Checkers, etc.
As the Ex-NOR gate gives an output of logic level "1" whenever its two inputs
are equal it can be used to compare the magnitude of two binary digits or numbers
and so Ex-NOR gates are used in Digital Comparator circuits. Pin out diagram of
a 74266 Quad XNOR, DIP-format IC.
Figure 26 show the pin outs diagrams and front inside view of IC 74266 (quad 2input XNOR gate).
(a)
(b)
Fig. 26. (a) pin out diagram (b) front view of 74266 (quad 2-input Ex-NOR
Gate)
Number
Family
Subfamily
Description
74HCT266
CMOS
Hi Speed CMOS
Quad 2-input Ex-NOR
Table 10. some of the available NOR gate ICs
17
Application of XOR
1. Uses in addition
The XOR logic gate can be used as a one-bit adder that adds any two bits together
to output one bit. For example, if we add 1 plus 1 inbinary, we expect a two-bit
answer, 10 (i.e. 2 in decimal). Since the trailing sum bit in this output is achieved
with XOR, the precedingcarry bit is calculated with an AND gate. This is the
main principle in Half Adders and the combined AND-XOR circuit may be
chained together in order to add ever longer binary numbers.
Fig. 27. Half Adder logic diagram

Signal crossing
XOR gates can be used to cross two Boolean signals without requiring a via. The
crossover comprises three XOR gates, strategically positioned to cancel out the
effects of each other. A similar result can be achieved using eight NAND gates.
Note that this setup can only cross Boolean (digital) signals, and not analog
signals, so would be of limited use in an amplifier or other analog circuit.
Fig. 28. Crossover comprising three XOR gates

2.6 Universal gates
Type
Distinctive
shape
Rectangular
shape
Boolean algebra
between A & B
NAND
Logic
Low output
when both
inputs are
high
high output
when both
inputs are
low
NOR
Fig. 29. Universal Logic gates

2.6.1 The NAND gate:
Definition:
A variation on the idea of the AND gate is called the NAND gate. The word
"NAND" is a verbal contraction of the words NOT and AND. Essentially, a
18
NAND gate behaves the same as an AND gate with a NOT (inverter) gate
connected to the output terminal. The NAND gate is a circuit that produces a 0
on its output when all of its inputs are 1. NAND is the contraction of the words
NOT and AND.
Symbols:
To symbolize this output signal inversion, the NAND gate symbol has a bubble
on the output line. The truth table for a NAND gate is as one might expect,
exactly opposite as that of an AND gate.
Fig. 30 NAND gate

Truth table:
The truth table for an NAND gate
Input
B
0
0
1
1
A
0
1
0
1
Output
Y AB
0
0
0
1
Table 11. 2 input NAND gate truth table
Logic families:
(a)
(b)
Fig. 31. (a) Resistor Transistor Logic (RTL) circuit and (b) Schematic of
basic two-input DTL NAND gate Diode Transistor Logic of NAND gate
19

Serially connected switches are placed parallel to battery and bulb. When all
switches are in high position means short circuited the battery and bulb no output.
Relay Equivalent:
In the NAND gate circuit, both relays, in series with their own switch buttons are
placed (in parallel) independently from each other, yet connected to the same
source. The lamp (output) circuit is also connected to the same source.
However, the lamp is connected in series with NORMALY CLOSE contact of
relay A, parallel to the contacts of relay A the normally closed contact of relay B
is placed.
So the lamp will light up only if either contact of relay A or the contact of relay B
will be closed. And it will happen if either NONE or just ONE of relays be
activated. But not the both, when both normally closed contacts will be open.
Fig. 32. Relay Equivalence AND and NAND gate

Boolean Equation: Y AB
Timing Diagram:
Fig. 33. Timing diagram for NAND gate

20

The 7400 chip, containing four NANDs. The second line of smaller numbers
(7645) is a date code; this chip was manufactured in the 45th week of 1976. The
N suffix on the part number is a vendor-specific code indicating PDIP packaging.
Here Figure 34 show the pin outs diagrams and front inside view of IC 7400
(quad 2-input NAND gate).
Fig. 34. pin out diagram and front view of 7400

The NAND gate is available
following Table
Number
Family
7400
TTL
7430
TTL
74LS20
TTL
74ALST10
TTL
in many forms in TTL and CMOS, as shown in
Subfamily
Description
Standard
Quad 2-input NAND
Standard
8-input NAND
Low-Power Schottky
Dual 4-input NAND
Advanced Low-Power Triple 3-input NAND
Schottky
74ALST133
TTL
Advanced Low-Power 13-input NAND
Schottky
74HTC11
CMOS
High-Speed CMOS
Quad 2-input NAND
4011
CMOS
Standard
Quad 2-input NAND
4012
CMOS
Standard
Dual 4-input NAND
4023
CMOS
Standard
Triple 3-input NAND
Table 12. some of the available NAND gate ICs
2.6.2 NOR gates:
Definition:
The NOR gate is a circuit that produces a 0 on its output when one or more of its
inputs are 1. NOR is the contraction of the words NOT and OR. Its symbol is
the OR symbol with an inverted (conventional, and IEC/IEEE), with two inputs A
and B and output Y, is shown in Fig.35.
Symbols:
Fig.35. NOR gate symbol

21
Truth table:
Input
B
0
0
1
1
A
0
1
0
1
Output
Y A B
1
0
0
0
Table 13. 2 input NOR gate truth table

Logic families:
Fig. 36. Transistor Transistor Logic (TTL) circuitNOR gate

Boolean Equation:
Y A B
Figure 37 show the pin outs diagrams and front inside view of IC 7402 (quad 2input NOR gate).
(a)
(b)
Fig. 37. (a) pin out diagram (b) front inner view of 7402
22
The NOR gate is available in many forms in TTL and CMOS, as shown in
following Table.
Number
7402
7425
74LVQ02
74ALS27
4001
4002
4025
2.7
Family
TTL
TTL
TTL
TTL
Subfamily
Description
Standard
Quad 2-input NOR
Standard
Dual 4-input NOR
Low-Voltage Quiet
Quad 2-input NOR
Advanced
Low-Power Triple 3-input NAND
Schottky
CMOS
Standard
Quad 2-input NOR
CMOS
Standard
Dual 4-input NOR
CMOS
Standard
Triple 3-input NOR
Table 14. some of the available NOR gate ICs
Positive and Negative gates:

Consider the truth table for positive logic OR gate as shown in table 15 the low
input means off state logically represents as 0 and high input is on state 1
represented in table 16. The table 17 which represents negative logic is the truth
table for OR gate.
inputs
Output
A
B
Y=A+B
LOW
LOW
LOW
LOW
HIGH HIGH
HIGH
LOW HIGH
HIGH HIGH HIGH
Table 15. Truth table of positive OR gate
OR gate
inputs
output
output
A
B
Y
A
B
Y
1
1
1
0
0
0
1
0
0
0
1
1
0
1
0
1
0
1
0
0
0
1
1
1
Table 16. representation in positive logic
Table 17. representation in negative logic
Inputs
AND gate
Similarly table 18 and table 19 represents the positive and negative logic AND
gate respectively.
23
And gate
inputs
output
output
A
B
Y
A
B
Y
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
1
0
0
0
0
0
1
1
1
Table18. representation in positive logic
Table 19. representation in negative logic
Above tables show that positive logic OR gate system becomes an negative logic
AND gate systems and vice versa.
Inputs
Positive OR
Positive AND
Negative AND
Negative OR
In a similar ways, we can compare the equivalences between positive and negative
logic NOR and NAND gates:
Positive NOR
Positive NAND
2.8
Negative NAND
Negative NOR
Gate Universality:
2.8.1 NAND/NOR gate as a Universal gate:
A NAND gate is a combination of NOT and AND gate (i.e., AND gate followed
by inverter). Therefore, the output is NOT the AND of the inputs. Thus it has two
or more input signals but only one output signal. All input signals must be high to
get a low output.
The NAND gate is said to be a universal gate because any digital system can be
implement with it. The logic operation of NOT (inverter/complement), AND, OR,
Ex-OR, and Ex-NOR gates can be obtained with NAND gates only. NAND gate
is easier to realize and consume less power than the other gates.
The NOR operation is the dual of the NAND operation. Therefore, all procedures
and rules for NOR logic are the duals of the corresponding procedures and rules
developed for NAND logic. A NOR gate is a combination of NOT and OR gate
(i.e., OR gate followed by inverter). Therefore, the output is NOT the OR of the
inputs. Thus it has two or more input signals but only one output signal. All input
signals must be low to get a high output. The NOR gate is another universal gate
that can be used to implement any Boolean function. The implement of the NOT
(complement), AND, OR, NAND, Ex-OR, and Ex-NOR gates with NOR gate
only. NOR gate is easier to realize and consume less power than the other gates.
2.8.2 NAND/NOR as NOT (Inverter /Complement) operation:
The complement operation is obtained from a one input NAND gate that behaves
exactly like an inverterFig.2.1.1 shows a two-input NAND gate as an Inverter.
Suppose we apply the same signal to both inputs of a two-input NAND. The twoinputs to NAND gate are tied together, so that the gate works as inverter (NOT)
gate. Then either both inputs are 0 or both inputs are 1. If input is 0 the output
will be 1. If input is 1 the output will be 0. The output is always the
complement of the input.
24
The complement operation is obtained from a one input NOR gate that behaves
exactly like an inverter. If we apply the same signals of a two-input NOR gate,
then either both inputs are0 or both inputs are 1. In either case the output is
always the complement of the input. Fig.2.2.1 shows a two-input NOR gate as an
Inverter. An Inverter or logic NOT gate can also be made using
standard NAND and NOR gates by connecting together ALL their inputs to a
common input signal for example.
Fig. 38. NOT gate using NAND/NOR

2.8.3 NAND/NOR as buffer operation:
Being that it is quite easy to employ NAND and NOR gates to perform the inverter (NOT)
function, it stands to reason that two such stages of gates will result in a buffer function, where
the output is the same logical state as the input.
25
Fig. 39. Buffer gate using NAND/NOR

2.9.4 NAND/NOR as AND operation:
An AND operation requires two NAND gate. The first produces the NAND operation
and second inverts the logical sense of the signal. Fig.40 shows a two-input NAND gate
used as a two-input AND gate. The output of two-input AND gate is
(Y A.B AB , NAND NAND combinatio n} , therefore, the combination of two

NAND gates gives AND operation. The two inputs of first NAND gate are A and B, its
output is (Y ) A.B . The two inputs to the second NAND gate are tied together (NAND
as NOT) and the output of first A.B is fed to this common terminal. The second NAND
gate works as inverter and its output (Y AB AB), thus giving two-input AND
operation.
The AND operation is achieved through a NOR gate with additional inverters in each
input. . The output of two-input AND gate is ( Y AB AB A . B ). It implies that,
the combination of three NOR gates gives AND operation. In Fig. 40, the two-inputs of
each of the first two two - input NOR gates are tied together and fed by A and B as
shown. The outputs are Aand B . They are fed to as inputs to third two-input NOR gate.
The final output is AB thus giving two-input AND operation.
To make the AND function from NAND gates, all that is needed is an inverter (NOT)
stage on the output of a NAND gate. This extra inversion "cancels out" the first N in
NAND, leaving the AND function. It takes a little more work to wrestle the same
functionality out of NOR gates, but it can be done by inverting ("NOT") all of the inputs
to a NOR gate.
26
Fig. 40. AND gate using NAND/NOR

a.
NAND/NOR as an OR operation:
The OR operation is achieved through a NAND gate with additional inverters in each
input. Fig. 41 shows a two-input NAND gate used as a two-input OR gate operation. The
output of two-input OR gate is ( Y A B A B A . B ). It indicates, the combination
of three NAND gates gives two-input OR gate, when two input NAND gate are tied
together then NAND gates work as inverters giving outputs A and B. The output of third
NAND gate is A . B. As per De-Morgans theorem, this is equal to A B thus giving twoinput OR function.
An OR operation requires two NOR gate. Fig.42 shows a two-input NOR gates as a twoinput OR operation. The output of two-input OR gate is ( Y A. B A B ), therefore,
the combination of two two-inputs NOR gates gives OR operation. The two inputs of first
NOR gate are A and B, its output is (Y ) A. B . The two inputs to the second NOR gate
is tied together and the output of first A. B is fed to this common terminal. The second
NOR gate works as inverter and its output is A+B, thus giving two-input OR operation.
27
Fig. 41. OR gate using NAND/NOR

Inverting
the
output
of
a
NOR gate (with
another
NOR gate connected as an inverter) results in the OR function. The NAND gate, on the
other hand, requires inversion of all inputs to mimic the OR function, just as we needed
to invert all inputs of a NOR gate to obtain the AND function. Remember that inversion
of all inputs to a gate results in changing that gates essential function from AND to OR
(or vice versa), plus an inverted output. Thus, with all inputs inverted, a NAND behaves
as an OR, a NOR behaves as an AND, an AND behaves as a NOR, and an OR behaves
as a NAND. In Boolean algebra, this transformation is referred to as DeMorgan's
Theorem, covered in more detail in a later chapter of this book.
28
Fig. shows a two-input NAND gates as a two-input NOR gate The output of twoinput NOR gate is ( Y A B A . B ). It indicates, the combination of four two-input
NAND gates gives two-input NOR gate operation. In Fig.2.1.4, the two inputs of each of
the first two NAND gates are tied together and fed by A and B. The outputs are Aand B .
They are fed to as inputs to third NAND gate. The output is A+B, fed to as input to fourth
NAND gate. The final output is A B thus giving NOR operation.
It would be pointless to show you how to "construct" the NAND function using a NAND
gate, since there is nothing to do. To make a NOR gate perform the NAND function, we
must invert all inputs to the NOR gate as well as the NOR gate's output. For a two-input
gate, this requires three more NOR gates connected as inverters.
Fig. 42. NAND gate using NOR
a. NOR as an NAND operation:

29
The output of two-input NOR gate is ( Y A B A . B ). It indicates, the combination of

four two-input NAND gates gives two-input NOR gate operation. In Fig.43, the two
inputs of each of the first two NAND gates are tied together and fed by A and B. The
outputs are Aand B . They are fed to as inputs to third NAND gate. The output is A+B,
fed to as input to fourth NAND gate. The final output is A B thus giving NOR
operation.
Much the same as the procedure for making a NOR gate behave as a NAND, we must
invert all inputs and the output to make a NAND gate function as a NOR.
Fig. 43. NOR gate using NAND

Fig.43 shows a two-input NOR gates as a two-input NAND operation. The output of twoinput NAND gate is ( Y AB A B ). It implies that, the combination of four NOR
gates NAND operation. Fig.2.2.3 shows a NOR gates as a NAND. In Fig.2.2.4, the twoinputs of each of the first two NOR gates are tied together and fed by A and B as shown.
The outputs are Aand B . They are fed to as inputs to third NOR gate. The output is AB,
fed to as input to fourth NOR gate. The final output is AB thus giving NAND operation.
30
b. NAND as an Ex-OR operation:

The output of Ex-OR gate is ( Y AB AB ). There are two ways, from which we
can implement the Ex-OR gate. Fig.44 shows a logic diagram of Ex-OR gate using twoinput NAND gates. The comparisons between two logic diagrams are as follows.
One way: =
. + .
=
. .
.
Second way: = . + . + +
= ( + ) + ( + )
= (.
) + (.
)
= (.
).
(.
)
Minimum number NAND gate used in the second way method.
Fig. 44. EX-OR using only NAND

1. NOR as an Ex-OR operation:
Fig.45 shows a two-input NOR gates as Ex-OR operation. The output of Ex-OR
gate is ( Y AB AB ). There are two ways, from which we can implement the
Ex-OR gate. The comparisons between two logic diagrams are as follows.
One way: -
Second way:Y AB A B A A B B
Y AB AB
A( A B ) B (( A B )
( A B) ( A B)
( A B ).( A B )
( A B) ( A B)
Minimum number NAND gate used in the second way method.
Fig. 45. EX-OR using only NOR

31
2.
NAND as an Ex-NOR operation:
The output of Ex-NOR gate is ( Y AB AB AB AB ). It is the invert of ExOR gate. We can implement the Ex-NOR gate using minimum number of
NAND gates as shown in the following logic diagram.
. + . + + )
=
. + . = (
) + ()
=
( + ) + ( + ) = (
) . (
)
= (
One easier way of producing the Ex-NOR function from a single gate type is to
use NAND gates as shown below.
Fig. 46. EX-NOR using only NAND

2. NOR as an Ex-NOR operation:
Fig.2.2.6 shows a two-input NOR gates as Ex-NOR operation. The output of ExNOR gate is ( Y AB AB AB AB ). It is the invert of Ex-OR gate. We can
implement the Ex-NOR gate using minimum number of NOR gates as:
Y AB AB ( A B) ( A B) ( A B) ( A B)
Fig. 47. EX-NOR using only NOR

32
Data control enable/inhibit of gates.

One of the common uses of gates is to control or gate the flow of data from the
input to the output. In that mode of operation one input is used as the control and
the other presents the data to be passed to the output. If the data is allowed to pass
through, the gate is said to be enabled. If the data is not allowed to pass through,
the gate is said to be inhibited.
1. AND gate Enable/Inhibit:
Following table shows the truth table for AND gate as an Enable/Inhibit.
Inhibit
Enable
Input
Control
0
0
1
1
Data
0
1
0
1
Y
0
0
0
1
Output
Comments
Output locked at 0
Data passes through unaltered
Table20. truth table for AND gate as an Enable/Inhibit.

If the signal on the control input of an AND gate is 0 (top two lines of the truth
table in Table 20), the output of the gate is 0 regardless of the data present on the
data input. The data does not pass through the gate, and the gate is said to be
inhibited. The output is locked up in the 0 state.
If the signal on the control input is 1 (bottom top two lines of the truth table in
Table 20), then whatever is present on the data input appears on the output and the
gate is said to be enabled. The data passes through the gate.
2. NAND gate Enable/Inhibit:
Following table shows the truth table for NAND gate as an Enable/Inhibit.
Inhibit
Enable
Input
Control
0
0
1
1
Data
0
1
0
1
Y
1
1
1
0
Output
Comments
Output locked at 1
Data passes through inverted
Table21. truth table for NAND gate as an Enable/Inhibit.

If the signal on the control input of a NAND gate is 0 (top two lines of the truth
table in Table2.19), the signal on the data input is ignored and the output is
locked up in the 1 state. The gate is said to be inhibited even through the output
is 1.
Table2.19), the signal on the data input is passed through the gate but is inverted
in the process. The gate is said to be enabled. The inverted data passes through
the gate.
3. OR gate Enable/Inhibit:
Following table shows the truth table for OR gate as an Enable/Inhibit.
33
Input
Output
Control
Data
Y
Comments
Enable
0
0
0
Data passes through
0
1
1
Inhibit
1
0
1
Output
locked at 1
1
1
1
Table 22. truth table for OR gate as an Enable/Inhibit.
If the signal on the control input of an OR gate is 0 (top two lines of the truth
table in Table 22), the signal on the data input passes through to the output
and the gate is enabled.
Table 22), the signal on the data input is ignored and the output is locked up
in the 1 state. The gate is said to be inhibited.
NOR gate as Enable/Inhibit:
Following table shows the truth table for NOR gate as an Enable/Inhibit.
Input
Output
Control
Data
Y
Comments
Enable
0
0
1
Data passes through inverted
0
1
0
Inhibit
1
0
0
Output
locked at 0
1
1
0
Table23. truth table for NOR gate as an Enable/Inhibit.
If the signal on the control input of a NOR gate is 0 (top two lines of the truth
table in Table 23), whatever is present on the data input appears at the output
inverted. The gate is enabled.
Table 23), the output of the gate is 0 regardless of the data present at the data
input. The gate is said to be inhibited.
4. Ex-OR gate as Enable/Inhibit:
Following table shows the truth table for Ex-OR gate as an Enable/Inhibit.
Input
Output
Control
Data
Y
Comments
Data passes
Data passes
0
0
0
(buffer)
0
1
1
Data passes
Inverted
1
1
0
1
1
0
Data passes inverted

(NOT gate)
Table 24. truth table for Ex-OR gate as an Enable/Inhibit.

If the signal on the control input of Ex-OR gate is 0 (top two lines of the truth
table in Table 24), whatever is present on the data input appears at the output
inverted. The gate is enabled.
Table 24), the output of the gate is inverted input.
34
The expanding the inputs of gates.

1. Expanding an AND gate:
a. A three-input AND gate can be created from two two-input AND gates as
shown in Fig 48.The output is the same as if we had fed A, B, and C into a
three-input AND, Y=(A.B).C.=A.(B.C)
Fig. 48. Three input AND using two input AND

The basic logic gates found in integrated circuits have a limited small number of
inputs, usually two, three or four. In many applications there is a need for logic
gates with more inputs. A number of logic gates can be combined to form a logic
gate with more inputs. Figure 49 (b) shows how a 3-input AND gate can be
implemented using two 2-input AND gates. Figure 49(c) and 49(d) show how a 4input AND gate can be implemented using three 2-input AND gates. Figure 49(f)
shows how a 3-input OR gate can be implemented using two 2-input OR gates.
Figure 49(g) and 49(h) show how a 4-input OR gate can be implemented using
three 2-input OR gates
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
Fig. 49. Logic Gate Input Expansion

In many applications there are gates available with more inputs that the required
ones. The extra inputs must be connected in such a way not to change the function
of the logic gate. The unused inputs are usually connected directly to logic 1, a
logic 0, or to another input of the same gate. Figure 50 below shows how the
unused inputs of logic gates can be connected.
35
+5V
(a)
(b)
(c)
(d)
(f)
(g)
(h)
+5V
(e)
Fig. 50. Unused inputs of logic gates

Because the Boolean expression for the logic AND function is defined as (.),
which is a binary operation, AND gates can be cascaded together to form any
number of individual inputs. However, commercial available AND gate IC's are
only available in standard 2, 3, or 4-input packages. If additional inputs are
required, then standard AND gates will need to be cascaded together to obtain the
required input value, for example.
Fig. 51. Six input AND using two input AND

The Boolean Expression for this 6-input AND gate will therefore
be: Q = (A.B).(C.D).(E.F)
If the number of inputs required is an odd number of inputs any "unused" inputs
can be held HIGH by connecting them directly to the power supply using suitable
"Pull-up" resistors.
2. Expanding a NAND gate:
a. The output from a three-input NAND gate would be Y=.

. , can be created
from two two-input NAND gates as shown in the following expressions. The
output is the same as if we had fed A, B, and C into a three-input NAND as:
Y A.B.C ( A.B).C A.( B.C ) NAND NAND Combination

Similarly for the four input NAND gate:
36
b. A four-input NAND gate can be created from two two-input NAND gates as
shown in Fig.52. The output is the same as if we had fed A, B, C, and D into a
four-input NAND as:
Y A.B.C.D ( A.B).(CD) NAND NAND Combination
Fig.52. four input NAND using two input NAND gates
3. Expanding an OR gate:
a. A three-input OR gate can be created from two two-input OR gates as shown
in Fig.53. The output is the same as if we had fed A, B, and C into a threeinput AND, Y= (A+B) +C =A+ (B+C).
Fig. 53. Three input OR using two input OR gates
b. A four-input OR gate can be created from two two-input OR gates. The output
is the same as if we had fed A, B, C, and D into a four-input OR, Y= (A.B).
(C.D), similarly we can expand an OR with another OR.
The OR function can have any number of individual inputs. However,
commercial available OR gates are available in 2, 3, or 4 inputs types.
Additional inputs will require gates to be cascaded together for example.
Fig. 54. six input OR using two input OR gates

37
The Boolean Expression for this 6-input OR gate will therefore

be: Q = (A+B)+(C+D)+(E+F)
can be held LOW by connecting them directly to ground using suitable "Pulldown" resistors.
4. Expanding an NOR gate:
a. A three-input NOR gate can be created from two two-input NOR gates. The
output of three (A, B, and C) input NOR gate is:
Y A B C ( A. ) C A B C ) NOR NOR Combination

b. A four-input NOR gate can be created from two two-input NOR gates as
shown in Fig.2.58. The output of four input (A, B, C, and D) NOR gate is
Y A B C D ( A B) (C D) {NOR NOR Combination }

Similarly we can expand an NOR with another NOR.
As with the OR function, the NOR function can also have any number of
individual inputs and commercial available NOR Gate IC's are available in
standard 2, 3, or 4 input types. If additional inputs are required, then the
standard NOR gates can be cascaded together to provide more inputs for example.
Fig. 55. four input NOR using two input NOR gates
The Boolean Expression for this 4-input NOR gate will therefore
be: Q = A+B+C+D
can be held LOW by connecting them directly to ground using suitable "Pulldown" resistors.
The Logic NOR Gate function is sometimes known as the Pierce Function and
is denoted by a downwards arrow operator as shown, AB.
2.9
Boolean Postulates
2.2.1 Boolean Arithmetic
Let us begin our exploration of Boolean algebra by adding numbers together: The
first three sums make perfect sense to anyone familiar with elementary addition.
The last sum, though, is quite possibly responsible for more confusion than any
other single statement in digital electronics, because it seems to run contrary to
the basic principles of mathematics. Well, it does contradict principles of addition
for real numbers, but not for Boolean numbers. Remember that in the world of
Boolean algebra, there are only two possible values for any quantity and for any
arithmetic operation: 1 or 0. There is no such thing as "2" within the scope of
38
Boolean values. Since the sum "1 + 1" certainly isn't 0, it must be 1 by process of
elimination. It does not matter how many or few terms we add together, either.
Consider the following sums: Take a close look at the two-term sums in the first
set of equations. Does that pattern look familiar to you? It should! It is the same
pattern of 1's and 0's as seen in the truth table for an OR gate. In other words,
Boolean addition corresponds to the logical function of an "OR" gate, as shown in
figure 1 below.
Fig.2.55 Boolean addition and the OR gate

There is no such thing as subtraction in the realm of Boolean mathematics.
Subtraction implies the existence of negative numbers: 5 - 3 is the same thing as 5
+ (-3), and in Boolean algebra negative quantities are forbidden. There is no such
thing as division in Boolean mathematics, either, since division is really nothing
more than compounded subtraction, in the same way that multiplication is
compounded addition. Multiplication is valid in Boolean algebra, and thankfully
it is the same as in real-number algebra: anything multiplied by 0 is 0, and
anything multiplied by 1 remains unchanged: This set of equations should also
look familiar to you: it is the same pattern found in the truth table for an AND
gate. In other words, Boolean multiplication corresponds to the logical function of
an "AND" gate. Like "normal" algebra, Boolean algebra uses alphabetical letters
to denote variables. Unlike "normal" algebra, though, Boolean variables are
always UPPERCASE letters, never lower-case. Because they are allowed to
possess only one of two possible values, either 1 or 0, each and every variable has
a complement: the opposite of its value. For example, if variable "A" has a value
of 0, then the complement of A has a value of 1. Boolean notation uses a bar
above the variable character to denote complementation, like this. In written form,
the complement of "A" denoted as "A-not" or "A-bar". Sometimes a "prime"
symbol is used to represent complementation (A). Boolean complementation
finds equivalency in the form of the NOT gate. The basic definition of Boolean
quantities has led to the simple rules of addition and multiplication, and has
excluded both subtraction and division as valid arithmetic operations. We have
symbols for denoting Boolean variables, and their complements. In the next
section we will proceed to develop Boolean identities.
2.2.2 Boolean Algebraic Identities
Let us begin our exploration of Boolean algebra by adding numbers together:
0+
0+
1+
1+
0=
1=
0=
1=
0
1
1
1
39
Fig. 56. OR operation

There is no such thing as subtraction in the realm of Boolean mathematics.
Subtraction implies the existence of negative numbers: 5 - 3 is the same thing as
5 + (-3), and in Boolean algebra negative quantities are forbidden. There is no
such thing as division in Boolean mathematics, either, since division is really
nothing more than compounded subtraction, in the same way that multiplication
is compounded addition.
Multiplication is valid in Boolean algebra, and thankfully it is the same as in
real-number algebra: anything multiplied by 0 is 0, and anything multiplied by 1
remains unchanged:
0x
0x
1x
1x
0=
1=
0=
1=
0
0
0
1
This set of equations should also look familiar to you: it is the same pattern
found in the truth table for an AND gate. In other words, Boolean multiplication
corresponds to the logical function of an "AND" gate, as well as to series switch
contacts:
40
Fig. 57. AND operation

Like "normal" algebra, Boolean algebra uses alphabetical letters to denote
variables. Unlike "normal" algebra, though, Boolean variables are always
CAPITAL letters, never lower-case. Because they are allowed to possess only
one of two possible values, either 1 or 0, each and every variable has
a complement: the opposite of its value. For example, if variable "A" has a value
of 0, then the complement of A has a value of 1. Boolean notation uses a bar
above the variable character to denote complementation, like this:
If : A 0 ; Then A 1
If : A 1 ; Then A 0
In written form, the complement of "A" denoted as "A-not" or "A-bar".
Sometimes a "prime" symbol is used to represent complementation. For
example, A' would be the complement of A, much the same as using a prime
symbol to denote differentiation in calculus rather than the fractional notation
d/dt. Usually, though, the "bar" symbol finds more widespread use than the
"prime" symbol, for reasons that will become more apparent later in this
chapter.
Boolean complementation finds equivalency in the form of the NOT gate, or a
normally-closed switch or relay contact:
41
Fig. 58. NOT operation

The basic definition of Boolean quantities has led to the simple rules of addition
and multiplication, and has excluded both subtraction and division as valid
arithmetic operations. In the next section we will proceed to develop Boolean
identities.
2.2.3 Boolean Algebraic Identities with variable:
In mathematics, an identity is a statement true for all possible values of its
variable or variables. The algebraic identity of x + 0 = x tells us that anything
(x) added to zero equals the original "anything," no matter what value that
"anything" (x) may be. Like ordinary algebra, Boolean algebra has its own
unique identities based on the bivalent states of Boolean variables. The first
Boolean identity is that the sum of anything and zero is the same as the original
"anything." This identity is no different from its real-number algebraic
equivalent:
Fig.59. OR operation
No matter what the value of A, the output will always be the same: when A=1,
the output will also be 1; when A=0, the output will also be 0.The next identity
is most definitely different from any seen in normal algebra. Here we discover
that the sum of anything and one is one:

No matter what the value of A, the sum of A and 1 will always be 1. In a sense,
the "1" signal overrides the effect of A on the logic circuit, leaving the output
42
fixed at a logic level of 1. Next, we examine the effect of adding A and A

together, which is the same as connecting both inputs of an OR gate to each
other and activating them with the same signal:

In real-number algebra, the sum of two identical variables is twice the original
variable's value (x + x = 2x), but remember that there is no concept of "2" in the
world of Boolean math, only 1 and 0, so we cannot say that A + A = 2A. Thus,
when we add a Boolean quantity to itself, the sum is equal to the original
quantity: 0 + 0 = 0, and 1 + 1 = 1.
Introducing the uniquely Boolean concept of complementation into an additive
identity, we find an interesting effect. Since there must be one "1" value
between any variable and its complement, and since the sum of any Boolean
quantity and 1 is 1, the sum of a variable and its complement must be 1:

Just as there are four Boolean additive identities (A+0, A+1, A+A, and A+A'),
so there are also four multiplicative identities: Ax0, Ax1, AxA, and AxA'. Of
these, the first two are no different from their equivalent expressions in regular
algebra:
43

The third multiplicative identity expresses the result of a Boolean quantity
multiplied by itself. In normal algebra, the product of a variable and itself is
the square of that variable (3 x 3 = 32 = 9). However, the concept of "square"
implies a quantity of 2, which has no meaning in Boolean algebra, so we cannot
say that A x A = A2. Instead, we find that the product of a Boolean quantity and
itself is the original quantity, since 0 x 0 = 0 and 1 x 1 = 1:

The fourth multiplicative identity has no equivalent in regular algebra because it
uses the complement of a variable, a concept unique to Boolean mathematics.
Since there must be one "0" value between any variable and its complement,
and since the product of any Boolean quantity and 0 is 0, the product of a
variable and its complement must be 0:

To summarize, then, we have four basic Boolean identities for addition and four
for multiplication:
44
Fig. 66. Double compliment operation
In mathematics, an identity is a statement true for all possible values of its

variable or variables. The algebraic identity of x + 0 = x tells us that anything (x)
added to zero equals the original "anything," no matter what value that "anything"
(x) may be. Like ordinary algebra, Boolean algebra has its own unique identities
based on the bivalent states of Boolean variables. I just list the identities here, for
detailed descriptions refer to. If A is a Boolean variable, figure 2 below shows
the basic Boolean algebraic identities.
2.3 Boolean Algebra Symbol
Named after its inventor, George Boole (1954), Boolean algebra defines
constants, variables and functions to describe binary systems .it then describes a
number of theorems that can be used to manipulate logic expressions. Boolean
operators are the codes for the basic logic gates.
Boolean constants consist of 0 and 1. Boolean variables are quantities that can
take different values at different times. They may represent input, output or
intermediate signals and are given names consisting of alphabetic characters such
as A, B,C,X or Y. Boolean variables may only take the values 0 or 1.Following
are the commonly used Boolean laws.
a. Commutative law:
It states that the elements of a function can be arranged in any sequence provided
the connective is the same. Commutative law can also be stated as:the order in
which terms are ANDed or ORed together is unimportant.Therefore, the OR
operation is commutative.
(a) + = +
ORing-the two inputs to OR gate have been interchanged. The output is the same.
45
Fig. 67.Logic Diagram of Commutative Property of addition

Another type of mathematical identity, called a "property" or a "law," describes
how differing variables relate to each other in a system of numbers. One of these
properties is known as the commutative property, and it applies equally to
addition and multiplication. In essence, the commutative property tells us we can
reverse the order of variables that are either added together or multiplied together
without changing the truth of the expression:
The AND operation is also commutative.
A.B B. A
ANDing- the two inputs to AND gate has been interchanged. The output is the
same.
Fig. 68. Logic Diagram of Commutative property of multiplication

Truth table for equation given in fig.68 and is given in fig 25.
S.No.
0
1
2
3
Inputs
A
0
0
1
1
B
0
1
0
1
Commutative (ORing)
Commutative (ANDing)
A+B
B+A
A.B
B.A
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
Table 25. truth table for commutative laws
b. Distributive law:
The distributive laws allow the factoring or multiplying of expressions. Two
distributive laws will be considered.
A + (B. C) = (A + B). ( A + C )
46
Figure 2.72 illustrates the distributive law, the AND gate gives an output B.C.
This signal when fed to OR gate along with input A gives the output A + (B. C).In
the circuit on right hand side the two OR gates give the output (A + B) and ( A +
C ) respectively. The AND gate gives the output (A + B). (A + C).
Boolean Algebraic Properties
Another type of mathematical identity, called a "property" or a "law," describes
how differing variables relate to each other in a system of numbers. Assuming A
and B are Boolean numbers; figure 2 lists the Boolean algebraic properties.
Boolean Rules for Simplification

Boolean algebra finds its most practical use in the simplification of logic circuits.
If we apply certain algebraic rules to a Boolean equation resulting from a truth
table, we will get a simpler equation. The simplified equation may be translated
into circuit form for a logic circuit performing the same function with fewer
components. If equivalent function may be achieved with fewer components, the
result will be increased reliability and decreased cost of manufacture. A few of
the Boolean rules for simplification are shown below.
Truth table for the above mention equations
S.No.
0
1
2
3
4
5
6
7
Truth table for distributive law

Inputs
Distributive law
A
B
C
B.C A+B.C
A+B
A+C
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
Table 26. truth table for distributive law
(A+B).(A+C)
0
0
0
1
1
1
1
1
A. (B + C) = A .B + A. C
Figure 69 illustrates the distributive law, the OR gate gives an output B + C.
This is fed as input to AND gate along with input A. On the right hand side the
47
two AND gates give the output (A. B) and (A. C) respectively. The OR gate gives
the output (A. B) + (A. C).
Fig. 69. Logic Diagram of Distributive Property

c. Associative law:
This law merely states that in any Boolean function containing elements (A, B, C
etc) separated by the same connective, it does not matter if some of the elements
are considered as a group.
(a) + + = + ( + ) = ( + ) +
Fig.70 shows the associative law for ORing. The inputs to OR gates have been
grouped in two different ways but the output is the same, i.e. y = A+B+C.
Along with the commutative properties of addition and multiplication, we have
the associative property, again applying equally well to addition and
multiplication. This property tells us we can associate groups of added or
multiplied variables together with parentheses without altering the truth of the
equations.
Fig. 70. Logic Diagram of Associative property of addition
S.No.
0
1
2
3
4
Inputs
A
0
0
0
0
1
B
0
0
1
1
0
Truth table for above mention equation

Associative
C
B+C
A+B
A+(B+C)
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
0
0
1
1
(A+B)+C
0
1
1
1
1
48
5
6
7
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 27. truth table for associative law using OR.
1
1
1
(b) . . = . (. ) = (. ).
Fig 71 shows the associative law for ANDing. The inputs to AND gates have
been grouped in two different ways without affecting the output. In each case
the output is y = A.B.C.
Fig. 71. Logic Diagram of Associative property of multiplication

Associative
B
C
B.C
A.B
A.(B.C)
(A.B)C
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
1
1
1
1
1
1
Table 28. truth table for associative law using AND.
S.No.
Inputs
0
1
2
3
4
5
6
7
A
0
0
0
0
1
1
1
1
To summarize, here are the three basic properties: commutative, associative, and
distributive.
d. Absorption law:
This law is extremely important for the elimination of redundant function in a
system.
(a) ( + ) =
Fig.2.78 shows the law of absorption. The output is logic 0 when A is 0 and logic
1 when A is 1, irrespective of the state of B.
49
Fig. 72. Logic Diagram of absorption law

S.No.
0
1
2
3
4
5
6
7
Inputs
Output
B
C
A+B
A
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
Table 29. truth table for absorption law
A(A+B)
0
0
0
0
1
1
1
1
(b) + =
Fig.2.79 shows another law of absorption. The output is logic 0 when A is 0
and logic 1 when A is 1, irrespective of the state of B.
Boolean rules for simplification
Boolean algebra finds its most practical use in the simplification of logic
circuits. If we translate a logic circuit's function into symbolic (Boolean)
form, and apply certain algebraic rules to the resulting equation to reduce the
number of terms and/or arithmetic operations, the simplified equation may be
translated back into circuit form for a logic circuit performing the same
function with fewer components. If equivalent function may be achieved
with fewer components, the result will be increased reliability and decreased
cost of manufacture.
To this end, there are several rules of Boolean algebra presented in this
section for use in reducing expressions to their simplest forms. The identities
and properties already reviewed in this chapter are very useful in Boolean
simplification, and for the most part bear similarity to many identities and
properties of "normal" algebra. However, the rules shown in this section are
all unique to Boolean mathematics.
This rule may be proven symbolically by factoring an "A" out of the two
terms, then applying the rules of A + 1 = 1 and 1A = A to achieve the final
result:
50
Fig.73. Absorption law in Boolean algebra

S.No.
0
1
2
3
4
5
6
7
Inputs
A
0
0
0
0
1
1
1
1
Output
B
C
AB
A+(AB)
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
Table 30. truth table for absorption law
Please note how the rule A + 1 = 1 was used to reduce the (B + 1) term to 1.
When a rule like "A + 1 = 1" is expressed using the letter "A", it doesn't
mean it only applies to expressions containing "A". What the "A" stands for
in a rule like A + 1 = 1 is any Boolean variable or collection of variables.
This is perhaps the most difficult concept for new students to master in
Boolean simplification: applying standardized identities, properties, and rules
to expressions not in standard form.
For instance, the Boolean expression ABC + 1 also reduces to 1 by means of
the "A + 1 = 1" identity. In this case, we recognize that the "A" term in the
identity's standard form can represent the entire "ABC" term in the original
expression.
The next rule looks similar to the first one shown in this section, but is
actually quite different and requires a more clever proof:
Fig. 74. Absorption law

51
Note how the last rule (A + AB = A) is used to "un-simplify" the first "A"
term in the expression, changing the "A" into an "A + AB". While this may
seem like a backward step, it certainly helped to reduce the expression to
something simpler! Sometimes in mathematics we must take "backward"
steps to achieve the most elegant solution. Knowing when to take such a step
and when not to is part of the art-form of algebra, just as a victory in a game
of chess almost always requires calculated sacrifices.
Another rule involves the simplification of a product-of-sums expression:
Fig. 75. Absorption law

And, the corresponding proof:
52
To summarize, here are the three new rules of Boolean simplification

expounded in this section:
Following table summarizes the operation of AND, NAND, OR, NOR, XOR, and
XNOR.
Gates
AND
Commutative
Yes A.B B.A
NAND
Yes
Associative
Yes
( AB) ( BA)
( A.B)C A( BC )
Distributive
Yes
Yes
Not
( A.B).C )
Yes
Yes
OR
Yes
A B B A
Yes
( A.( B.C )
( A. B ) C
A (B C)
NOR
Yes
( A B) ( B A)
Not
( A B) C )
XOR
Yes
A B B A
Yes
( A .( B C )
A (B C)
( A B) C
XNOR
Yes
A B B A
Yes
A (B C)
( A B) C
A( B C )
AB AC
A( B C )
AB AC
A. ( BC )
( A B ).( A C )
A. ( BC )
( A B).( A C )
Not
Not
A (B C)
( A B) ( A C )
A (B C)
( A B) ( A C )
Table 31. truth table forBooleans law

e. Idempotent law:
This law states that if a variable is ANDed or ORed with itself any number of
times, the result will always be the original variable.
(a) = . . . .
Fig. 2.83 shows the law of idempotent for ANDing. The output is variable
itself A whatsoever, the value of A.
Fig. 76. Idempotent operation using AND

Inputs
Output
A
A
A
A.A.A
0
0
0
0
1
1
1
1
Table 32. truth table for idempotent law using AND
(b) = + + + .
Fig 2.84 shows another law of idempotent for ORing. The output is
variable itself A whatsoever, the value of A.
53
Fig. 77. idempotent law operation using OR

Inputs
A
0
1
Output
A
A
A+A+A
0
0
0
1
1
1
Table 33. truth table for idempotent law using OR
f. Complementation law:
This law states that if a function consists of a variable and its inverse, then the
function is a constant.
(a) . = 0
Since an AND gate requires both inputs to be logic 1 for a logic 1 output, .
is always logic 0, since A and can never be logic 1 simultaneously. This is
shown in Fig.3.2.11
Fig.78. complementation operation using AND

Fig.3.2.11 Complementation law in Boolean algebra
Truth table for equation 3.2.5 and is given in table 3.2.2
Table 3.2.10
Inputs
Output
.
0
1
0
1
0
0
Table 34. truth table for complementation using AND
(b) + = 1
..(3.2.5)
Since an OR gate requires only one input to be logic 1 for logic 1 output,
either must be 1 at any time, so the result of A+A is always logic 1.
This is shown in Fig.3.2.12.
54
Fig. 79. complementation operation using OR

Fig.3.2.12 Complementation law in Boolean algebra
Truth table for equation 3.2.1 and is given in table 3.2.2
Table 3.2.11
Inputs
Output
+
0
1
1
1
0
1
Table 35. truth table for idempotent law using OR
2.10 Basic Theorems and Proof
De Morgan equivalent symbolsBy use of De Morgan's theorem,
an AND function is identical to an OR function with negated inputs and outputs.
Likewise, an OR function is identical to an AND function with negated inputs
and outputs. Similarly, a NAND gate is equivalent to an OR gate with negated
inputs, and a NOR gate is equivalent to an AND gate with negated inputs.
The leads to an alternative set of symbols for basic gates that use the opposite
core symbol (AND or OR) but with the inputs and outputs negated . Use of these
alternative symbols can make logic circuit diagrams much clearer and help to
show accidental connection of an active high output to an active low input or
vice-versa. Any connection that has logic negations at both ends can be replaced
by a negationless connection and a suitable change of gate or vice-versa. Any
connection that has a negation at one end and no negation at the other can be
made easier to interpret by instead using the De Morgan equivalent symbol at
either of the two ends. When negation or polarity indicators on both ends of a
connection match, there is no logic negation in that path (effectively, bubbles
"cancel"), making it easier to follow logic states from one symbol to the next.
This is commonly seen in real logic diagrams - thus the reader must not get into
the habit of associating the shapes exclusively as OR or AND shapes, but also
take into account the bubbles at both inputs and outputs in order to determine
the "true" logic function indicated.
All logic relations can be realized by using NAND gates (this can also be done
using NOR gates). De Morgan's theorem is most commonly used to transform
all logic gates to NAND gates or NOR gates. This is done mainly since it is easy
55
to buy logic gates in bulk and because many electronics labs stock only NAND
and NOR gates.
2.11
De Morgans Theorems
De-Morgans theorems is one of the most important theorems of Boolean
algebra, since it formulates the relationship between N (AND) and N (OR)
functions that allows one type of function to be implemented using a different
type of gate. This is also known as Law of dualisation.
1. De-Morgans first theorem:
In words, it says the complement of a sum equals the product of the
complements. Boolean expression for the above is B A B. A . This equation
means that a NOR function can be implemented by inverting the two inputs to
an AND function. Fig. 3.1.1 shows the logic diagram and truth table for twoinput De-Morgans first theorem. This theorem supports the fact that a NOR
gate is the same as inverting the inputs into an AND gate (bubbled AND).
B
0
0
1
1
A
0
1
0
1
B.A
0
0
0
1
+
1
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
Fig. 80. De-Morgans theorem

2. De-Morgans second theorem:
In words, it says the complement of a product equals the sum of the
complements. Boolean expression for the above is BA B. A . This equation
means that a NAND function can be implemented by inverting the two inputs to
an OR function. Fig. 3.1.2 shows the logic diagram and truth table for two-input
De-Morgans second theorem.
56
B
0
0
1
1
A
0
1
0
1
B.A
0
0
0
1
BA
B A
.
1
1
1
0
1
1
0
0
1
0
1
0
1
1
1
0
B. A
B. A
A mathematician named DeMorgan developed a pair of important rules regarding

group complementation in Boolean algebra. By group complementation, I'm
referring to the complement of a group of terms, represented by a long bar over
more than one variable.
You should recall from the chapter on logic gates that inverting all inputs to a gate
reverses that gate's essential function from AND to OR, or vice versa, and also
inverts the output. So, an OR gate with all inputs inverted (a Negative-OR gate)
behaves the same as a NAND gate, and an AND gate with all inputs inverted (a
Negative-AND gate) behaves the same as a NOR gate. DeMorgan's theorems
state the same equivalence in "backward" form: that inverting the output of any
gate results in the same function as the opposite type of gate (AND vs. OR) with
inverted inputs:
A long bar extending over the term AB acts as a grouping symbol, and as such is
entirely different from the product of A and B independently inverted. In other
words, (AB)' is not equal to A'B'. Because the "prime" symbol (') cannot be
stretched over two variables like a bar can, we are forced to use parentheses to
make it apply to the whole term AB in the previous sentence. A bar, however, acts
as its own grouping symbol when stretched over more than one variable. This has
profound impact on how Boolean expressions are evaluated and reduced, as we
shall see.
DeMorgan's theorem may be thought of in terms of breaking a long bar symbol.
When a long bar is broken, the operation directly underneath the break changes
from addition to multiplication, or vice versa, and the broken bar pieces remain
over the individual variables. To illustrate:
57
When multiple "layers" of bars exist in an expression, you may only break one
bar at a time, and it is generally easier to begin simplification by breaking the
longest (uppermost) bar first. To illustrate, let's take the expression (A + (BC)')'
and reduce it using De-Morgan's Theorems:
Fig. 81. Reduce using De-Morgan theorem

Following the advice of breaking the longest (uppermost) bar first, I'll begin by
breaking the bar covering the entire expression as a first step:
As a result, the original circuit is reduced to a three-input AND gate with the A
input inverted:
Fig. 82. After simplify

You should never break more than one bar in a single step, as illustrated here:
As tempting as it may be to conserve steps and break more than one bar at a time,
it often leads to an incorrect result, so don't do it!
58
It is possible to properly reduce this expression by breaking the short bar first,
rather than the long bar first:
The end result is the same, but more steps are required compared to using the first
method, where the longest bar was broken first. Note how in the third step we
broke the long bar in two places. This is a legitimate mathematical operation, and
not the same as breaking two bars in one step! The prohibition against breaking
more than one bar in one step is not a prohibition against breaking a bar in more
than one place. Breaking in more than one place in a single step is okay; breaking
more than one bar in a single step is not.
You might be wondering why parentheses were placed around the sub-expression
B' + C', considering the fact that I just removed them in the next step. I did this to
emphasize an important but easily neglected aspect of DeMorgan's theorem. Since
a long bar functions as a grouping symbol, the variables formerly grouped by a
broken bar must remain grouped lest proper precedence (order of operation) be
lost. In this example, it really wouldn't matter if I forgot to put parentheses in after
breaking the short bar, but in other cases it might. Consider this example, starting
with a different expression:
59
As you can see, maintaining the grouping implied by the complementation bars
for this expression is crucial to obtaining the correct answer.
Let's apply the principles of De-Morgan's theorems to the simplification of a gate
circuit:
As always, our first step in simplifying this circuit must be to generate an

equivalent Boolean expression. We can do this by placing a sub-expression label
at the output of each gate, as the inputs become known. Here's the first step in this
process:
Fig. 83. Starting from input to get Boolean expression
Next, we can label the outputs of the first NOR gate and the NAND gate. When
dealing with inverted-output gates, I find it easier to write an expression for the
gate's output without the final inversion, with an arrow pointing to just before the
inversion bubble. Then, at the wire leading out of the gate (after the bubble), I
write the full, complemented expression. This helps ensure I don't forget a
complementing bar in the sub-expression, by forcing myself to split the
expression-writing task into two steps:
60
Fig. 84. Starting from input to get Boolean expression

Finally, we write an expression (or pair of expressions) for the last NOR gate:
Fig. 85. Starting from input to get Boolean expression on

Now, we reduce this expression using the identities, properties, rules, and
theorems (DeMorgan's) of Boolean algebra:
61
The equivalent gate circuit for this much-simplified expression is as follows:
Fig. 86. Simplified logic diagram

2.12
Duality Theorem
It states that every algebraic expression deducible from the postulate of Boolean
algebra remains valid if the operators and identity elements are interchanged.
When applying duality theorem, we simply interchange OR and AND operators
and replaced 1s by 0s and 0s by 1s. For example A+1 =1, by duality A.1 =
0.The variables are not complemented in this process
2.13
Reducing Boolean Expressions:

Every Boolean expression must be reduced to as simple as possible before
realization, became every logic operation in the expression represents a
corresponding element of hardware. Realization of a digital circuit with minimal
expression- reduction of cost and complexity.-increase in reliability, reduction
techniques: all the laws of Boolean algebra may be used, similar to ordinary
algbra.
Procedure:
1. Multiply all variables necessary to remove parentheses.
62
2. Look for identical terms. Only one of those terms be retained and all others
dropped.
AB+AB+AB++AB+AB = AB
3. Look for variable and its negation in the same term. This term can be
dropped.
AB A ABB C ABCC 0
4. Look gor the pairs of terms that are identical except for one variable which
may be missing in of the terms. The larger term cam be dropped.
AB C D AB C ABC
5. Look for the pairs of terms, which have the same variables, with one or
more variables complemented. If a variable in term of such a pair is
complemented while in the second term it is not, then such term can be
combined into a single term with that variable dropped.
= AB C D AB C D ABC
Boolean expressions and logic diagrams:
Can be realized as hardware using logic gates. Conversely, hardware can be
translated into Boolean expression for analysis of circuits.
1. Converting Boolean expressions to logic:
To start with the output and work towards the input.
2. Converting logic to Boolean expressions:
To start with the input and work towards the output.
2.14
Canonical and standard forms

Digital circuits are frequently constructed with NAND or NOR gates rather then
with AND and OR gates. Universal gates are easier to fabricate with electronic
components and are the basic gates used in all IC digital logic families.
Minterms and maxterms for two variables
Minterms
Maxterms
B
A
Term
Designation Term
Designation
0
0
B A
M0
m0
BA
0
1
M1
m1
BA
B A
1
0
M2
m2
BA
B A
BA
1
1
M3
m3
BA
Table 36. truth table for maxterms and minterms
Now consider two binary variables B and A combined with an AND gate
operation. Since each variable may appear in either form, there are four possible
combinations: B A , B A , B A , and B A . Each of these four AND terms is
called a minterm, or a standard product. In a similar manner, n variables can be
combined to form 2nminterms. Each minterms is obtained from an AND term of
the n variables, with each variable being primed if the corresponding bit of the
binary number is a 0 and unprimed if a 1.
In a similar manner, n variables forming an OR term, with each variable being
primed or unprimed, provide 2n possible combinations, called maxterms, or
standard sums. It is important to note that63
(1) Each maxterm is obtained from an OR term of the n variables, with each
variable being unprimed if the corresponding bit is a 0 and primed if a 1,
and
(2) Each maxterms is the complement of its corresponding minterms and vice
versa.
(i)
SOP (sum of the Product terms ) sum of Minterms:
It is sometimes convenient to express a Boolean function in its sum-of-minterms
form. If the function is not in this form, it can be made so by first expanding the
expression in to a sum of AND terms. Each term is then inspected to see if it
contains all the variables. If it misses one or more variables, it is ANDed with an
expression such as A A , where A is one of the missing variables.
Steps for the expansion of a Boolean expression in SOP form to the standard SOP
form:
1. Write down all the terms.
2. If one or more variable are missing in any term, expand that term by
multiplying it with the sum of each of the missing variables and its
compliments.
3. Drop out redundant terms.
4. Direct method:
a. Write down all the terms.
b. Put Xs in terms where variable must be inserted to form a minterm.
c. Replace the non-complimented variable by 1 and the complemented
variables by 0, and use all combinations of Xs in terms of 0 and 1 to
generate minterms.
d. Droup out all the redundant terms.
If the Boolean function in sum of products (SOP) form. Consider the given logic
function in SOP form; y1 AB CD .This function can be implemented with (a)
AND and OR gates, (b) NAND-NAND, and (c) NOR-NOR as shown in Fig.3.3.1.
In (b) the AND gates are replaced by NAND gates and the OR gates by NAND
gates with an OR-invert graphic symbol (bubbled OR), similarly in (c) the AND
gates are replaced by NOR gates and the OR gates by NOR gates. Remember that
a bubble denotes complementation and two bubbles along the same line represent
double complementation, so both can be removed. Therefore, the given SOP
equation is implemented by universal gates only, but minimum number of
gates/IC is required in NAND-NAND implementation.
Following tables summarizes the converting non standard SOP to standard form
and vice versa.
SOP
Standard
SOP
y AB A
y BA A B
y B A
In second term B is In first term A and in No missing terms
missing
second term B is
missing
y AB A ( B B )
y ( A A ) B A ( B B ) y BA A B
AB A B A B
AB A B A B A B
64
y AB A X
y XB A X
y AB A B
11 00 01
01 10 10 11
11 00
m (0,2,3)
m ( m 0 m 2 m3 )
m ( m 0 m3 )
m 0 m 2 m3
y AB A ( BB )
y ( A A)B A(B B )
y BA A B
AB A B A B
Missing minterms
AB A B A B A B
Missing minterms
Missing minterms
y M (M 1 )
y M (M 1 )
y M (M 1 .M 2 )
POS
yB
yA
y B A
Standard
POS
y AA B
y A BB
( A B ).( A B )
y ( A B ).( A B )
y B A
M ( M 0 )
M ( M 0 .M 2 )
M ( M 2 .M 3 )
Missing Maxterm
Missing Maxterm
Standard
SOP
Standard
POS
Standard
POS
Standard
SOP
y m(1.3)
Table 37.
y m(0,1)
Missing Maxterm
y m(1,2,3)
truth table for maxterms and minterms
POS function:
Steps for the expansion of a Boolean expression in POS form to the standard POS
form:
1. Write down all the terms.
2. If one or more variable are missing in any term, expand that term by
adding it with the product of each of the missing variables and its
compliments.
3. Drop out redundant terms.
4. Direct method:
a. Write down all the terms.
b. Put Xs in terms where variable must be inserted to form a maxterms.
c. Replace the non-complimented variable by 0 and the complemented
variables by 1, and use all combinations of Xs in terms of 1 and 0
to generate maxterms.
d. Drop out all the redundant terms.
If the Boolean function in sum of products (POS) form. Consider the given logic
function in POS form; y2 ( A B).(C D) .This function can be implemented
with (a) OR and AND gates, (b) NOR- NOR, and (c) NAND-NAND, as shown in
Fig.3.3.2. In (b) the OR gates are replaced by NOR gates and the AND gates by
NOR gates with an AND-invert graphic symbol (bubbled AND), similarly in (c)
the AND gates are replaced by NAND gates and the OR gates by NAND gates.
Remember that a bubble denotes complementation and two bubbles along the
same line represent double complementation, so both can be removed. Therefore,
the given POS equation is implemented by universal gates only, but minimum
number of gates/IC is required in NOR-NOR implementation.
65
Logic Gates and Boolean Algebra

Remember These:
Boolean addition is equivalent to the OR logic function, as well as parallel switch contacts.
Boolean multiplication is equivalent to the AND logic function, as well as series switch contacts.
Boolean complementation is equivalent to the NOT logic function, as well as normally-closed relay
contacts.
DeMorgan's Theorems describe the equivalence between gates with inverted inputs and gates with
inverted outputs. Simply put, a NAND gate is equivalent to a Negative-OR gate, and a NOR gate is
equivalent to a Negative-AND gate.
When "breaking" a complementation bar in a Boolean expression, the operation directly underneath
the break (addition or multiplication) reverses, and the broken bar pieces remain over the respective
terms.
It is often easier to approach a problem by breaking the longest (uppermost) bar before breaking any
bars under it. You must never attempt to break two bars in one step!
Complementation bars function as grouping symbols. Therefore, when a bar is broken, the terms
underneath it must remain grouped. Parentheses may be placed around these grouped terms as a help
to avoid changing precedence.
Sum-Of-Products, or SOP, Boolean expressions may be generated from truth tables quite easily, by
determining which rows of the table have an output of 1, writing one product term for each row, and
finally summing all the product terms. This creates a Boolean expression representing the truth table
as a whole.
Sum-Of-Products expressions lend themselves well to implementation as a set of AND gates
(products) feeding into a single OR gate (sum).
Product-Of-Sums, or POS, Boolean expressions may also be generated from truth tables quite easily,
by determining which rows of the table have an output of 0, writing one sum term for each row, and
finally multiplying all the sum terms. This creates a Boolean expression representing the truth table
as a whole.
Product-Of-Sums expressions lend themselves well to implementation as a set of OR gates (sums)
feeding into a single AND gate (product).
NAND and NOR gates are universal: that is, they have the ability to mimic any type of gate, if
interconnected in sufficient numbers.
To convert a gate circuit to a Boolean expression, label each gate output with a Boolean subexpression corresponding to the gates' input signals, until a final expression is reached at the last
gate.
To convert a Boolean expression to a gate circuit, evaluate the expression using standard order of
operations: multiplication before addition, and operations within parentheses before anything else.
To convert a ladder logic circuit to a Boolean expression, label each rung with a Boolean subexpression corresponding to the contacts' input signals, until a final expression is reached at the last
coil or light. To determine proper order of evaluation, treat the contacts as though they were resistors,
and as if you were determining total resistance of the series-parallel network formed by them. In
other words, look for contacts that are either directly in series or directly in parallel with each other
first, then "collapse" them into equivalent Boolean sub-expressions before proceeding to other
contacts.
To convert a Boolean expression to a ladder logic circuit, evaluate the expression using standard
order of operations: multiplication before addition, and operations within parentheses before
anything else.
Logic gates most commonly used are AND, OR. NOT. NAND, NOR, XOR. XNOR
NAND and NOR are universal gates.
Output of AND gate is low even if one input is low (Y = A.B) where A and B are inputs and Y is the
output.
Output of OR gate is high if any one input is high (Y = A + B)
In NOT gate, when a high is applied as input, a low appears at output and vice versa.
66
NAND gate has output high when any one of its input is low.
The output of NOR gate is high when any input is low.
Output of XOR gate is high if one an only one input is high.
The output of XNOR gate is high when all inputs are high.
NAND and NOR can be used to realize any gate.
SOP involves sum of given product terms and these terms are known as minterms (m).
POS involves product of given sum terms of these are known as maxterms (M).
67
Problems:
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
2.27
2.28
2.29
2.30
2.31
2.32
Construct the truth table for F =

Convert the given expression in canonical SOP form Y = AC + AB + BC
Evaluate the expressions
(i)
A+1;
(ii)
A + A;
In a function of six variables the total maximum number of terms which the expression
can have will be?
Explain the difference between Boolean operations OR and XOR. Use truth tables to
described how these operations differ.
Realize and OR and NOT using NOR gates.
Realize X-OR function using NOR gates only.
Realize OR, AND, NOT, NOR gates using NAND gates only.
Tell some of applications of buffer?
Give two ways of converting a two input NAND gate to an inverter?
Why is most interrupts active low?
Design a three-input NAND gate using only two-input NAND gates.
Design a four-input NAND gate using only two-input NAND gates.
Implement the following circuits:
(i)
3 input NAND gate using min no of 2 input NAND Gates
(ii)
3 input NOR gate using min no of 2 input NOR Gates
(iii)
3 input XNOR gate using min no of 2 input XNOR Gates
Design a 2 input AND gate using a 2 input XOR gate.
Why is an understanding of Boolean algebra important to computer scientists?
Which Boolean operation is referred to as a Boolean product?
Which Boolean operation is referred to as a Boolean sum?
Create truth tables for the Boolean operators OR, AND, and NOT.
What is the Boolean duality principle?
Why is it important for Boolean expressions to be minimized in the design of digital
circuits?
What is the relationship between transistors and gates?
Name the four basic logic gates.
What are the two universal gates described in this chapter? Why are these universal
gates important?
Describe the basic construction of a digital logic chip.
Write the complements formula for integer and fractional part.
Prove that complement of complements is original number.
Reduce A B( D C D) B( A A CD) into one literal.
Reduce A C ABC AC AB into two literals.
Convert ( A B)( B C )(C A) into CPOS form.
Convert AB C A BC into its POS form.
Identify each of the following Boolean equations as a POS, SOP, and both.
AB C BC A C
(1)
(2)
( A C )( B C )
(3)
AC ( B C )
A B C BD
(4)
( AB D)( A C D)
(5)
68
2.33
2.34
2.35
2.36
2.37
Implement A B A B BC using only two input NAND gates only.

Show that a positive logic NAND gate is a negative logic NOR and vice-versa.
Show that EX-OR operation is commutative and associative.
Show that the dual of the EX-OR is equal to its complement.
Do 2-input EX-OR gates form a complete set of logic gates? Prove your answer.
2.38 Find the maxterms for the expression
2.39 Discuss the domestic application of gates?
69

Boolean and Gate

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Logic Gates and Boolean algebra

Dr. V. S. Bist, STO (Electronics),

Basic Logic gates

Fig. 2 different symbol of AND gate

Electrical Equivalent circuit:

Fig. 5 Electronic Circuit of AND gate

Fig. 7 Timing Diagrams for AND gate

Fig. 8 (a) pin out diagram (b) front view of 7408

Some of the available AND gate ICs are listed in Table 2.

Fig. 9. OR gate(a) MIL/ANSI Symbol (b) IEC Symbol

Electrical Equivalent circuit:

Fig. 12. Electronic Circuit of OR gate

Fig.13. (a) Relay Equivalence of OR

Fig. 15. different logic symbol of NOT gate

Fig. 16. (a) Transistor Logic circuit of NOT gate

Electrical Equivalent circuit:

Fig. 17. Electrical analogy of NOT gate

Fig. 18. Relay NOT gate

2.5 Other Logic gates:

Fig. 20. Other Logic gates

2.5.1 Exclusive-OR gates (XOR):

Fig. 21. different representation of XOR gate

Fig. 22. (a) Diode Logic circuit XOR gate

Fig. 24. two input XNOR gate

The Exclusive-NOR Gate function is achieved by combining standard gates

Table 9. input XNOR gate truth table

Fig. 25. Timing Diagrams for XNOR gate

Quad 2-input Ex-NOR

Table 10. some of the available NOR gate ICs

Fig. 27. Half Adder logic diagram

Fig. 28. Crossover comprising three XOR gates

Fig. 29. Universal Logic gates

Fig. 30 NAND gate

Table 11. 2 input NAND gate truth table

Electrical Equivalent circuit:

Fig. 32. Relay Equivalence AND and NAND gate

Fig. 33. Timing diagram for NAND gate

Integrated Circuits (ICs):

Fig. 34. pin out diagram and front view of 7400

in many forms in TTL and CMOS, as shown in

Fig.35. NOR gate symbol

Table 13. 2 input NOR gate truth table

Fig. 36. Transistor Transistor Logic (TTL) circuitNOR gate

Positive and Negative gates:

Fig. 38. NOT gate using NAND/NOR

Fig. 39. Buffer gate using NAND/NOR

(Y A.B AB , NAND NAND combinatio n} , therefore, the combination of two

Fig. 40. AND gate using NAND/NOR

Fig. 41. OR gate using NAND/NOR

Fig. 42. NAND gate using NOR

a. NOR as an NAND operation:

The output of two-input NOR gate is ( Y A B A . B ). It indicates, the combination of

Fig. 43. NOR gate using NAND

b. NAND as an Ex-OR operation:

Minimum number NAND gate used in the second way method.

Fig. 44. EX-OR using only NAND

Minimum number NAND gate used in the second way method.

Fig. 45. EX-OR using only NOR

NAND as an Ex-NOR operation:

Fig. 46. EX-NOR using only NAND

Fig. 47. EX-NOR using only NOR

Data control enable/inhibit of gates.

Table20. truth table for AND gate as an Enable/Inhibit.