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APPLICATION NOTE
This paper describes in detail the principle of operation of the MC34063 and A78S40 switching regulator subsystems. Several
converter design examples and numerous applications circuits with test data are included.
INTRODUCTION
The MC34063 and A78S40 are monolithic switching
regulator subsystems intended for use as dc to dc converters.
These devices represent a significant advancement in the
ease of implementing highly efficient and yet simple
switching power supplies. The use of switching regulators
is becoming more pronounced over that of linear regulators
because the size reductions in new equipment designs
require greater conversion efficiency. Another major
advantage of the switching regulator is that it has increased
application flexibility of output voltage. The output can be
less than, greater than, or of opposite polarity to that of the
input voltage.
control signal will go low and turn off the gate, terminating
any further switching of the seriespass element. The output
voltage will eventually decrease to below nominal due to the
presence of an external load, and will initiate the switching
process again. The increase in conversion efficiency is
primarily due to the operation of the seriespass element
only in the saturated or cutoff state. The voltage drop across
the element, when saturated, is small as is the dissipation.
When in cutoff, the current through the element and likewise
the power dissipation are also small. There are other
variations of switching control. The most common are the
fixed frequency pulse width modulator and the fixed
ontime variable offtime types, where the onoff
switching is uninterrupted and regulation is achieved by
duty cycle control. Generally speaking, the example given
in Figure 1b does apply to MC34063 and A78S40.
PRINCIPLE OF OPERATION
In order to understand the difference in operation between
linear and switching regulators we must compare the block
diagrams of the two stepdown regulators shown in Figure
1. The linear regulator consists of a stable reference, a high
gain error amplifier, and a variable resistance seriespass
element. The error amplifier monitors the output voltage
level, compares it to the reference and generates a linear
control signal that varies between two extremes, saturation
and cutoff. This signal is used to vary the resistance of the
seriespass element in a corrective fashion in order to
maintain a constant output voltage under varying input
voltage and output load conditions.
The switching regulator consists of a stable reference and
a high gain error amplifier identical to that of the linear
regulator. This system differs in that a free running oscillator
and a gated latch have been added. The error amplifier again
monitors the output voltage, compares it to the reference
level and generates a control signal. If the output voltage is
below nominal, the control signal will go to a high state and
turn on the gate, thus allowing the oscillator clock pulses to
drive the seriespass element alternately from cutoff to
saturation. This will continue until the output voltage is
pumped up slightly above its nominal value. At this time, the
Vin
Vout
+
Linear Control
Signal
Error
Amp
Ref
Voltage
a. Linear Regulator
Vin
Vout
Gated
Latch
Error
Amp
+
Ref
Voltage
Digital
Control Signal
OSC
b. Switching Regulator
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GENERAL DESCRIPTION
The MC34063 series is a monolithic control circuit
containing all the active functions required for dc to dc
converters. This device contains an internal temperature
compensated reference, comparator, controlled duty cycle
oscillator with an active peak current limit circuit, driver,
and a high current output switch. This series was specifically
designed to be incorporated in stepup, stepdown and
voltageinverting converter applications. These functions
are contained in an 8pin dual inline package shown in
Figure 2a.
The A78S40 is identical to the MC34063 with the
addition of an onboard power catch diode, and an
uncommitted operational amplifier. This device is in a
16pin dual inline package which allows the reference and
the noninverting input of the comparator to be pinned out.
These additional features greatly enhance the flexibility of
this part and allow the implementation of more sophisticated
applications. These may include seriespass regulation of
the main output or of a derived second output voltage, a
tracking regulator configuration or even a second switching
regulator.
Latch
S
170
Timing
Capacitor
1.25 V
Reference
Regulator
+
Comp
Switch
Emitter
CT
VCC 6
Comparator
Inverting 5
Input
Q1
Ipk
7
Sense
OSC
Switch
Collector
Q2
Ipk
4 Ground
VCC
Ipk Sense
Driver
Collector
Switch
Collector
10
Timing
Capacitor
GND
Inverting
Input
12
13
14
15
16
11
GND
CT
OSC
S
B
Comp
+
1.25 V
Ref
Latch
Ipk
R
170
Op
Amp
D1
3
1
Diode
Cathode
Noninverting
Input
Diode
Anode
Inverting
Input
Switch
Emitter
VCC
Op Amp
Ref
Output
Output
FUNCTIONAL DESCRIPTION
The oscillator is composed of a current source and sink
which charges and discharges the external timing capacitor
CT between an upper and lower preset threshold. The typical
charge and discharge currents are 35 A and 200 A
respectively, yielding about a one to six ratio. Thus the
rampup period is six times longer than that of the
rampdown as shown in Figure 3. The upper threshold is
equal to the internal reference voltage of 1.25 V and the
lower is approximately equal to 0.75 V. The oscillator runs
continuously at a rate controlled by the selected value of CT.
During the rampup portion of the cycle, a Logic 1 is
present at the A input of the AND gate. If the output
voltage of the switching regulator is below nominal, a Logic
1 will also be present at the B input. This condition will
set the latch and cause the Q output to go to a Logic 1,
enabling the driver and output switch to conduct. When the
oscillator reaches its upper threshold, CT will start to
discharge and Logic 0 will be present at the A input of
the AND gate. This logic level is also connected to an
inverter whose output presents a Logic 1 to the reset input
of the latch. This condition will cause Q to go low,
disabling the driver and output switch. A logic truth table of
these functional blocks is shown in Figure 4.
The output of the comparator can set the latch only during
the rampup of CT and can initiate a partial or full oncycle
of output switch conduction. Once the comparator has set
the latch, it cannot reset it. The latch will remain set until CT
begins ramping down. Thus the comparator can initiate
output switch conduction, but cannot terminate it and the
latch is always reset when CT begins ramping down. The
comparators output will be at a Logic 0 when the output
voltage of the switching regulator is above nominal. Under
Noninverting
Input
a. MC34063
b. mA78S40
t
Discharge
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Active Condition of
Timing Capacitor, CT
Latch Inputs
Output
Switch
Begins RampUp
Begins RampDown
Ramping Down
Ramping Down
Ramping Up
Ramping Up
Begins RampUp
Begins RampDown
1
0
Timing Capacitor, CT
Output Switch
On
Off
Quiescent Operation
AN920/D
30
10
3.0
TA = 25C
VCC = 40 V
Q1
+Vin
+Vout
MC34063
A78S40
VCC = 5 V
D1
Co
RL
1.0
a. StepDown Vout Vin
0.3
0.1
0.03 0
Ichg = Idischg
0.2
0.4
0.6
0.8
VCLS, CurrentLimit Sense Voltage (V)
+Vin
MC34063
A78S40
1.0
+Vout
D1
Q1
Co
RL
Q1
+Vin
Vout
D1
A78S40
Co
RL
ton
Vout + Vin% ton or Vout + Vin
ton ) toff
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AN920/D
value. The output voltage across capacitor Co will
eventually decay below nominal because it is the only
component supply current into the external load RL. This
voltage deficiency is monitored by the switching control
circuit and causes it to drive Q1 into saturation. The inductor
current will start to flow from Vin through Q1 and, Co in
parallel with RL, and rise at a rate of I/T = V/L. The
voltage across the inductor is equal to Vin Vsat Vout and
the peak current at any instant is:
IL +
V * Vsat * Vout
Lmin + in
ton
Ipk(switch)
VoutL) VF t
Vripple(pp) +
where i t +
ton2
and i t +
t2
i t dt
t1
1
I t
2 pk
toff2
Ipk (ton2)2
Ipk (toff2)2
+ 1
) 1
2
2
Co ton
Co toff
+
IL(pk)(ton ) toff)
+ Iout (ton ) toff)
2
NIL(pk) + 2 Iout
CT + Ichg(min) Dt
DV
10 5 ton
1
I t
2 pk
C1o
IL(pk)
ton ) IL(pk)
toff + Iout ton ) Iout toff
2
2
+ 4.0
i t dt )
Ipk t2 t1
Ipk t2 t2
+ 1
) 1
t
Co on 2 0
Co toff 2 t1
t
t
And t1 + on and t2 * t1 + off
2
2
t
10 6 on
0.5
t1
Vout ) VF
t
N on +
Vin * Vsat * Vout
toff
+ 20
C1o
V
Vripple(pp)min + out (1.5
Vref
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10 3)
AN920/D
Voltage Across
Switch Q1
VCE
Voltage Across
Diode D1
VKA
Vin + VF
Vin
Vsat
0
Vin
Vin Vsat
0
VF
Ipk
Switch Q1
Current
Iin = IC(AVG)
0
Ipk
Diode D1
Current
ID(AVG)
0
Ipk
Iout = Ipk/2 = IC(AVG) + ID(AVG)
Capacitor Co
Current
0
Ipk/2
Capacitor Co
Ripple Voltage
Q+
1/2 Ipk/2
toff/2
0
+Ipk/2
ton/2
Inductor
Current
Vout + Vpk
Vout
Vripple(pp)
Vout Vpk
t0 t1
t2
5.0 ) 0.8
21.6 * 0.8 * 5.0
+ 0.37
ton(max) ) toff + 1
fmin
+
1
50
103
+ 20 ms per cycle
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The equation is:
toff +
ton(max) ) toff
ton
)1
t
off
20 10 6
0.37 ) 1
10 5 ton
CT + 4.0
+ 14.6 ms
10 5 (5.4
+ 4.0
ton(max) + 20 ms * 14.6 ms
10 6)
+ 216 pF
+ 5.4 ms
Vin = 24 V
47
Rsc
R2
R1
36 k
12 k
2.7
CT
220 pF
10
11
GND
CT
OSC
12
14
15
16
Ipk
S
Comp
+
1.25 V
Ref
170
Op
Amp
D1
13
VCC
1N5819
853 H
Vout
5 V/50 mA
L
Co
27
Test
Conditions
Results
Line Regulation
Vin = 18 to 30 V, Iout = 50 mA
= 16 mV or 0.16%
Load Regulation
Vin = 24 V, Iout = 25 to 50 mA
= 28 mV or 0.28%
Output Ripple
Vin = 24 V, RL = 0.1
Vin = 24 V, Iout = 50 mA
45.3%
Vin = 24 V, Iout = 50 mA
72.6%
24 mVpp
105 mA
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9. The nominal output voltage is programmed by the
R1, R2 resistor divider. The output voltage is:
+ 100 mA
R1 +
* Vsat * Vout
Vin(min)Ipk(switch)
ton(max)
R2 + R1
R2 + 12
+ 36 k
0.33
Ipk(switch)
115
0.33
10 3
Vout + Vin
8 (25
t
tton
5.0 * 1
1.25
Co +
103
10 6
+ 115 mA
out * 1
V1.25
V * Vsat * Vout
Ipk(switch) + in
ton(max)
Lmin
+ 24 * 0.8 * 5.0 5.4
853 10 6
1.25
10 6
10 6
Rsc +
100
+ 12, 500 W
+ 853 mH
Vout + 1.25 R2 ) 1
R1
10 3)
10 6)
10 3)
+ 10 mF
IL +
Vin *L Vsat t
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Voltage Across
Switch Q1
VCE
Diode D1 Voltage
VKA
Vout + VF
Vin
Vsat
0
Vout Vsat
0
VF
Ipk
Switch Q1
Current
0
Ipk
Diode D1
Current
Iout
0
Ipk
Inductor
Current
Iin = IL(AVG)
0
Ipk Iout
Capacitor Co
Current
1/2(Ipk Iout)
0
Iout
Capacitor Co
Ripple Voltage
Q+
toff
t1
Vout + Vpk
ton
Vripple(pp)
Vout
Vout Vpk
IL(pk)
toff + Iout (ton ) toff)
2
t
IL(pk) + 2 Iout on ) 1
toff
Vin * Vsat
V
) VF * Vin
ton + out
toff
L
L
t
V
) VF * Vin
N on + out
Vin * Vsat
toff
Vin * Vsat
Lmin +
t
Ipk(switch) on(max)
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AN920/D
capacitor current waveforms in Figure 10, t1 is defined as the
capacitor charging interval. Solving for t1 in known terms
yields:
Vout ) VF * Vin(min)
ton
+
Vin(min) * Vsat
toff
+ 28 ) 0.8 * 6.75
6.75 * 0.3
Ipk * Iout
Ipk
+
t1
toff
+ 3.42
Ipk * Iout
Nt1 +
toff
Ipk
ton(max) ) toff + 1
fmin
Ipk * Iout
I+
t
t1
C1o
t1
20 10 6
toff +
3.42 ) 1
Ipk * Iout t2 t1
+ 1
2 0
t1
Co
+ 4.5 ms
(Ipk * Iout)
+ 1
t1
2
Co
ton + 20 ms * 4.5 ms
+ 15.5 ms
103
+ 20 ms per cycle
Ipk * Iout
t dt
t1
1
50
CT + 4.0
+ 4.0
ICouto ton
10 5 ton
10 5 (15.5
10 6)
+ 620 pF
t
Ipk(switch) + 2 Iout on ) 1
toff
I
A + (toff * t1) out
2
+ 2 (50
10 3) (3.42 ) 1)
+ 442 mA
Lmin +
+
* Vsat
Vin(min)
ton
Ipk(switch)
6.75 * 0.3 15.5
442
10 3
+ 226 mH
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10 6
AN920/D
7. A value for the current limit resistor, Rsc, can now be
determined by using the current level of Ipk(switch)
when Vin = 9.0 V.
Co [
V * Vsat
Ipk(switch) + in
ton(max)
Lmin
+
50
140
10 3
15.5
10 3
10 6
[ 50 mF
10 6
+ 597 mA
0.33
Rsc +
Ipk(switch)
+
9 Iout
t
Vripple(pp) on
V
Vripple(pp) + out 1.5
Vref
10 3
+ 28 1.5
1.25
10 3
0.33
597 10 3
+ 33.6 mV
V
Eripple(pp) + out 1.5
Vref
I
10 3 ) out ton ) Ipk ESR
Co
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AN920/D
Vin = 9 V
+
47
226 H
Rsc
R2
R1
47 k
2.2 k
0.5
CT
620 pF
10
11
GND
CT
OSC
12
13
VCC
14
15
16
Ipk
S
Comp
+
1.25 V
Ref
170
Op
Amp
D1
240
1N5819
*
Co
27
Test
Conditions
Vout
5 V/50 mA
Results
Line Regulation
= 120 mV or 0.21%
Load Regulation
= 50 mV or 0.09%
Output Ripple
90 mVpp
62.2%
74.2%
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AN920/D
Vin
L
Rsc
CT
9
10
11
GND
CT
OSC
12
14
15
16
Ipk
S
Comp
+
1.25 V
Ref
170
Op
Amp
D1
13
VCC
R2
R1
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Vout
+
Co
AN920/D
The current required to drive the internal 170
baseemitter resistor is:
I170 W +
8
1
S
Vin
2
Ipk
+ 4.1 mA
Q1
7
Rsc
+ 0.7
170
Q2
OSC
D1
CT
VCC
3
1.25 V
Reference
Regulator
+
Comp
GND
Rdriver +
CT
VZ = Vout 1.25 V
Co
Vout + 1.25 1 ) R2
R1
Vout + Vin
500
1.25
10 6
out * 1
V1.25
+ 2200
28 * 1
1.25
|Vout| ) VF
t
N on +
Vin * Vsat
toff
Ipk(switch)
Bf
442
tton
off
Then R2 + R1
VOLTAGEINVERTING SWITCHING
REGULATOR OPERATION
The basic voltageinverting switching regulator is shown
in Figure 7c and the operating waveforms are in Figure 14.
Energy is stored in the inductor during the conduction time
of Q1. Upon turnoff, the energy is transferred to the output
filter capacitor and load. Notice that in this configuration the
output voltage is derived only from the inductor. This allows
the magnitude of the output to be set to any value. It may be
less than, equal to, or greater than that of the input and is set
by the following relationship:
4
Vout
R1
VBE(switch)
170
10 3
20
+ 22.1 mA
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AN920/D
Vin
Vsat
0
Voltage Across
Switch Q1
VCE
Switch Q1
Current
Iin = IC(AVG)
0
Ipk
Diode D1
Current
Iout
0
Ipk
Inductor
Current
0
Ipk Iout
Capacitor Co
Current
1/2(Ipk Iout)
0
Iout
Capacitor Co
Ripple Voltage
Q+
toff
t1
Vout + Vpk
ton
Vripple(pp)
Vout
Vout Vpk
ton(max) ) toff + 1
fmin
+
50
1
10 3
+ 20 ms
|Vout| ) VF
ton
+
Vin * Vsat
toff
ton + 20 ms * 8.9 ms
+ 11.1 ms
+ 15 ) 0.8
13.5 * 0.8
+ 1.24
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AN920/D
Note again that the ratio of ton/(ton + toff) does not
exceed the maximum of 0.857.
Vin = 15 V
100
R2
36 k
Q2
MPS
U51A
Rsc
CT
430 pF
9
10
11
GND
CT
OSC
12
13
VCC
14
15
16
Ipk
S
Comp
+
1.25 V
Ref
170
Op
Amp
D1
RB
160
160
1N5822
5
Vout
15 V/0.5 A
1
L
66.5 H
Co
470
R1
3.0 k
RBE
0.12
Co
470
Conditions
Results
Line Regulation
= 3.0 mV or 0.01%
Load Regulation
= 27 mV or 0.09%
Output Ripple
Vin = 15 V, RL = 0.1
2.5 A
Efficiency
80.6%
35 mVpp
10 5 ton
10 5 (11.1
t
Ipk(switch) + 2 Iout on ) 1
toff
+ 2 (500
10 6)
10 3) (1.24 ) 1)
+ 2.24 A
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Lmin +
* Vsat
Vin(min)
ton
Ipk(switch)
10 6
R1 +
VinL*minVsat ton
Then R2 +
10 6
+ 36 k
IB +
+ 64 mA
10 6
RBE +
[ 92.5 mF
|Vout|
1.5
Vref
+ 15 1.5
1.25
10 3
10 (35)
2.24
IRBE +
VBE (Q2)
RBE
+ 0.8
160
10 Bf
Ipk(switch)
+ 18 mV
Eripple(pp) +
Ipk(switch)
Bf
+ 2.24
35
Iout
Co [
t
Vripple(pp) on
0.5
11.1
60 10 3
10 3
+ 0.33
2.62
|Vout|
R1
1.25
+ 15 3.0
1.25
0.33
Ipk(switch)
1.25
10 6
+ 2.62 A
Rsc +
400
+ 5.0 mA
I
10 3 ) out ton ) Ipk ESR
Co
RB +
+ 18 mV ) 5.9 mV ) 22.4 mV
+ 46.3 mV
AN920/D
STEP UP/DOWN SWITCHING
REGULATOR OPERATION
When designing at the board level it sometimes becomes
necessary to generate a constant output voltage that is less
than that of the battery. The stepdown circuit shown in
Figure 16a will perform this function efficiently. However,
as the battery discharges, its terminal voltage will eventually
fall below the desired output, and in order to utilize the
remaining battery energy the stepup circuit shown in
Figure 16b will be required.
+Vin
Q1
+Vout
L
D1
Co
General Applications
Q2
+Vout
D2
Co
+Vin
Q1
L
D1
+Vout
D2
Q2
Co
ton
Vout ) VFD1 ) VFD2
+
toff
Vin(min) * VsatQ1 * VsatQ2
+ 10 ) 0.6 ) 0.6
7.5 * 0.8 * 0.8
+ 1.9
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3. Next calculate ton and toff from the ratio of ton/toff in
#1 and the sum of ton(max) + toff in #2.
toff +
ton(max) ) toff
ton
)1
t
Lmin +
off
20 10 6
1.9 ) 1
ton + 20 ms * 6.9 ms
Ipk(switch) +
10 6)
+ 1.41 A
t
Ipk(switch) + 2 Iout on ) 1
toff
+ 2 (120
* VsatQ2
Vin * VsatQ1
ton(max)
Lmin
+ 524 pF
10 6
+ 13.1 ms
+ 4.0
+ 6.9 ms
CT + 4.0
VsatQ1 * VsatQ2
Vin(min) *Ipk(switch)
ton
10 3) (1.9 ) 1)
+ 696 mA
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Vout
10 V/120 mA
D1
1N5818
RBE
300
D2
1N5818
120 H
Q1
MPSU51A
Co
330
RB
150
8
1
S
Q
Q2
R
170
7
Ipk
Rsc
0.22
Vin
7.5 to 14.5 V
6
+
OSC
CT
VCC
3
+
100
Comp
1.25 V
Reference
Regulator
MC34063
GND
CT
510 pF
4
R2
9.1 k
R1
1.3 k
Conditions
Test
Results
Line Regulation
= 22 mV or 0.11%
Load Regulation
= 3.0 mV or 0.015%
Output Ripple
Efficiency
95 mVpp
1.54 A
74%
0.33
Ipk(switch)
+ 0.33
1.41
+ 0.23 W
Iout
Vripple(pp)
ton
120
100
10 3
13.1
10 3
Vripple(pp) +
VVout
1.5
ref
10 3
10 1.5
1.25
10 3
+ 12 mV
10 6
[ 15.7 mF
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DESIGN CONSIDERATIONS
As previously stated, the design equations for Lmin were
based upon the assumption that the switching regulator is
operating on the onset of continuous conduction with a fixed
input voltage, maximum output load current, and a
minimum chargecurrent oscillator. Typically the oscillator
chargecurrent will be greater than the specific minimum of
20 microamps, thus ton will be somewhat shorter and the
actual LC operating frequency will be greater than predicted.
Also note that the voltage drop developed across the
currentlimit resistor Rsc was not accounted for in the ton/toff
and Lmin design formulas. This voltage drop must be
considered when designing high current converters that
operate with an input voltage of less than 5.0 V.
When checking the initial switcher operation with an
oscilloscope, there will be some concern of circuit instability
due to the apparent random switching of the output. The
oscilloscope will be difficult to synchronize. This is not a
problem. It is a normal operating characteristic of this type
of switching regulator and is caused by the asynchronous
operation of the comparator to that of the oscillator. The
oscilloscope may be synchronized by varying the input
voltage or load current slightly from the design nominals.
High frequency circuit layout techniques are imperative
with switching regulators. To minimize EMI, all high
current loops should be kept as short as possible using heavy
copper runs. The low current signal and high current switch
and output grounds should return on separate paths back to
the input filter capacitor. The R1, R2 output voltage divider
should be located as close to the IC as possible to eliminate
any noise pickup into the feedback loop. The circuit
diagrams were purposely drawn in a manner to depict this.
All circuits used molypermalloy power toroid cores for
the magnetics where only the inductance value is given. The
number of turns, wire and core size information is not given
since no attempt was made to optimize their design. Inductor
and transformer design information may be obtained from
the magnetic core and assembly companies listed on the
switching regulator component source table.
In some circuit designs, mainly stepup and
voltageinverting, a ratio of ton/(ton + toff) greater than
0.857 may be required. This can be obtained by the addition
of the ratio extender circuit shown in Figure 19. This circuit
uses germanium components and is temperature sensitive.
A negative temperature coefficient timing capacitor will
help reduce this sensitivity. Figure 20 shows the output
switch on and off time versus CT with and without the ratio
extender circuit. Notice that without the circuit, the ratio of
ton/(ton + toff) is limited to 0.857 only for values of CT greater
than 2.0 nF. With the circuit, the ratio is variable depending
upon the value chosen for CT since toff is now nearly a
constant. Current limiting must be used on all stepup and
voltageinverting designs using the ratio extender circuit.
This will allow the inductor time to reset between cycles of
overcurrent during initial power up of the switcher. When
ESR [
10 3
Ref
Ipk(switch)
out * 1
VVRef
10 * 1
1.25
+ 7 R1
Ipk(switch)
Bf
696 10 3
20
+ 35 mA
10 Bf
Ipk(switch)
10 (20)
696 10 3
+ 287 W
+
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AN920/D
tontoff, Output Switch OnOff Time (s)
1
S
ton
R
170
7
Ipk
6
+
OSC
CT
1.25 V
Reference
Regulator
ton
toff
10
toff
CT
2N524
4
ton
1.0
10
CT, Oscillator Timing Capacitor (nF)
1N270
3
+
Comp
To Scope
100
100
VCC
10
5
toff
1000
ton
toff Ratio
Extender
Circuit
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100
AN920/D
APPLICATIONS SECTION
Listed below is an index of all the converter circuits shown
in this application note. They are categorized into three
Input V
Output 1
V/mA
Output 2
V/mA
Output 3
V/mA
Figure
No.
StepDown
A78S40
24
5/50
MC34063
Medium Power
36
12/750
21
MC34063
28
5.0/5000
12/300
22
A78S40
33
24/500
15/50
23
A78S40
28
15/3000
12/1000
24
A78S40
28
12/500
25
A78S40
9.0
28/50
11
MC34063
Medium Power
12
36/225
26
MC34063
4.5
190/5.0
27
A78S40
4.5
334/45
28
A78S40
2.5
9.0/100
6/30
29
A78S40
4.5
See
Circuit
30
A78S40
4.5
15/1000
12/500
12/50
31
A78S40
12
28/250
5.0/250
32
7.5 to 14.5
10/120
18
StepUp
StepUp/Down
MC34063
VoltageInverting
MC34063
Low Power
5.0
12/100
33
A78S40
15
15/500
15
A78S40
A78S40
A78S40
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23
28
120/850
34
115 Vac
5.0/4000
12/700
12/700
35
15
12/500
12/500
37
AN920/D
1
S
R
170
7
Ipk
0.2
Vin
36 V
6
47
OSC
1N5819
CT
VCC
3
+
Comp
1.25 V
Reference
Regulator
1.74 k
Test
GND
190 H
470 pF
15 k
270
Conditions
Vout
12 V/750 mA
Results
Line Regulation
= 15 mV or 0.063%
Load Regulation
= 40 mV or 0.17%
Output Ripple
Vin = 36 V, RL = 0.1
1.6 A
Efficiency
89.5%
60 mVpp
A maximum power transfer of 9.0 watts is possible from an 8pin dualinline package with Vin = 36 V and Vout = 12 V.
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AN920/D
D45VH4 (1)
MBR2540 (2)
22
51
8
1
S
Q
T
R
0.036
100
Vin
28 V
Ipk
6
2200
170
7
OSC
CT
22,000
Comp
1.25 V
Reference
Regulator
1N5819
330 pF
GND
3.6 k
1.2 k
3
+
23.1 H
VCC
1.4T
470
Vout1
5 V/5 A
Vout2
12 V/300 m A
Conditions
Test
Results
Line Regulation
Vout1
= 9.0 mV or 0.09%
Load Regulation
Vout1
= 20 mV or 0.2%
Output Ripple
Vout1
Vout1
Vin = 28 V, RL = 0.1
Line Regulation
Vout2
= 72 mV or 0.3%
Load Regulation
Vout2
= 12 mV or 0.05%
Output Ripple
Vout2
Vout2
Vin = 28 V, RL = 0.1
Efficiency
60 mVpp
11.4 A
25 mVpp
11.25 A
80%
A second output can be easily derived by winding a secondary on the main output inductor and phasing it so that energy is delivered to
Vout2 during toff. The second output power should not exceed 25% of the main output. The 100 potentiometer is used to divide down the
voltage across the 0.036 resistor and thus fine tune the current limit.
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AN920/D
Vin = 33 V
33
18.2 k
1.0 k
0.22
750 pF
9
10
11
GND
CT
OSC
12
14
15
16
Ipk
S
Comp
+
1.25 V
Ref
170
Op
Amp
D1
13
VCC
1.8 k
1
Vout2
15 V/50 mA
22 k
0.1
130 H
1N5819
100
Vout1
24 V/500 mA
2.0 k
Test
Conditions
Results
Line Regulation
Vout1
= 30 mV or 0.63%
Load Regulation
Vout1
= 70 mV or 0.15%
Output Ripple
Vout1
Vout1
Vin = 33 V, RL = 0.1
Line Regulation
Vout2
= 20 mV or 0.067%
Load Regulation
Vout2
= 60 mV or 0.2%
Output Ripple
Vout2
Vout2
Vin = 33 V, RL = 0.1
90 mA
88.2%
Efficiency
80 mVpp
2.5 A
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70 mVpp
AN920/D
Vin = 28 to 36 V
D45VH10
0.022
470
22 k
35 H
Vout1
15 V/3.0 mA
MBR1540
*
100
2.0 k
2200
51
910 pF
9
10
11
GND
CT
OSC
12
14
15
16
Ipk
S
Comp
+
1.25 V
Ref
170
Op
Amp
D1
13
VCC
820
TIP31 *
Vout2
12 V/1.0 mA
0.1
8.2 k
963
*All devices mounted on one heatsink, extra #10 hole required for
MBR2540, IERC HP3T01274CB
Conditions
Test
Results
Line Regulation
Vout1
= 13 mV or 0.043%
Load Regulation
Vout1
= 21 mV or 0.07%
Output Ripple
Vout1
Vout1
Vin = 36 V, RL = 0.1
Line Regulation
Vout2
= 2.0 mV or 0.008%
Load Regulation
Vout2
= 2.0 mV or 0.08%
Output Ripple
Vout2
Vout2
Vin = 36 V, RL = 0.1
3.6 A
78.5%
Efficiency
120 mVpp
12.6 A
25 mVpp
Figure 24. StepDown with Buffered Switch and Buffered Linear Pass from Main Output
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AN920/D
Vin = 28 V
3.09 k
100
11.8 k
275 H
Vout
12 V/500 mA
470
10
11
GND
CT
OSC
12
Test
170
D1
20 k
16
Op
Amp
470
15
+
7
10 k
14
470
Ipk
Comp
1.25 V
Ref
8
13
VCC
1N5819
820 pF
20 k
10 k
2.5 V
Conditions
Results
Line Regulation
= 25 mV or 0.104%
Load Regulation
= 10 mV or 0.042%
Output Ripple
130 mVpp
Efficiency
85.5%
In this stepdown circuit, the output switch must be connected in series with the negative input, causing the internal 1.25 V reference to be
with respect to Vin. A second reference of 2.5 V with respect to ground is generated by the Op Amp. Note that the 10 k and 20 k resistors
must be matched pairs for good line regulation and that no provision is made for output shortcircuit protection.
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AN920/D
180 H
7.75T T
1.25 V
1N5819
8
1
S
Vout
36 V/225 mA
100
R
170
7
Ipk
0.22
Vin
12 V
OSC
CT
VCC
3
+
470
Comp
1.25 V
Reference
Regulator
2.7 k
Test
GND
910 pF
75 k
Conditions
Results
Line Regulation
= 20 mV or 0.028%
Load Regulation
= 30 mV or 0.042%
Output Ripple
100 mVpp
Efficiency
90.4%
A maximum power transfer of 8.1 watts is possible with Vin = 12 V and Vout = 36 V. The high efficiency is partially due to the use of the
tapped inductor. The tap point is set for a voltage differential of 1.25 V. The range of Vin is somewhat limited when using this method.
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AN920/D
T1
Lp = 140 H
1N4936
Vout
190 V/5.0 mA
To SCD 504 Display
1.0
1
S
R
170
7
Ipk
0.24
Vin
4.5 to12 V
6
100
OSC
CT
VCC
3
+
Comp
27 k
1.25 V
Reference
Regulator
680 pF
GND
4.7 M
10 k
Test
Conditions
Results
Line Regulation
= 2.3 V or 0.61%
Load Regulation
= 1.4 V or 0.37%
Output Ripple
Efficiency
250 mVpp
113 mA
68%
This circuit was designed to power the ON Semiconductor Solid Ceramic Displays from a Vin of 4.5 to 12 V. The design calculations are
based on a stepup converter with an input of 4.5 V and a 24 V output rated at 45 mA. The 24 V level is the maximum stepup allowed by
the oscillator ratio of ton/(ton + toff). The 45 mA current level was chosen so that the transformer primary power level is about 10% greater
than that required by the load. The maximum Vin of 12 V is determined by the sum of the flyback and leakage inductance voltages present
at the collector of the output switch during turnoff must not exceed 40 V.
Figure 27. HighVoltage, Low Power StepUp for Solid Ceramic Display
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AN920/D
Vin = 4.5 to 6.0 V
D45VH10
0.022
2200
T1
27
Lp =
16.5 H
5.1
1600 pF
10
11
GND
CT
OSC
12
14
15
16
Comp
C1
500
10
0.033
170
Op
Amp
G.E.
FT118
D1
+
6
18 k
22 M
+
7
MR817
Ipk
1.25 V
Ref
8
13
VCC
1.8 M
Shutter
TRAID
PL10
4.7 M
18 k
Charging
Indicator
LED
With Vin of 6.0 V, this stepup converter will charge capacitor C1 from 0 to 334 V in 4.7 seconds. The switching operation will cease until C1
bleeds down to 323 V. The charging time between flashes is 4.0 seconds. The output current at 334 V is 45 mA.
Figure 28. HighVoltage StepUp with Buffered Switch for Photoflash Applications
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AN920/D
Vin = 2.5 V
470
62 k
10 k
40 H
0.22
10
11
GND
CT
OSC
12
14
15
16
170
Op
Amp
D1
+
6
Vout1
9.0 V/100 mA
Ipk
+
8
13
VCC
Comp
1.25 V
Ref
330
27
910 pF
9
1N5819
8.2 k
Vout2
6.0 V/30 mA
38.3 k
0.1
10 k
Test
Conditions
Results
Line Regulation
Vout1
= 20 mV or 0.11%
Load Regulation
Vout1
= 20 mV or 0.11%
Output Ripple
Vout1
Line Regulation
Vout2
= 1.0 mV or 0.0083%
Load Regulation
Vout2
= 1.0 mV or 0.0083%
Output Ripple
Vout2
Vout2
Efficiency
60 mVpp
5.0 mVpp
150 mA
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68.3%
AN920/D
Vin = 4.5 to 5.5 V
16.5 k
47
70 H
0.22
B 13.7 k
294 k
68
820 pF
9
10
11
GND
CT
OSC
12
14
15
16
Ipk
S
Comp
+
1.25 V
Ref
170
Op
Amp
D1
13
VCC
1.0 k
1.0
2N5089
470
57.6 k
470
TIP29
X
16.5 k
0.058
WRITE
TTL Input
4.7 k
VPP Output
10.2 k
47 k
3.4 k
Voltage @
Switch Position
WRITE
Pins 1 & 5
VPP
< 1.5
23.52
5.24
20.95
> 2.25
23.52
1.28
5.12
< 1.5
28.07
6.25
25.01
> 2.25
28.07
1.28
5.12
NOTE:
Used in conjunction with two transistors, the A78S40 can generate the required VPP voltage of 21 V or 25 V needed to program and erase
EEPROMs from a single 5.0 V supply. A stepup converter provides a selectable regulated voltage at Pins 1 and 5. This voltage is used to
generate a second reference at point X and to power the linear regulator consisting of the internal op amp and a TIP29 transistor. When
the WRITE input is less than 1.5 V, the 2N5089 transistor is OFF, allowing the voltage at X to rise exponentially with an approximate time
constant of 600 s as required by some EEPROMs. The linear regulator amplifies the voltage at X by four, generating the required VPP
output voltage for the byteerase write cycle. When the WRITE input is greater than 2.25 V, the 2N5089 turns ON clamping point X to the
internal reference level of 1.245 V. The VPP output will not be at approximately 5.1 V or 4.0 (1.245 + Vsat 2N5089). The A78AS40
reference can only source current, therefore a reference pre bias of 470 is used. The VPP output is shortcircuit protected and can
supply a current of 100 mA at 21 V or 75 mA at 25 V over an input range of 4.5 to 5.5 V.
Figure 30. StepUp with Buffered Linear Pass from Main Output for Programming EEPROMs
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AN920/D
Vin = 4.5 to 5.5 V
6800
22 k
2.0 k
0.022
8.8 H
5.1
1200 pF
9
10
11
GND
CT
OSC
12
13
VCC
15
16
2N5824
2200
170
Op
Amp
D1
1N5818
MC79L12
ACP
47
820
D44
VH1
(1)
27
1N5818
Vout1
15 V/1.0 mA
+
8
Ipk
Comp
1.25 V
Ref
14
47
Vout3
12 V/50 mA
0.1
TIP29
(2)
0.1
8.2 k
47
Vout2
12 V/50 mA
953
Conditions
Test
Results
Line Regulation
Vout1
= 18 mV or 0.06%
Load Regulation
Vout1
= 25 mV or 0.083%
Output Ripple
Vout1
Vin = 5.0 V
Line Regulation
Vout2
= 3.0 mV or 0.013%
Load Regulation
Vout2
= 5.0 mV or 0.021%
Output Ripple
Vout2
Vin = 5.0 V
Vout2
Line Regulation
Vout3
Load Regulation
Vout3
Output Ripple
Vout3
Vin = 5.0 V
Vout3
Efficiency
NOTE:
75 mVpp
20 mVpp
2.7 A
= 2.0 mV or 0.008%
= 29 mV or 0.12%
15 mVpp
130 mA
Vin = 5.0 V
71.8%
Figure 31. StepUp with Buffered Switch and Buffered Linear Pass from Main Output
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AN920/D
Vin = 12 V
47
47 k
108 H
0.24
2.2 k
1N5819
10
11
GND
CT
OSC
12
14
15
16
R
170
Op
Amp
10 k
D1
+
7
100
0.1
Vout1
28 V/250 mA
Ipk
+
8
13
VCC
Comp
1.25 V
Ref
470
180
470 pF
MPSU51A
1.0 M
4.4 mH
470
1N5819
2200
Vout2
5.0 V/250 mA
3.6 k
1.2 k
Conditions
Test
Results
Line Regulation
Vout1
= 30 mV or 0.054%
Load Regulation
Vout1
= 20 mV or 0.036%
Output Ripple
Vout1
Vout1
Vin = 12 V, RL = 0.1
Line Regulation
Vout2
= 4.0 mV or 0.04%
Load Regulation
Vout2
= 18 mV or 0.18%
Output Ripple
Vout2
70 mVpp
81.8%
Efficiency
35 mVpp
1.7 A
This circuit shows a method of using the A78S40 to construct two independent converters. Output 1 uses the typical stepup circuit
configuration while Output 2 makes the use of the op amp connected with positive feedback to create a free running stepdown converter.
The op amp slew rate limits the maximum switching frequency at rated load to less than 2.0 kHz.
Figure 32. Dual Switcher, StepUp and StepDown with Buffered Switch
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AN920/D
1
S
R
170
7
Ipk
0.24
Vin
4.5 to 6.0 V
100
OSC
2
88 H
CT
VCC
3
+
Comp
1.25 V
Reference
Regulator
R2
8.2 k
Test
GND
R1
953
1300 pF
1N5819
|Vout| + 1.25 1 ) R2
R1
1000
Conditions
Vout
12 V/100 mA
Results
Line Regulation
= 2.0 mV or 0.008%
Load Regulation
= 10 mV or 0.042%
Output Ripple
1.4 A
Efficiency
60%
35 mVpp
The above circuit shows a method of using the MC34063 to construct a low power voltageinverting converter. Note that the integrated
circuit ground, pin 4, is connected directly to the negative output, thus allowing the internally connected comparator and reference to
function properly for output voltage control. With this configuration, the sum of Vin + Vout + VF must not exceed 40 V. The conversion
efficiency is modest since the output switch is connected as a Darlington and its onvoltage is a large portion of the minimum operating
input voltage. A 12% improvement can be realized with the addition of an external PNP saturated switch when connected in a similar
manner to that shown in Figure 15.
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AN920/D
Vin = 28 V
Rsc
0.022
2N6438
4700
100
100 k
10
51
1050
1200 pF
10
11
GND
CT
OSC
12
14
15
16
Ipk
S
Comp
+
1.25 V
Ref
170
Op
Amp
MR822
D1
13
VCC
Vout
120 V/850 mA
1000
pF
560
Conditions
Results
Line Regulation
= 100 mV or 0.042%
Load Regulation
= 70 mV or 0.029%
Output Ripple
Vin = 28 V, RL = 0.1
6.4 A
Efficiency
81.8%
450 mVpp
This high power voltageinverting circuit makes use of a center tapped inductor to stepup the magnitude of the output. Without the tap, the
output switch transistor would need a VCE breakdown greater than 148 V at the start of toff; the maximum rating of this device is 120 V. All
calculations are done for the typical voltageinverting converter with an input of 28 V and an output of 120 V. The inductor value will be
50 H or 200 H center tapped for the value of CT used. The 1000 pF capacitor is used to filter the spikes generated by the high switching
current flowing through the wiring and Rsc inductance.
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AN920/D
output filter capacitor must have separate ground returns to
the transformer as shown on the circuit diagram. A complete
printed circuit board with component layout is shown in
Figure 36.
The A78S40 may be used in any of the previously shown
circuit designs as a fixed frequency pulse width modulator,
however consideration must be given to the proper selection
of the feedback loop elements in order to insure circuit
stability.
T1
680
12
Fusible Resistor
100
1 1/2 4N35
1N4303
2200
20
470
20 A
22
3.3 k
1.0 k
+
1000
0.1
15 k
2.0 W
Vout1
5.0 V/4.5 A
L1
MBR1635
10 11 11
3.3 k
TL431
1N965A
5.0 V
Return
1000 pF
1.0 k
10
11
GND
12
13
VCC
CT
Ipk
OSC
9
9
4
170
10
L3
MTP
4N50
MPSA55
MPS6515
4
680
1000
12 V
Return
Vout3
12 V/0.8 A
5
6
10
470 pF
560
1000
D1
8
+
Op
Amp
Vout2
12 V/0.8 A
L2
MUR110
16
15
S Q
Comp
1.25 V
Ref
14
1.0 k
1N4937
0.1
0.0047
UL/CSA
0.24
1.8 k
T1 Primary:
Pins 4 and 6 = 72 Turns #24 AWG, Bifilar Wound
Pins 5 and 6 = 72 Turns #26 AWG, Bifilar Wound
Secondary 5.0 V:
6 Turns (two strands) #18 AWG Bifilar Wound
Secondary 12 V:
14 Turns #23 AWG Bifilar Wound
1000 pF
3.9 k
*Heatsink
Thermalloy 6072BMT
Figure 35. 42 Watt OffLine Flyback Switcher with Primary Power Limiting
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AN920/D
Conditions
Test
Results
Line Regulation
Vout1
= 1.0 mV or 0.01%
Load Regulation
Vout1
= 3.0 mV or 0.03%
Output Ripple
Vout1
Vout1
40 mVpp
19.2 A
Line Regulation
Vout2 or Vout3
= 10 mV or 0.04%
Load Regulation
Vout2 or Vout3
= 384 mV or 1.6%
Output Ripple
Vout2 or Vout3
Vout2 or Vout3
10.8 A
75.7%
Efficiency
NOTE:
80 mVpp
Figure 35. (continued) 42 Watt OffLine Flyback Switcher with Primary Power Limiting
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AN920/D
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40
AN920/D
Vin = 15 V
MPSU51A
0.15
100
1N5822
Vout1
12 V/500 mA
100
Vout2
Voltage Adj
36.1 H
+
2.0 k
12 k
1.5 k
100
270
180 pF
9
10
11
GND
CT
OSC
12
14
15
16
Ipk
S
Comp
+
1.25 V
Ref
170
Op
Amp
D1
13
VCC
1
*Heatsink
IERC PSC23
6.2 k
MPSU01A *
12 k
Vout2
12 V/500 mA
0.1
200
Tracking Adj
12 k
Test
Conditions
Results
Line Regulation
Vout1
= 10 mV or 0.042%
Load Regulation
Vout1
= 2.0 mV or 0.008%
Output Ripple
Vout1
Line Regulation
Vout2
= 10 mV or 0.042%
Load Regulation
Vout2
= 5.0 mV or 0.021%
Output Ripple
Vout2
140 mVpp
77.2%
Efficiency
125 mVpp
This tracking regulator provides a 12 V output from a single 15 V input. The negative output is generated by a voltageinverting converter
while the positive is a linear pass regulator taken from the input. The 12 V outputs are monitored by the op amp in a corrective fashion so
that the voltage at the center of the divider is zero VIO. The op amp is connected as a unity gain inverter when |Vout1| = |Vout2|.
Figure 37. Tracking Regulator, VoltageInverting with Buffered Switch and Buffered Linear Pass from Input
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AN920/D
SWITCHING REGULATOR
COMPONENT SOURCES
SUMMARY
The goal of this application note is to convey the theory of
operation of the MC34063 and A78S40, and to show the
derivation of the basic first order design equations. The
circuits were chosen to explore a variety of cost effective and
practical solutions in designing switching converters.
Another major objective is to show the ease and simplicity
in designing switching converters and to remove any
mystical black magic fears. ON Semiconductor maintains
a Linear and Discrete products applications staff that is
dedicated to assisting customers with any design problems
or questions.
Capacitor
BIBLIOGRAPHY
Steve Hageman, DC/dc Converter Powers EEPROMs,
EDN, January 20, 1983.
Design Manual for SMPS Power Transformers, Copyright
1982 by Pulse Engineering.
Heatsinks
IERC
135 W. Magnolia Blvd.
Burbank, CA
(213) 8492481
Thermalloy, Inc.
2021 W. Valley View Lane
Dallas, Texas 75234
(214) 2434321
Magnetic Assemblies
Coilcraft, Inc.
1102 Silver Lake Rd.
Cary, IL 60013
(312) 6392361
Pulse Engineering
P.O. Box 12235
San Diego, CA 92112
(714) 2795900
Magnetic Cores
Ferroxcube
5083 Kings Highway
Saugerties, NY 12477
(914) 2462811
Magnetics, Inc.
P.O. Box 391
Butler, PA 16001
(412) 2828282
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