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ACKNOWLEDGMENT
The author would like to thank the anonymous reviewers and Dr.
J. Chambers for their helpful comments which substantially improved
this paper.
REFERENCES
[1] G. R. Arce and M. P. McLoughlin, Theoretical analysis of the maxmedian filter, IEEE Trans. Acoust., Speech, Signal Processing, vol.
ASSP-35, pp. 6069, Jan. 1987.
[2] P. A. Maragas and R. W. Schafer, Morphological filtersPart I: Their
set theoretic analysis and relations to linear shift invariant filters,
IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-35, pp.
11531184, Aug. 1987.
[3] R. Martin, Spectral subtraction based on minimum statistics, in Proc.
EUSIPCO-94, Edinburgh, Scotland, Sept. 1994, pp. 11821185.
[4] I. Pitas, Fast algorithms for running ordering and max/min calculation,
IEEE Trans. Circuits Syst., vol. 36, pp. 795804, 1989.
[5] D. Coltuc and I. Pitas, On fast running max-min filtering, IEEE Trans.
Circuits Syst. II, vol. 44, pp. 660664, Aug. 1997.
[6] J. Garofolo et al., DARPA TIMIT acoustic-phonetic continuous speech
corpus (CD-ROM), National Institute of Standards and Technology,
1990.
Fig. 1.
I. INTRODUCTION
With the high integration level of CMOS very large scale integration (VLSI), the capacitive load of periodic signals such as clock has
become very large. With such a large capacitive load, driving circuits
consume a relatively large portion of the total power of a VLSI. The
Manuscript received June 1999; revised June 2000. This paper was recommended by Associate Editor M. Bayoumi.
The author was with Integrated Systems Laboratory (IIS), Swiss Federal Institute of Technology, Zurich, Switzerland. He is now with Samsung Electronics,
Kiheung, Korea.
Publisher Item Identifier S 1057-7130(00)07752-1.
Fig. 2. (a) Feedback-controlled split-path CMOS buffer and (b) its timing
diagram.
power consumption of a CMOS buffer driving a capacitive load consists of dynamic switching power and short-circuit power. While the
switching-power consumption is unavoidable to drive a capacitive load,
short-circuit power is a waste of current and should be minimized or
even eliminated for low-power operation.
A conventional tapered CMOS buffer, shown in Fig. 1(a), consumes
both the dynamic switching power and short-circuit power due to simultaneous turn-on of the pull-up/pull-down transistors, as illustrated
in Fig. 1(b) [1]. Short-circuit power consumption can be eliminated by
tri-stating the output node momentarily before every output signal transition. In [2], asymmetric inverters were used as waveform shaper to
get momentary tri-state output period, but the propagation delay is increased by the asymmetric inverters. As an alternative, a feedback-controlled split-path (FS) CMOS buffer was proposed, where the output
signal is fed back to control the output pull-up and pull-down transistors, as shown in Fig. 2, tri-stating the output momentarily and thereby
eliminating the short-circuit power consumption [3]. But, in the FS
CMOS buffer, the logic states of the split output stage drivers change
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 9, SEPTEMBER 2000
TABLE I
TRANSISTOR SIZES OF THE PROPOSED
CMOS BUFFER IN FIG. 3
Fig. 5. (a) Total power consumption and (b) propagation delay of CMOS
buffers as a function of load capacitance.
twice for every output signal transition, increasing the power consumption. In charge-transfer feedback-controlled split-path (CFS) CMOS
buffer, this additional power consumption is minimized by transferring
the large charge stored in the output-stage driver to the output node
[4]. In both the FS and CFS buffer, the feedback delay t1 and t2 should
be controlled very well because if t1 and t2 are too small, the output
transistors can be turned off before the complete output transition. The
TABLE II
TOTAL ACTIVE AREA OF CMOS BUFFERS
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 47, NO. 9, SEPTEMBER 2000
In this brief, a new CMOS buffer without short-circuit power consumption is proposed. The output pull-up and pull-down transistors
are driven by separate driving signals generated so the pull-up and
pull-down transistors do not turn on simultaneously.
II. A CMOS BUFFER WITHOUT SHORT-CIRCUIT POWER
CONSUMPTION
The schematic and timing diagram of the proposed CMOS buffer
are shown in Fig. 3(a) and (b), respectively. While the output signal
itself is fed back in case of the FS and CFS buffer, the gate driving
signal N1 (N2 ) of the output pull-up (pull-down) transistor is fed back
to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption. The logic
states of the output-stage driver change only once for each output transition in the proposed buffer as opposed to twice in the FS and CFS
buffer. Since the gate driving signals are fed back instead of the output
signal itself, the feedback delay is independent of the output capacitive
load, making the optimization of the circuit much easier. The pull-up
and pull-down operations are explained respectively in the following.
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IV. CONCLUSION
A new CMOS buffer has been proposed which has no short-circuit
power consumption. The output pull-up and pull-down transistors are
driven by separate driving stages which ensure pull-up and pull-down
transistors do not turn on simultaneously. The HSPICE simulation results show about 15% improvement in the power-delay product compared to a conventional tapered CMOS buffer, and thus the proposed
buffer is suitable for low-power operation.
REFERENCES
[1] N. Li, F. Haviland, and A. Tuszynski, A CMOS tapered buffer, IEEE
J. Solid-State Circuits, vol. 25, pp. 10051008, Aug. 1990.
[2] K. Y. Khoo and A. N. Wilson Jr., Low power CMOS clock buffer,
Proc. Int. Symp. Circuits and Systems, vol. 4, pp. 355358, 1994.
[3] H.-Y. Huang and Y.-H. Chu, Feedback-controlled split-path CMOS
clock buffer, Proc. Int. Symp. Circuits and Systems, vol. 4, pp. 300303,
1996.
[4] K.-H. Cheng, W.-B. Yang, and H.-Y. Huang, The charge-transfer feedback-controlled split-path CMOS buffer, IEEE Trans. Circuits Syst, II,
vol. 46, pp. 346348, Mar. 1999.
I. INTRODUCTION
Residue Number System (RNS) has the advantage of carry-free
arithmetic operations. Therefore, using residue arithmetic would, in
principle, increase the speed of computations. Specifically, addition,
subtraction, and multiplication can be carried out on each residue digit
concurrently and independently. RNS has demonstrated a high efficiency in implementing different types of digital filters, which depends
mainly on the above mentioned operations. It has been successfully
implemented in applications involving the design of fast number
theoretic transform, discrete Fourier transform, and many other areas
[1]. Therefore, designing an efficient modular multiplier has been
an important task in realizing different RNS-based applications and
processors. The modular multiplication is defined as evaluating
jXY jm , where X; Y 2 [0; m). Defining Z as Z = jXY jm , then
Z is the least nonnegative remainder when dividing the product
Manuscript received July 1998; revised May 2000. This paper was recommended by Associate Editor W. Liu.
The author is with Electronics Engineering Department, Princess Sumaya
University, Amman 11941, Jordan.
Publisher Item Identifier S 1057-7130(00)07746-6.