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INTRODUCTION
Field Effect Transistors are preferred for weak
signal work.
They are also preferred in circuits and system
requiring high impedance
FETs are fabricated onto a silicon integrated
circuit (IC) chips
HISTORY
October 22, 1925
The first patent for the field effect transistor principle
was filed in Canada by Austrian-Hungarian physicist
Julius Edgar Lilienfeld
1934
German physicist Dr. Oskar Heil patented another field
effect transistor
Legal papers from the Bell Labs patent show that
William Shockley and a co-worker at Bell Labs, Gerald
Pearson, had built operational versions from Lilienfelds
patents
DEFINITION
The field-effect transistor (FET) is a threeterminal device
FET vs BJT
1. The FET has extremely high input resistance
with about 100 M typically (BJT input
resistance typically 2 k).
FET vs BJT
FET vs BJT
FET vs BJT
Types of FET
JFET Construction
Drain
Gate
Drain
Channel
Gate
Source
P - CHANNEL
Source
N - CHANNEL
Drain
Gate
Drain
Gate
Source
N - CHANNEL
Source
P - CHANNEL
Biasing FET
Greater VGG
Less VGG
Transconductance
It is also called dynamic mutual conductance
If the gate-source voltage changes by a small
amount dVGS then the drain current will also
change by a certain increment dID.
Transconductance
Transconductance
I D
gm
VGS
v DS 0
VGS
g m g m o 1
VP
JFET Parameters
VGS
I D I DSS 1
VP
2 I DSS
gm
VP
VGS
1
VP
ID = drain current
IDSS = drain-source
saturation current
VGS = gate-source
voltage
VP = pinch-off voltage
gm = transconductance
Sample Problems
1. Determine the drain current of an n-channel JFET
having a pinch-off voltage VP = - 4 V and the drainsource saturation current IDSS = 12 mA at VGS = 0
and VGS = - 3 V.
12 mA, 0.75 mA
Sample Problems
3.75 mS
Sample Problems
6.75 mA
Sample Problems
3.69 V
Sample Problems
3.58 mS
Sample Problems
4.525 mS
Sample Problems
6 mS
Important Relationships
JFET Biasing
Fixed Bias
VGS
I D I DSS 1
VP
VDS VDD I DR D
Vgs = -2 V
Id = 5.625 mA
Vds = 4.75 V
Self-Bias
VGS I DR S
2
V
GS
I D I DSS 1
V
GS
(
off
)
VDS VDD I D ( R D R S )
Self-Bias Configuration
Vgs = - 2.6 V
Id = 2.6 mA
Vds = 8.82 V
Voltage-Divider Bias
R2
VG VDD
R1 R 2
VG VGS
ID
RS
VDS VDD I D ( R D R S )
Vgs = - 1.8 V
Id = 2.4 mA
Vd = 10.24 V
Vs = 3.6 V
MOSFET
MOSFET
45
Schematic Symbol
Depletion MOSFET
Drain
n-channel D-MOSFET is
D
usually operated in the
SiO2
n
depletion mode with VGS
Gate
p
G
< 0 and in the
n
enhancement mode with
S
VGS > 0.
Channel
Symbol
Source
p-channel D-MOSFET
uses the opposite
Basic structure of
n-channel D-MOSFET voltage polarity
D-MOSFET Symbols
50
VP
ID = IDSS 1
VP
Basic Operation
Symbols
DMOSFET
Vgs = - 0.8 V
Id = 3.1 mA
Vds = 10.1 V
ENHANCEMENT-TYPE
MOSFET
The transfer curve is not defined by Shockleys
equation.
The drain current is now cut off until the gate-tosource voltage reaches a specific magnitude.
Current control in an n-channel device is now
effected by a positive gate-to-source voltage.
ENHANCEMENT-TYPE
MOSFET
The construction of an
enhancement-type
MOSFET is quite
similar to that of the
depletion-type
MOSFET, except for
the absence of a
channel between the
drain and source
terminals.
Basic Operation
SYMBOLS
EMOSFET Parameters
I D k VGS VGS TH
g m 2k VGS VGS TH
k = 0.3 mA/V2
VGS(TH) = threshold voltage
Advantages of MOSFET
draws no gate current at all
draws no leakage current
the input resistance of the device
is essentially infinite.
Disadvantages of
MOSFET
that thin layer of glass cant
withstand much voltage
the static charge can destroy the
device
Sample Problem
5. 25 mS
Sample Problem
What is the value of threshold voltage for an nchannel enhancement MOSFET that operates at
ID = 4.8 mA when biased at 7 V?
3V
Sample Problem
675 A
Sample Problem
1.92 mS
Sample Problem
3.33 V
Sample Problem
2 mA/V2
EMOSFET
Vgs = 6.4 V
Id = 2.75 mA
VMOS
Vertical Metal-Oxide-Silicon FET
Compared with commercially available planar
MOSFETs, VMOS FETs have reduced channel
resistance levels and higher current and power
ratings.
VMOS
CMOS
Complementary MOSFET
It has extensive applications in computer logic
design.
The relatively high input impedance, fast
switching speeds, and lower operating power
levels of the CMOS configuration have resulted
in a whole new discipline referred to as CMOS
logic design.
Characteristic parameters
Av Ai Zi Zo
Three configurations
Common-source configuration
Common-drain configuration
Common-gate configuration
SJTU
J. Chen
Characteristics of CS amplifier
81
Input resistance
Rin RG
Voltage gain
Av g m (ro // RD // RL )
RG
Gv
g m ( RD // RL // ro )
RG Rsig
Rout ro // RD
Output resistance
Summary of CS amplifier
The CG amplifier
84
A small-signal equivalent
circuit
T model is used in
preference to the model
Ro is neglected
Voltage gain
Av g m ( RD // RL )
SJTU
J. Chen
Summary of CG amplifier
86
Noninverting amplifier
Low input resistance
Relatively high output resistance
Current follower
Superior high-frequency performance
RG
ro // RL
Gv
1
RG Rsig r // R 1
o
L
gm
small drain-to-source
voltages FETs resemble
voltage-controlled resistors
the
used,