Overview

Much of the computer’s architecture /

organization is hidden from a HLL
programmer
– In the abstract sense, the programmer should
not care what the underlying architecture really
EE 4504 is
Computer Organization The instruction set is the boundary where
the computer designer and the computer
programmer can view the same machine
Thus, an examination of the instruction set
Section 7
goes a long way to explaining the
The Instruction Set computer’s CPU itself
This section investigates the design of the
instruction set and the impact of the set on
the design of the overall computer system
Readings: Chapters 9 and 10

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 Instruction content Instruction types

Each instruction must contain 4 basic An instruction set should be functionally

pieces of information complete
– Operation code: specifies the operation to be – Permit the user to formulate any high-level data
performed, expressed as a binary code processing task
– Source operand references: operands required Five categories of instructions
for the instruction are specified
– Arithmetic operations
– Result reference: where should the result of the
– Logic operations
operation be placed?
– Data movement (internal to the system)
– Next instruction reference: how / where is the
next instruction to be found – I/O (data movements between the computer and
external devices)
» In most cases, this is not explicitly stated in
the instruction – Control operations
» Next instruction is the one that logically Instruction sets have been designed with
follows the current one in the program – Small numbers of instructions (1)
(sequential / linear progression through the – Hundreds of instructions
program)
– Trend today is to use “enough” to get the job
done well (more on this in the RISC/CISC
discussions to come)

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 Until the 1980s, the trend was to construct
more and more complex instruction sets
containing hundreds of instructions and
variations
Intent was to provide mechanisms to
bridge the semantic gap, the difference in
high and low level functioning of the
computer
– Reconcile the views of the HLL programmer
and the assembly level programmer
– Provide a diverse set of instructions in an
attempt to match the programming style of HLL
– Permit the compiler to “bridge the gap” with a
single instruction rather than synthesizing a
series of instructions
– Did not always have the desired impact
EE 4504 Section 7
Wulff asserts that compiler writers might
make the better architects
– Have had to deal with poor architecture
decisions
Wulff’s attributes of a good instruction set
– Complete: be able to construct a machine-level
program to evaluate any computable function
– Efficient: frequently performed functions
should be done quickly with few instructions
– Regular and complete classes of instructions:
provide “logical” set of operations
– Orthogonal: define instructions, data types, and
addressing independently
Additional attribute:
– Compatible: with existing H/W and S/W in a
product line
5 EE 4504 Section 7 6
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 Addresses in an Instruction

In a typical arithmetic or logical 2 address instructions

instruction, 3 addresses are required -- 2 – One of the addresses is used to specify both an
operands and a result operand and the result location
These addresses can be explicitly given or – Example: X = X + Y
implied by the instruction – Very common in instruction sets

3 address instructions 1 address instructions

– Both operands and the destination for the result
are explicitly contained in the instruction word
– Example: X = Y + Z
– With memory speeds (due to caching)
approaching the speed of the processor, this
gives a high degree of flexibility to the
compiler
» Avoid the hassles of keeping items in the
register set -- use memory as one large set
of registers
– This format is rarely used due to the length of
addresses themselves and the resulting length of
the instruction words
– Two addresses are implied in the instruction
– Traditional accumulator-based operations
– Example: Acc = Acc + X
0 address instructions
– All addresses are implied, as in register-based
operations
» Example: TBA (transfer register B to A)
– Stack-based operations
» All operations are based on the use of a
stack in memory to store operands
» Interact with the stack using push and pop
operations

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 Trade off: Fewer addresses in the – 2 address
instruction results in MOV Y,A
SUB Y,B
– More primitive instructions MOV T,D
– Less complex CPU MUL T,E
– Instructions with shorter length ADD T,C
– More total instructions in a program DIV Y,T
– Longer, more complex programs
– Longer execution times – 1 address
LOAD D
Consider MUL E
ADD C
Y = (A-B) / (C+D*E) STORE Y
LOAD A
SUB B
– 3 address DIV Y
SUB Y,A,B STORE Y
MUL T,D,E
ADD T,T,C
DIV Y,Y,T

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 Types of Operations

– 0 address
» Convert to postfix (reverse Polish) notation
Y = AB-CDE*+/

PUSH A
PUSH B
SUB
PUSH C
PUSH D
PUSH E
MUL
ADD
DIV
POP Y

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 Control Operations

Common operations
– Branch
» Conditional or unconditional
» Jump to another part of the program for the
next instruction by modifying the program
counter
– Skip
» Useful in loop control
ISZ R1
BRA TOP
– Subroutine call / return
» Jump to routine with the expectation of
returning and resuming operation at the
next instruction
» Must preserve the address of the next
instruction (the return address)
Store in a register or memory location
Store as part of the subroutine itself
Store on the stack

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 Endian Wars

» Parameters can be passed to / from the Architects must specify how data is stored
subroutine in similar ways (its byte ordering) in memory and registers
» Use of the stack is the only reentrant – This leads to the “endian wars”
approach
» Big endian
» Each called subroutine is allocated a stack
frame on the stack » Little endian
Contains variable to be passed Consider the hex value $12345678 and
Return address how it is stored in memory starting at
Results to be returned address $100
– Big endian stores most significant byte in the
lowest address:
100 12
101 34
102 56
103 78
– Little endian stores the word in reverse:
100 78
101 56
102 34
103 12

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Observations:
– In storing several data items into a memory
segment, each item will have the same address
(big or little endian does not change this)
– Endianness does not effect the ordering of items
in a data structure
– No general consensus as to which is “best”
» Little endian: Intel X86, Pentium, VAX
» Big endian: S370, Motorola 680x0, RISCs
– No real advantage in one style over the other
» Decision is based on supporting previous
machines in many cases
– Biggest problems:
» Data transfers between machines of
different endianness
Must go though a format conversion
process
» Manipulation of individual bytes (bits) of
multibyte word
EE 4504 Section 7
Addressing Modes
Once we have determined the number of
addresses contained in an instruction, the
manner in which each address field
specifies memory location must be
determined
Want the ability to reference a large range
of address locations
Tradeoff between
– Addressing range and flexibility
– Complexity of the address calculation
Immediate Mode
– The operand is contained within the instruction
itself
– Data is a constant at run time
– No additional memory references are required
after the fetch of the instruction itself
– Size of the operand (thus its range of values) is
limited
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 Direct mode
– The address field of the instruction contains the
effective address of the operand
– No calculations are required
– One additional memory access is required to
fetch the operand
– Address range limited by the width of the field
that contains the address reference
– Address is a constant at run time but data itself
can be changed during program execution
– Some machines use variations of direct
addressing: direct and extended addressing on
the 68HC11 -- 8 and 16-bit addresses
EE 4504 Section 7
Indirect addressing
– The address field in the instruction specifies a
memory location which contains the address of
the data
– Two memory accesses are required
» The first to fetch the effective address
» The second to fetch the operand itself
– Range of effective addresses is equal to 2n,
where n is the width of the memory data word
– Number of locations that can be used to hold
the effective address is constrained to 2k, where
k is the width of the instruction’s address field
Register-based addressing modes
– Register addressing: like direct, but address
field specifies a register location
– Register indirect: like indirect, but address
field specifies a register that contains the
effective address
– Faster access to data, smaller address fields in
the instruction word
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 Displacement or address relative
addressing
– Two address fields in the instruction are used
» One is an explicit address reference
» The other is a register reference
» EA = A + (R)
– Relative addressing
» A is added to the program counter contents
to cause a branch operation in fetching the
next instruction
– Base-register addressing
» A is a displacement added to the contents of
the referenced “base register” to form the
EA
» Used by programmers and O/S to identify
the start of user areas, segments, etc. and
provide accesses within them
EE 4504 Section 7
Indexing
– Essentially the same impact as base addressing
– Our book says that the A field is a memory
address and the referenced register contains the
displacement value that is added to A
» This is not necessarily the case! “Indexing”
as used and defined by Motorola for the
68HC11 is exactly as our author defines
base addressing
– Better distinction of the base and indexing
might be who / what does the reference.
Examples:
» Indexing is used within programs for
accessing data structures
» Base addressing is used as a control
measure by the O/S to implement
segmentation
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Pentium and PowerPC addressing
– Text shows 9 addressing modes for the Pentium
» Range for simple modes (e.g., immediate)
to very complex modes (e.g., bases with
scaled index and displacement)
– The PowerPC, in contrast has fewer, simpler
addressing modes
EE 4504 Section 7
Instruction Formats
The instruction format defines the layout
of instruction word in terms of its
constituent parts
Most basic issue is the instruction length
– Longer instruction lengths permit more
opcodes, addressing modes, addressing ranges,
etc.
– Longer does not imply a significant increase in
functionality, however
– Instruction lengths are equal to the basic
memory transfer data size or a multiple of that
size
» If the memory system retrieves 32 bit
words, instructions should be 32 bits (or 64)
Allocation of bits
– Tradeoff between number of opcodes supported
(rich instruction set) and the power of the
addressing capability
23 EE 4504 Section 7 24
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 PDP-8: 12-bit fixed format PDP-10 36-bit fixed format
– Stressed orthogonality, completeness, and
direct addressing
– Trade off ease of programming with increased
H/W expense

Figure 10.5 PDP-10 instruction format

Figure 10.4 PDP-8 instruction format

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 PDP-11 variable length format PowerPC format
– 16-bit word length minicomputer
– Variable length instructions to provide
flexibility -- more opcodes and memory
addressing modes
» Cost of the flexibility is a significant
increase in the CPU complexity

Figure 10.6 PDP-11 instruction formats Figure 10.8 PowerPC instruction formats
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 Summary

In this section, we have looked at the

instruction set of the machine
– Content
» types of information contained in them
» Functional completeness
– Addressing in instructions
» Number of addresses included and the
impact on the program
» Addressing modes -- how is the effective
address determined
– Instruction format
» Size and amount allocated to different fields
» Fixed and variable formats
» Complexity

EE 4504 Section 7 29

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