VHDL Introduction

Dr.Ravi Sindal
Professor,Deptt of E&TC
IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore

What is VHDL?
A hardware description language
Starting point: A VHDL model
Destination: A hardware chip

Dr.Ravi Sindal,IET,DAVV,Indore

VHDLs History
Very High Speed Integrated Circuit (VHSIC)
Program
Launched in 1980
Aggressive effort to advance state of the art
Object was to achieve significant gains in VLSI
technology
Need for common descriptive language
$17 Million for direct VHDL development
$16 Million for VHDL design tools

Dr.Ravi Sindal,IET,DAVV,Indore

VHDLs History (Cont.)

In July 1983, a team of Intermetrics, IBM and Texas
Instruments were awarded a contract to develop VHDL
In August 1985, the final version of the language under
government contract was released: VHDL Version 7.2
In December 1987, VHDL became IEEE Standard 10761987 and in 1988 an ANSI standard
In September 1993, VHDL was restandardized to clarify
and enhance the language
VHDL has been accepted as a Draft International
Standard by the IEC
Dr.Ravi Sindal,IET,DAVV,Indore

Gajski and Kuhns Y Chart

Architectural

Behavioral

Structural

Algorithmic
Systems

Functional Block

Processor
Hardware Modules

Algorithms
Logic
ALUs, Registers
Register Transfer
Circuit Gates, FFs
Logic
Transistors
Transfer Functions
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Dr.Ravi Sindal,IET,DAVV,Indore
Physical/Geometry

VHDL
VHDL is a Hardware Description Language.
Over the years, HDLs have evolved to help electronic designers
in the following tasks a) Describing digital systems
b) Modeling digital systems
c) Designing digital systems
The VHDL language can be used with several goals in mind i) To synthesize digital circuits
ii) To verify and validate digital designs
iii) To generate test vectors to test circuits
iv) To simulate circuits
Dr.Ravi Sindal,IET,DAVV,Indore

VHDL as Integrated Language

VHDL can be regarded as an Integrated
amalgamation of following Languages.

Sequential Language+
Concurrent Language+
Net-List Language+
Timing Specification+
Waveform generation Language
Dr.Ravi Sindal,IET,DAVV,Indore

VHDL Provides

Portability
Compatibility across vendors
Code reuse
Distributed design
Reliable design process
Minimized design time and cost

Dr.Ravi Sindal,IET,DAVV,Indore

Additional Benefits of VHDL

Allows for various design methodologies
Provides technology independence
Describes a wide variety of digital hardware
Eases communication through standard language
Allows for better design management
Provides a flexible design language
Has given rise to derivative standards :
WAVES, VITAL, Analog VHDL

Dr.Ravi Sindal,IET,DAVV,Indore

Putting It All Together

Package

Generics

Architecture

Concurrent
Statements

Ports

Entity

Architecture

Concurrent
Statements

Architecture

Process

Dr.Ravi Sindal,IET,DAVV,Indore

Sequential Statements

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Inference
VHDL is a hardware description
language not a programming language!
Our aim is to synthesize VHDL models
into real hardware circuits
The synthesis tool will infer a hardware
architecture from the VHDL model
When writing a VHDL model always
think of the hardware inferred from it
Dr.Ravi Sindal,IET,DAVV,Indore

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