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Published in IET Renewable Power Generation
Received on 15th November 2013
Revised on 14th March 2014
Accepted on 6th May 2014
doi: 10.1049/iet-rpg.2013.0365

ISSN 1752-1416

Modelling and analysis of modular multilevel

converter for solar photovoltaic applications to
improve power quality
Albert Alexander1, Manigandan Thathan2
1

Department of EEE, Kongu Engineering College, Perundurai, Tamil Nadu 638 052, India
Department of EEE, P.A. College of Engineering and Technology, Pollachi, Tamil Nadu 642 002, India
E-mail: ootyalex@gmail.com

Abstract: The design of control circuit for a solar fed cascaded multilevel inverter to reduce the number of semiconductor
switches is presented in this study. The design includes binary, trinary and modied multilevel connection (MMC)-based
topologies suitable for varying input sources from solar photovoltaics (PV). In binary mode, 2Ns +1 1 output voltage levels
are obtained where Ns is the number of individual inverters. This is achieved by digital logic functions which includes
counters, ip-ops and logic gates. In trinary mode, 3Ns levels are achieved by corresponding look-up table. MMC intends
design in both control and power circuits to provide corresponding output voltage levels by appropriate switching sequences.
Hence to obtain a 15-level inverter, the conventional method requires 28 switches and in binary mode 12 switches are
needed. In trinary mode with the same 12 switches, 27 levels can be obtained whereas in MMC only 7 switches are
employed to achieve 15 levels. The advantage of these three designs is in the reduction of total harmonic distortion by
increasing the levels. Simulations are carried out in MATLAB/Simulink and comparisons were made. All the three topologies
are experimentally investigated for a 3 kWp solar PV plant and power quality indices were measured.

Introduction

Multilevel inverter provides a suitable solution for medium

and high power systems to synthesise a output voltage
which allows a reduction of harmonic content in voltage
and current waveforms. Multilevel refers to the multiple
connections of individual inverters termed as stages to
provide the output voltage with required levels. Increasing
the number of levels will result in the reduction of
harmonic distortion. The three topologies such as ying
capacitor (FC), neutral point clamped (NPC) and cascaded
multilevel inverters (CMLIs) are preferred for various
applications depending upon its structure and modulation
algorithms. Among the three topologies, CMLI is highly
preferred for the interconnection of renewable energy
systems because of the advantages such as absence of
voltage unbalance problem, possible elimination of DCDC
boost converter, adaptive at low switching frequency and
absence of clamping capacitors and diodes.
Solar photovoltaic (PV) fed CMLI is dealt in various
literatures, but it intends for low voltage and low level
congurations. Pulse-width modulation (PWM) technique
for a 5-level CMLI [12] and 7-level CMLI [3] for PV
system is addressed which requires boost converter,
auxiliary circuitry and multiple reference signals for pulse
generation. A 5-level current CMLI for a single phase grid
connected PV system given in [4] requires the redesign of
LC lter to reduce the inductive and resistive losses for
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higher power levels. The three control loop maximum

power point (MPP) for a 5-level inverter proposed in [5]
employs an output transformer between inverter and grid.
Inspite of reducing the harmonic distortions while
increasing the levels, CMLI requires more number of
semiconductor switches which has to be reduced for
minimising switching loss, cost, complexity and space.
Series connection of multilevel inverters introduced in [6]
restricts its use in high power applications because of the
necessity of changing the voltage polarity in every half
cycle and also the switches with different ratings are
required. A detailed look-up table is required for the
method proposed in [7] which consists of series connection
of a high-voltage NPC and a low-voltage conventional
inverter. A 5-level inverter with four DC sources
comprising two numbers of 2-level and 3-level inverters is
proposed in [8]. The drawback of this method is that in
conventional inverters upto 9 level can be generated with
the same number of power supplies. Bidirectional switches
with voltage and current blocking capability for the
reduction of switches is proposed in [911] where each
bidirectional switch requires a separate gate drive circuit
which increases the power loss.
In this paper, a digital logic control circuit is proposed for a
solar fed CMLI to achieve higher levels with reduced number
of switches without the requirement of bidirectional switches,
lter components, detailed look-up tables and output
transformers. The techniques include binary, trinary and
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Fig. 1 Three stage inverter power circuit

modied multilevel connections (MMCs) to achieve 15

level and 27 level, respectively. Fig. 1 shows the three stage
CMLI power circuit used to achieve 15 level by binary
mode using digital switching technique comprises of
counters and logic functions. The same power circuit is
used to achieve 27 level by trinary mode using embedded
controller. In certain literature, voltage balancing, ultra
capacitors, PWM switching and transformers are required
which will be the cause for the increase in cost and
manufacturing problems thereby not desirable for motor
drive applications [1214]. In MMC, a 15 level is achieved
with the single stage inverter by addition of input voltages
using the embedded controller based on the proposed
switching sequence. The comparison of three methods with
the existing techniques are analysed and experimentally
veried.
This paper is organised as follows: Section 2 presents the
proposed logic circuit design and Section 3 exhibits the
simulation results and comparative analysis. Section 4
presents the experimental results and Section 5 gives the
nal conclusions.

In conventional approach, PWM techniques are used by the

comparison of reference and carrier signals to provide the
required gating signals for the inverter switches. The number
of output voltage levels obtained from this approach is given
in the following equation
(1)

where m denotes the output voltage levels and Ns is the

individual inverter stages. The number of switches (l )
IET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888
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l = 2(m 1)

(2)

For the implementation of 15-level CMLI, the number of

switches required is 28 with seven individual inverter
stages. In addition to the 28 switches, 182 clamping diodes
in case of NPC or diode clamped multilevel inverter and 91
balancing capacitors in case of FC type multilevel inverter
along with 14 DC bus capacitors are needed to achieve
15-level output. The proposed paper deals with the following
topologies for the reduction of switches. Increasing the
number of levels will subsequently reduce the harmonic
distortion which in turn improves the power quality.
2.1

Binary mode

In binary mode operation, the number of levels which can be

achieved for the given set of inverter stages is given in the
following equation
m = 2Ns +1 1

Switching strategies

m = 2Ns + 1

required to achieve m levels is given in the following equation

(3)

Hence to obtain a 15-level output, only three inverter stages

are required with 12 switches. To achieve this, a switching
circuit with the control strategy incorporating digital logic
functions is implemented for the solar fed CMLI. The three
inverter stages are fed from varying solar PV input source.
The input voltages are scaled to the power of 2 in order to
achieve the output voltage in the range of 2Ns which can be
made by possible by binary counters. An incremental and
descended operator is required to achieve the condition
2Ns + 1 1 at the output level. For the circuit shown in
Fig. 1, during the positive half cycle the switches S1, S5
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Table 1 ON/OFF states for three stage 15-level inverter
Positive half cycle (10 ms)
INV1

+
+
+
+
+
+
+
+

Negative half cycle (10 ms)

INV2

INV3

Vo

INV1

INV2

INV3

Vo

+
+

+
+
+
+

+
+

+
+

48
96
144
192
240
288
336
336
288
240
192
144
96
48

+
+
+
+
+
+
+
+

+
+

+
+
+
+

+
+

+
+

48
96
144
192
240
288
336
336
288
240
192
144
96
48

Fig. 2 Block diagram of the proposed logic circuit

Any number of levels can be achieved with this

methodology by only adding the counters as accordance to
the number of inverter stages and control logic functions.
2.2

and S9 are in ON condition and during negative half cycle S3,

S7 and S11 are in ON condition. The conduction period for
each half cycle is xed at 10 ms which will determine the
output frequency of the inverter as 50 Hz.
The sequence shown in Table 1 gives the switching pattern
to attain the desired voltage levels. INV1, INV2 and INV3
specify the three inverter stages and Vo is the output
voltage. + and denote the ON and OFF condition
of the switches. The sequence + to + + + in the
positive half cycle shows the conduction period is from 0
to 90 and + + + to + from 90 to 180. The
similar condition holds for negative half cycle from 180 to
270 and 270 to 360. The switches present in the CMLI
are intended to operate based on the switching sequence
enlisted in the truth table.
Fig. 2 shows the block diagram for the implementation of the
binary mode. The three stage inverter requires Ns + 2 (3 + 2 = 5)
bit counters which acts as an up counter. The combinational
logic circuit makes the three bits (Q1, Q2 and Q3) to move
in forward direction during the rst half of the positive half
cycle and similarly in reverse direction during second half
of the positive half cycle. The same condition is repeated in
both half of the negative half cycle. The bits (Q1, Q2 and
Q3) are modied by Q4 and Q4, where Q4 is used to
control the incremental operation in the rst half of positive
or negative half cycles and Q4 is used for the decrement
operation in the latter half of positive or negative half cycles.
The pulse separation block comprises of bits Q5 and Q5 to
separate the pulses requires for both positive and negative
half cycles and also controlling other bits in the circuit.

Trinary mode

In trinary mode operation, the number of levels which can be

achieved for the given set of inverter stages is given in the
following equation
m = 3Ns

(4)

With the three inverter stages 27 levels can be obtained with

only 12 switches. To achieve this, rather than a digital logic
functions used in binary mode, an embedded controller is
proposed without the utlilisation of transformers [15] and
complicated algorithms [16]. In this approach, the circuit
shown in Fig. 1 is considered whose input voltages are
scaled to the power of 3. Table 2 illustrates the switching
sequence for the switches S1S12 to obtain 13-level output
during the positive half cycle and in negative half cycle the
same sequence is rotated by an angle of 90 to achieve the
remaining 13 level. By including level zero, the desired 27
levels will be achieved.
2.3

Modied multilevel connections

In the above two approaches, the modication is realised in

control circuit of CMLI to achieve 15 and 27 levels with
three inverter stages. In this approach, the modication is
made in both control circuit and predominately in power
circuit to obtain 15 levels with only seven switches. Fig. 3
shows the circuit diagram of MMC approach where the
input scaling is not mandatory. The addition of diode and

Table 2 ON/OFF states for three stage 27 level

Level
1
2
3
4
5
6
7
8
9
10
11
12
13

80

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

S11

S12

1
0
1
1
0
1
1
0
1
1
0
1
1

0
1
1
0
1
1
0
1
1
0
1
1
0

0
1
0
0
1
0
0
1
0
0
1
0
0

1
0
0
1
0
0
1
0
0
1
0
0
1

1
1
1
1
0
0
0
1
1
1
1
1
1

1
0
0
0
1
1
1
1
1
1
0
0
0

0
0
0
0
1
1
1
0
0
0
0
0
0

0
1
1
1
0
0
0
0
0
0
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1
1
1
1
1
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Fig. 3 Single stage 15-level inverter power circuit

The comparison of switches required with all the three

methods proposed is given in Table 4.

capacitor (1 nF) is to normalise the output within the given

interval. Table 3 shows the switching sequence to achieve
the 15-level output. Based on the table, the inverter circuit
(T1T4) is in ON condition at all the levels, but the input
switches (S1S3) are controlled in such a way that to obtain
the required output voltage.
Let the PV array inputs be V1V3. During the level 1, V1
alone is given as input to the inverter and V2, V3 in OFF
condition. Similarly the 15 level is achieved by controlling
the ON/OFF status of the input voltages. The remaining 7
level from the truth table will be obtained by controlling the
sequence in reverse direction.

3
3.1

0
1
2
3
4
5
6
7

S1

S2

S3

T1

T2

T3

T4

Vo

0
1
0
1
0
1
0
1

0
0
1
1
0
0
1
1

0
0
0
0
1
1
1
1

0
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
1
1
1
1
1
1
1

0
48
96
144
192
240
288
336

Modelling of solar PV panel

The simulation and the corresponding harmonics analysis for

all the three topologies are carried out in MATLAB/Simulink.
The model of solar PV panel is required which serves as the
input for the proposed inverter. In most of the literature based
on solar PV fed inverter, the input is given from the DC
supply and analysis were made [17] and also most of the
solar PV models proposed tends to the estimation of its
characteristics and MPP tracking [1820]. Hence a model
suitable for CMLI-based application is required which also
considers the variations in irradiance and temperature [21].
A solar PV panel is modelled by the interconnection of
solar cells in series and parallel to achieve the required
rating of 48 V, 7 A. Each solar cell of rating (0.5 V, 7 A)
with 96 numbers is connected in series at standard test
conditions of 1000 W/mm2 and 25C. With the rating of the
panel given in Table 6, the modelling is made and P V
and I V characteristics are plotted as shown in Fig. 4.

Table 3 Switching sequence for 15-level inverter with MMC

Level

Simulation and results

Table 4 Comparison of switches

No. of stages

No. of switches

1
2
3
4
5
6
7

4
8
12
16
20
24
28

No. of levels
Conventional

Binary

Trinary

MMC

3
5
7
9
11
13
15

3
7
15
31
63
127
255

3
9
27
81
243
729
2187

15 achieved with only 7 switches

Table 5 Comparison of THD for the solar PV fed CMLI

Stages

1
2
3
4
5
6
7

Voltage THD (%)

Current THD (%)

PWM

Binary

Trinary

MMC

PWM

Binary

Trinary

MMC

52.66
37.77
26.51
17.15
11.53
14.36
15.25

42.09
23.56
16.22
15.48
12.93
12.63
12.37

10.70
11.37
11.77
11.76
12.02

5.55

26.34
20.43
13.70
6.92
2.57
5.16
6.48

26.95
26.49
20.08
20.94
21.64
22.81
21.60

7.71
8.66
9.00
11.96
11.95

8.14

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Fig. 4 P V and I V characteristics

a Powervoltage
b Currentvoltage characteristics of the solar array

The equations corresponding to the solar cell model is given

in the following equations
I = I ph K1 K2 (V + 1Rs )/Rp

(5)


K1 = Is e(V +1Rs )/(N Vt ) 1



and K2 = Is2 e(V +1Rs )/(N 2Vt ) 1

(6)

where

where Is and Is2 are the diode saturation currents, Vt is the

thermal voltage, N and N2 are the diode emission
coefcients and Iph is the solar generated current given in
the following equation
I ph = Ir(I ph0 /Ir0)

(7)

where Iph0 is the measured solar generated current for

irradiance Ir0. In addition, the change in the output voltage
based on partial shaded condition of the solar PV is also
considered for a 15-level CMLI which is shown in Fig. 5.
According to this gure, based on the variations in the
irradiance and temperature at solar PV, the output voltage
of the inverter obtained gets varied but the level maintains
the same. The real time monitoring for the solar PV with
respect to its radiation is analysed for all the months and
based on its inference the modelling is made after knowing
the variation of irradiance for the given region.

3.2

Binary mode

The input to the three inverter stages are to be scaled in the

power of 2 as 48, 96 and 192 V to achieve the output
voltage of 326 Vp. Fig. 6 shows the proposed simulation
block of the control circuit which consists of counters,
combination circuit and pulse separation circuit. The
clock signal is given as the input to the ve bit
asynchronous counter for the movement of bits suitable
for positive and negative half cycles as according to the
truth table. At logic functions, the pulses are separated and
given to the inverter switches. Fig. 7 shows the 15-level
output voltage waveform achieved from three stage
inverter and its corresponding FFT (fast Fourier transform)
analysis.
3.3

Trinary mode

The input to the three inverter stages are to be scaled in the

power of 3 as 24, 72 and 216 V to achieve the output
voltage of 312 Vp. A programmable pulse generator is used
which will receive the switching sequence as per the truth
table from embedded controller and fed it to the switches
through repeating sequence block. Fig. 8 shows the
output voltage waveform and its corresponding harmonic
spectrum.
3.4

Modied multilevel connection

In this method, the embedded-based controller is used for

providing the gating signals based on the switching

Fig. 5 Solar PV with partial shaded condition for a 15-level CMLI

a Variation of panel irradiance
b 15-level output voltage waveform
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Fig. 6 Digital switching circuit for 15-level CMLI

Fig. 7 15-level output voltage waveform achieved from three stage inverter
a 15-level output voltage waveform
b FFT analysis for three stage 15-level CMLI
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Fig. 8 Output voltage waveform and its corresponding harmonic spectrum

a 27-level output voltage waveform
b FFT analysis for three stage 27-level CMLI

sequence according to the addition of input voltages. The

input voltages are 48, 96 and 192 V. Fig. 9 shows the
output voltage waveform and its corresponding harmonic
spectrum.
Table 5 shows the comparison of power quality
improvement pertaining to the reduction of voltage total
harmonic distortion (THD). As current THD is also
equally important, its values are noted for RL load (L =
100 mH, R = 100 ) [22]. All the works are implemented
with the input solar PV panel and output voltage
requirement of 230 Vrms with appropriate scaling of
input voltage and setting inverter output frequency = 50 Hz.
In
developing
PWM-based
technique,
unipolar
switching with single carrier is used with switching
frequency of 1 kHz.
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Experimental results

The three topologies are implemented separately and the

power quality analyses were made. The design was made to
provide 230 Vrms, 50 Hz AC supply as much of the
domestic loads operates in this system. A 3 kWp solar PV
plant shown in Fig. 10 is installed which comprises of 28
panels of each 115 Wp. The specication of the entire
hardware is listed in Table 6. In binary mode the input
voltage are in the range of 48, 96 and 192 V (48 V scaled
in power of 2), respectively. This is achieved by the series
connection of 12 V battery in four numbers. Hence three
separate input sources are designed to achieve the output of
336 Vp (peak voltage). The power circuit of 15-level CMLI
consists of 12 number of MOSFET.
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Fig. 9 Output voltage waveform and its corresponding harmonic spectrum

a 15-level output voltage waveform
b FFT analysis for one stage 15-level CMLI

Fig. 10 3 kWp solar plant

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Table 6 Hardware design Specifications
Solar panel descriptions
model
Pmpp
voc, isc
vpm, ipm
max system voltage
tolerance at peak power
no. of panels
total power
CCs
make
V I rating
no. of CC
Battery bank
make
voltage, ampere hour
no. of batteries
Hardware description
switch
no. of switches
controller
Measuring instruments
oscilloscope
power quality analyser

Solectric 9000
115 Wp
21.2 V, 7.4 A
16.5 V, 6.95 A
540 V
5%
28
3220 Wp
Sukaam
48 V, 10 A
7
EXIDE 6LMS100 L
12 V, 100 Ah
28
MOSFET IRF840
12 (12, 27 level) and 7 (15 level)
ATMEGA 16AVR
Tektronix
WT 3000 make: Yokogawa

The control circuit consists of CD4520 counters, timer IC

555, buffer IC and logic gates to perform the actions of
combinational and pulse separation circuit. The entire
hardware setup is shown in Fig. 11a. The input from the
solar PV is given to the battery through charge controller
(CC). Input to the inverter is driven through the battery. As
the proposed technique is application specic suitable to
rural areas, a standalone PV system with battery storage is
taken into consideration. This method can also be
implemented without the battery as grid connected system
where the same output voltage waveform can be achieved
for the given inverter stages. The control terminal includes
the separate input pairs along with the switchgear devices
for the input side protection. The output voltage waveform
for a three stage 15-level inverter is shown in Fig. 12a and

the corresponding harmonic analysis made in WT 3000 is

shown in Fig. 12b. The harmonic content is measured upto
20th order in both simulation and hardware. The THD
obtained in this mode is 15.4%.
The circuit shown in Fig. 11a is also used to achieve
27-level output in trinary mode. Here the input to the
inverter is in the range of 24, 72 and 216 V (24 V scaled
in the power of 3). The control circuit comprises of single
chip controller embedded with the switching sequence
listed in Table 2. The output voltage waveform of three
stage 27-level CMLI in trinary mode is shown in Fig. 13a
and its harmonic analysis is shown in Fig. 13b. The THD
obtained through trinary mode is 13.68%.
In MMC, only one inverter shown in Fig. 11b is used
where the input to the inverter are in the range of 48, 96
and 192 V, respectively. Across the each input side, three
switches are connected whose switching action is controlled
and monitored by the single chip controller. The addition of
input voltage is made appropriately by turning the switches
S1S2 as per the sequence. The switches T1T4 form the
full bridge inverter circuitry. The output voltage waveform
of a one stage 15 level is shown in Fig. 14a and the
corresponding harmonic analysis is given in Fig. 14b. The
THD obtained in this mode is 5.89%.
Based on the results, it is found that by adopting these
topologies increased level CMLI can be obtained with
reduced number of semiconductor switches. In addition, the
harmonic distortions are summarily reduced in both
simulation and hardware implementations. Earlier works are
reported with the implementation at low power with Vp of
150 [6], 15 [22], 60 [10], 10 [18] and 70 V [23] whereas
the proposed method implemented with 336 Vp. In
addition, to achieve the 15 level output the number of
switches required in existing works are 19 [7], 14 [24], 16
[25] and 36 [26] whereas only 12 or 7 switches are required
in the proposed methodology. For 27-level methodology in
existing works requires transformers at the input and output
end of the inverter and implemented with Vp of 150 and
104 V [1213] but the proposed method does not requires

Fig. 11 Experimental setup for

a Three stage 15-level CMLI
b One stage 15-level CMLI
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Fig. 12 Output voltage waveform for a three stage 15-level inverter

a 15-level output voltage waveform
b Harmonic analysis using WT 3000

Fig. 13 Output voltage waveform of three stage 27-level inverter

a 27-level output voltage waveform
b Harmonic analysis using WT 3000

Fig. 14 Output voltage waveform of a single stage 15 level inverter

a 15-level output voltage waveform
b Harmonic analysis using WT 3000
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transformers and also implemented for 312 Vp. During the
partial shaded condition, the required voltage levels will be
achieved with quiet reduction in voltage peak which in turn
is compensated by a battery storage system.

Conclusions

The power quality improvement for a solar fed CMLI with

reduced number of semiconductor switches is investigated
in this paper. The required 15-level output is achieved with
only 12 switches in binary mode and 7 switches in MMC
mode. In addition, 27-level output is obtained with 12
switches through trinary mode. The mathematical model for
solar PV is carried out which is considered as the input to
the inverter stages. A detailed simulation study is carried
out for various levels and comparison has been made. A 3
kWp solar PV fed CMLI is implemented for all the three
topologies and harmonics analysis was made. Based on the
observations, the proposed method provides the multiple
advantages which include reduced THD, less cost, simple
design, minimum computational complexity and the
absence of transformers, boost converters, detailed look-up
table and lter circuit. Moreover, these methods are much
suitable for standalone/grid interacted PV systems to
improve power quality.

Acknowledgments

The authors acknowledge and thank the Department of

Science and Technology (Government of India) for
sanctioning the research grant for the project titled, Design
and Development of Multilevel Inverters for Power Quality
Improvement in Renewable Energy Sources (Ref.No.DST/
TSG/NTS/2009/98)
under
Technology
Systems
Development Scheme for completing this work.

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IET Renew. Power Gener., 2015, Vol. 9, Iss. 1, pp. 7888

doi: 10.1049/iet-rpg.2013.0365