Code No: 26023 RR Set No.

2
III B.Tech II Semester Supplimentary Examinations,February 2010
V L S I DESIGN
Common to Electronics And Telematics, Electronics And Communication
Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. Implement 2-bit comparator using PROM. [16]

2. (a) Explain with neat sketches the Drain and Transfer characteristics of p-channel
enhancement MOSFET.
(b) With neat sketches explain the current variation of CMOS inverter with its
input voltage. [10+6]
3. (a) With neat sketches explain automatic diffusion mechanism.
(b) Explain clearly about different types of packing methods used in IC fabrica-
tion. [8+8]
4. Design a stick diagram for the PMOS logic shown below [16]

Y = (A + B).C

5. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 3, If n-channel sheet resistance is 104 Ω per square. [16]

Figure 3
6. (a) With neat sketches explain CMOS fabrication using n-well process.
(b) Explain how capacitors are fabricated in CMOS process. [10+6]
7. Design a layout diagram for the PMOS logic shown below [16]

Y = (AB) + (CD)

1
Code No: 26023 RR Set No. 2
8. Mention about various types of simulators used in ASIC design flow and clearly
discuss about the significance of each simulator. [16]

?????

2
Code No: 26023 RR Set No. 4
III B.Tech II Semester Supplimentary Examinations,February 2010
V L S I DESIGN
Common to Electronics And Telematics, Electronics And Communication
Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain with neat sketches the Drain and Transfer characteristics of p-channel
enhancement MOSFET.
(b) With neat sketches explain the current variation of CMOS inverter with its
input voltage. [10+6]

2. Mention about various types of simulators used in ASIC design flow and clearly
discuss about the significance of each simulator. [16]

3. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 3, If n-channel sheet resistance is 104 Ω per square. [16]

Figure 3
4. (a) With neat sketches explain CMOS fabrication using n-well process.
(b) Explain how capacitors are fabricated in CMOS process. [10+6]

5. Design a layout diagram for the PMOS logic shown below [16]

Y = (AB) + (CD)

6. Implement 2-bit comparator using PROM. [16]

7. Design a stick diagram for the PMOS logic shown below [16]

Y = (A + B).C

3
Code No: 26023 RR Set No. 4
8. (a) With neat sketches explain automatic diffusion mechanism.
(b) Explain clearly about different types of packing methods used in IC fabrica-
tion. [8+8]

?????

4
Code No: 26023 RR Set No. 1
III B.Tech II Semester Supplimentary Examinations,February 2010
V L S I DESIGN
Common to Electronics And Telematics, Electronics And Communication
Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. Mention about various types of simulators used in ASIC design flow and clearly
discuss about the significance of each simulator. [16]

2. (a) Explain with neat sketches the Drain and Transfer characteristics of p-channel
enhancement MOSFET.
(b) With neat sketches explain the current variation of CMOS inverter with its
input voltage. [10+6]

3. Implement 2-bit comparator using PROM. [16]

4. Design a layout diagram for the PMOS logic shown below [16]

Y = (AB) + (CD)

5. Design a stick diagram for the PMOS logic shown below [16]

Y = (A + B).C

6. (a) With neat sketches explain CMOS fabrication using n-well process.
(b) Explain how capacitors are fabricated in CMOS process. [10+6]

7. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 3, If n-channel sheet resistance is 104 Ω per square. [16]

Figure 3

5
Code No: 26023 RR Set No. 1
8. (a) With neat sketches explain automatic diffusion mechanism.
(b) Explain clearly about different types of packing methods used in IC fabrica-
tion. [8+8]

?????

6
Code No: 26023 RR Set No. 3
III B.Tech II Semester Supplimentary Examinations,February 2010
V L S I DESIGN
Common to Electronics And Telematics, Electronics And Communication
Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) With neat sketches explain CMOS fabrication using n-well process.
(b) Explain how capacitors are fabricated in CMOS process. [10+6]
2. Implement 2-bit comparator using PROM. [16]
3. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 3, If n-channel sheet resistance is 104 Ω per square. [16]

Figure 3
4. Design a stick diagram for the PMOS logic shown below [16]
Y = (A + B).C

5. Mention about various types of simulators used in ASIC design flow and clearly
discuss about the significance of each simulator. [16]
6. (a) With neat sketches explain automatic diffusion mechanism.
(b) Explain clearly about different types of packing methods used in IC fabrica-
tion. [8+8]
7. Design a layout diagram for the PMOS logic shown below [16]
Y = (AB) + (CD)

8. (a) Explain with neat sketches the Drain and Transfer characteristics of p-channel
enhancement MOSFET.

7
Code No: 26023 RR Set No. 3
(b) With neat sketches explain the current variation of CMOS inverter with its
input voltage. [10+6]

?????