Code.

No: 44018
R07 SET-1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II .B.TECH –II SEM SUPPLEMENTARY EXAMINATIONS JANUARY- 2010
SWITCHING THEORY AND LOGIC DESIGN
(COMMON TO ECE, ETM)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---

1.a) Obtain the 1's and 2's complements of the following binary numbers.
(i) (10001111) 2
(ii) (10001111)2
b) (i) (4350) 5 = ( )2
(ii) (11010011)2 = ( )16
(iii) (552) 6 = ( )8
c) Explain the advantages of 2’s complement. [4+8+4]

2.a) Express the Boolean function F=A + B'C in a sum of min terms form.
b) Express the Boolean function F= x y + x' z in a product of max terms form. [8+8]

3. Simplify the following Boolean functions using five-variable maps.

a) F(A,B,C,D,E) = Σ(0,1,4,5,16,17,21,25,29)
b) F = A'B'C'E' + A'B'C'D'¹+ B'D'E' + B'C'D' + CDE' + BDE' [8+8]

4.a) Design a combinational circuit with three inputs and one output.
The output is 1 when the binary value of the inputs is less than 3.
The output is 0 otherwise.
b) Draw the block diagram of a BCD adder. [12+4]

5.a) List out and explain capabilities and limitations of threshold gate.
b) Determine whether the following function
f (X1, X2, X3, X4) = Σ (0,1,3,4,5,6,7,12,13)
is a threshold function ,and if it is ,find a weighing –threshold vector. [8+8]

6. Explain sequential circuits of the following with an example.

(i) Synchronous
(ii) Asynchronous
(iii) Pulse mode
(iv) Level mode. [16]
7.a) Compare the Mealy machine and Moore machines.
b) Convert the following Mealy machine into Moore Machine. [8+8]

PS NS, Z
x=0 x =1

A C,0 B,1
B A,1 D,0
C B,1 A,1
D D,1 C,0

8.a) Define an ASM chart.

b) What are the basic elements of ASM chart?
c) Write short notes on ASM block. [4+6+6]

******
Code.No: 44018
R07 SET-2
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II .B.TECH –II SEM SUPPLEMENTARY EXAMINATIONS JANUARY- 2010
SWITCHING THEORY AND LOGIC DESIGN
(COMMON TO ECE, ETM)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---

1.a) Find the 9's and 10's complements of the following decimal numbers.
(i) (99631899)10
(ii) (94915376)10
(iii) (92466050)10
(iv) (99669966)10
b) Perform the following operations
(i) (1000011) 2 – (1010100) 2
(ii) By using BCD arithmetic perform (7184) 10 +(5764) 10
(iii) (1111011) 2 % (101) 2
(iv) (101101) 2 x (11101)2 [8+8]

2. Given the Boolean Function.

F = xy'z + x'y'z + w'xy + wx'y + wxy
a) Draw the logic diagram using the original Boolean Expression.
b) Draw the logic diagram from the simplified expression and compare the
total number of gates with the diagram of part (a). [8+8]

3. Simplify the following Boolean function F together with the don’t-care

conditions d, and then express the simplified function in sum of min terms:
F(x,y,z) = Σ (0,1,2,4,5)
d (x,y,z) = Σ (3,6,7) [16]

4.a) Draw and explain the logic diagram of the 4-Bit by 3-Bit binary multiplier.
b) Explain about static harzards. [12+4]

5. For the following switching functions find a minimal threshold –logic

realization.
f(X1, X2, X3, X4) = Σ (2,3,6,710,12,14,15)
f(X1, X2, X3, X4) = Σ (3,5,7,10,12,14,15) [16]

6.a) Design a 4-bit BCD ripple counter with state diagram.

b) Draw the block diagram of a three-decade decimal BCD counter. [12+4]
7. Minimize the following state machine using merge table. [16]

PS NS, Z
x=0 x =1

A E,0 B,0
B F,0 A,0
C E,- C,0
D F,1 D,0
E C,1 C,0
F D,- B,0

8.a) Draw an ASM chart to implement binary multiplier.

b) What are the basic elements of ASM chart? [10+6]

******
Code.No: 44018
R07 SET-3
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II .B.TECH –II SEM SUPPLEMENTARY EXAMINATIONS JANUARY- 2010
SWITCHING THEORY AND LOGIC DESIGN
(COMMON TO ECE, ETM)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---
1. Construct a seven bit error correcting code to represent the decimal
digits by augmenting the Excess-3 code and by using odd_1 parity check. [16]

2.a) State and prove postulates and theorems of Boolean algebra.

b) Draw the logic diagram and list the truth table of the given function.
F = xy + xy' + y'z [8+8]

3. Draw a NAND logic diagram that implements the complement of the following
function
F(A,B,C,D) = Σ (0,1,2,3,4,8,9,12) [16]

4.a) Construct a 4-to-16 line decoder with five 2-to-4 line decoders with enable.
b) Explain about harzard due to subcubes formed of 0 cells. [10+6]

5. Design a combinational circuit using PAL by considering the Boolean

functions.
w(A,B,C)= Σ (2,12,13)
x(A,B,C,D)= Σ (7,8,9,10,11,12,13,14,15)
y(A,B,C)= Σ (0,2,3,4,5,6,7,8,10,11,15)
z(A,B,C)= Σ (1,2,8,12,13) [16]

6. Design a counter with the following repeated binary sequence 0,1,2,4,6 using
D- flipflops. [16]

7. Minimise the following machine using partition method by writing the necessary
steps Involved. [16]

PS NS, Z
x=0 x =1

A E,0 D,1
B F,0 D,0
C E,0 B,1
D F,0 B,0
E C,0 F,1
F B,0 C,0

8. a) Draw an ASM chart to implement weighing machine.

b) Write an algorithm for the above case. [10+6]
******
Code.No: 44018
R07 SET-4
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
II .B.TECH –II SEM SUPPLEMENTARY EXAMINATIONS JANUARY- 2010
SWITCHING THEORY AND LOGIC DESIGN
(COMMON TO ECE, ETM)
Time: 3hours Max.Marks:80
Answer any FIVE questions
All questions carry equal marks
---

1.a) List out the difference between weighted codes and non weighted code.
b) Represent the decimal number 11110010 in
(i) BCD (ii) Excess-3 code (iii) Gray code [8+8]

2.a) Express the complement of the following functions in sum of min terms.
i) F(A ,B,C,D) = Σ (0,2,6,11,13,14)
ii) F(x,y,z) = Π (0,3,6,7)
b) Show that a positive logic NAND gate is a negative logic NOR gate
and vice versa. [8+8]

3. Simplify the following Boolean functions by first finding the essential

prime implicants.
a) F(w,x,y,z) = Σ (0,2,4,5,6,7,8,10,13,15)
b) F(A,B,C,D) = Σ (0,2,3,5,7,8,10,11,14,15) [8+8]

4. Design a priority encoder with n input lines and log2 (n) output lines
when n=8. [16]

5. Implement the following four Boolean functions with a PLA.

F1(A,B,C)= Σ (0,1,2,4)
F2(A,B,C)= Σ (0,5,6,7)
F3(A,B,C)= Σ (1,3,4,5)
F4(A,B,C)= Σ (2,5,6,7) [16]

6. Construct J-K flip-flop using a D flip-flop, a 2-to-1-line multiplier

and an inverter. [16]

7.a) List out capabilities and limitations of finite state machines.

b) Define each of the following one with an example.
(i) Synchronous sequential machine
(ii) k-equivalence. [8+8]

8.a) Draw an ASM chart to implement BCD counter.

b) Write short notes on ASM block. [10+6]

******