UNIVERSITY OF MORATUWA

Faculty of Engineering
Department of Electronic & Telecommunication Engineering
B.Sc. Engineering
Semester 2 Examination
EN 1802 BASIC ELECTRONICS
Time Allowed: 2 Hours

November 2011

INSTRUCTIONS TO CANDIDATES
1. This paper contains 4 questions on 4 Pages.
2. This examination accounts for 70% of the module assessment. Each question carry 25
marks each and marks assigned for each section are included in square brackets.
brackets
3. This is a closed book examination.
4. Answer ALL questions.

This Space is Intentionally Left Blank

Question 1
1.1
1.2

Draw
w the diode characteristics (V
(V-I)) curve and clearly mark the forward biased
region, reversed biased region
region, and the break down region.
[5 Marks]
A photo diode is connected in series with a 10 K resistor as shown in Figure Q1.1.
The photo diode has a reversed biased leakage current of 220 A
A at night time and 100
A at day time. Neglecting the current dra
drawn
wn by the comparator, determine the
comparator threshold level VT to detect day and night.
[10 Marks]

Figure Q1.1
1.3

A 18V zener diode D and a 500 resistor R are connected as shown in Figure
Q1.2. The current through the zener diode (Iz) has to be greater than 1mA for its
proper operation. The maximum power rating of the ze
zener is 486mW.
mW. The load
current is kept at 3mA
mA constant. Find the minimum and the maximum
aximum source voltage
voltag
that ensure the proper operation of the voltage stabilizer.
[10 Marks]

Figure Q1.2
Question 2
2.1
A student wants to design a combinational logic circuit which has 2 input pins A,
and B, 1 select pin S, and 1 output pin Z as shown in Figure Q2.1.. When the select pin
S is set to 0, the student wants the circuit to behave as a XOR gate. If the select pin S is
set to 1, he wants the circuit to behave as an OR gate.

Figure Q2.1
(a) Draw the truth table for the combinational circuit.

[5 Marks]

(b) Write the min term expression for the output Z.

[5 Marks]
(c) Use Karnaugh Map to simplify the combinational logic.
[5 Marks]
(d) Design the combinational circuit using 1 AND gate, 1 XOR gate, and 1 OR gate only.
[5 Marks]
2.2
Design a positive edge D Flip flop using a SR Latch (with EN Pin), a negative edge
detection circuit, and 2 NOT gates only.
[5 Marks]

Question 3
3.1
3.2
3.3

How is a Bipolar Junction Transistor biased? What are the configuration types of a
BJT? Explain one configuration with a suitable diagram(s).
[6 Marks]
What is meant by Q-Point? What is the significance of it and explain how you would
find this?
[5 Marks]
Determine the load line without using characteristic curves
[6 Marks]
2k

4k

+ 6V

3.4

20V

For the circuit given below, answer the following questions: Assume Silicon
Transistor.
(a) If IC= 1.2 mA, what is VCE?
(b) If VCE=11.5 V, what is IC?
24V
+V

220k

4.7k

Q1

[8 Marks]

Question 4
1.
2.

Briefly describe one method of JFET Biasing with suitable diagrams.

Give five comparisons between BJT and a JFET.

Page 3 of 4

[5 Marks]
[5 Marks]

3.
4.

Explain the operation of a N-channel JFET with suitable diagrams(s) and

mathematical expressions.
[6 Marks]
The following JFET has IDSS=11mA and VP=4.4V. Compute ID and VDS when
VGS= -1.2V. Assume that the JFET is biased in the pinch-off region.
18V
+V

2k

Vgs
+

[9 Marks]

Page 4 of 4