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Designing a chip Challenges, Trends, and Latin America Opportunity Victor Grimblatt R&D Group Director ©

Designing a chip

Challenges, Trends, and Latin America Opportunity

Victor Grimblatt

R&D Group Director

© Synopsys 2012

1

SASE 2012

Challenges, Trends, and Latin America Opportunity Victor Grimblatt R&D Group Director © Synopsys 2012 1 SASE

Agenda

Introduction

The Evolution of Synthesis

SoC

IC Design Methodology

New Techniques and Challenges

IP Market, an opportunity for Latin America

© Synopsys 2012

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SoC IC Design Methodology New Techniques and Challenges IP Market, an opportunity for Latin America ©
Introduction
Introduction

© Synopsys 2012

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Introduction © Synopsys 2012 3

Interesting Facts from Cisco

• Last year’s mobile data traffic eight times the size of the entire global Internet in 2000

Global mobile data traffic grew 2.3-fold in 2011, more than doubling for 4 th year in a row

Mobile video traffic exceeded 50% for the first time in 2011

Average smartphone usage nearly tripled in 2011

In 2011, a 4 th generation (4G) connection generated 28x more traffic on average than non-4G connection

Source: Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, 20112016, Feb 14, 2012

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Cisco Visual Networking Index: Global Mobile Data Traffic Forecast Update, 2011 – 2016, Feb 14, 2012

Drives Exploding Need for Bandwidth

and Storage

Bandwidth Increase
Bandwidth Increase

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A Decade of Digital Universe Growth 7.910 Zettabytes 8000 7000 6000 5000 4000 3000 1.2
A Decade of Digital
Universe Growth
7.910
Zettabytes
8000
7000
6000
5000
4000
3000
1.2
2000
Zettabytes
130
1000
Exabytes
0
2005
2010
2015
7.910 Zettabytes 8000 7000 6000 5000 4000 3000 1.2 2000 Zettabytes 130 1000 Exabytes 0 2005
• One zettabyte = stacks of books from Earth to Pluto 20 times (72 billion

One zettabyte = stacks of books from Earth to Pluto 20 times (72 billion miles)

If an 11 oz. cup of coffee equals 1

Source: IBS and Cisco

© Synopsys 2012

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gigabtye, then 1 zettabyte would

have the same volume of the Great Wall of China

Source: IBS and Cisco © Synopsys 2012 6 gigabtye, then 1 zettabyte would have the same

Tomorrow’s World

Reality Augmented Reality Blended Reality

Search Agents Info That Finds You (and networks that know you)

2D 3D Immersive Video Holographics

Medical Mobile Medical Personal Medical

Person to Person Machine to Machine Human Machines

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Mobile Medical  Personal Medical Person to Person  Machine to Machine  Human Machines ©

What the Future Has in Store

What the Future Has in Store © Synopsys 2012 8

© Synopsys 2012

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What the Future Has in Store © Synopsys 2012 8
How Does This Affect Design?
How Does This Affect Design?

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How Does This Affect Design? © Synopsys 2012 9

Megatrends Change Design Requirements

Used to Be… Today It’s… Computing Creating Info Compute Power Connectivity Consuming Info Battery Power
Used to Be…
Today It’s…
Computing
Creating Info
Compute Power
Connectivity
Consuming Info
Battery Power
Business
At your desk
Work
Consumer
Anywhere, anytime
Entertainment

© Synopsys 2012

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Info Battery Power Business At your desk Work Consumer Anywhere, anytime Entertainment © Synopsys 2012 10

Trends Drive Process Migration

35%

30%

25%

20%

15%

10%

5%

0%

Trends Drive Process Migration 35% 30% 25% 20% 15% 10% 5% 0% Last Current Next 31%

Last

Drive Process Migration 35% 30% 25% 20% 15% 10% 5% 0% Last Current Next 31% 13%

Current

Process Migration 35% 30% 25% 20% 15% 10% 5% 0% Last Current Next 31% 13% 4%

Next

31% 13% 4% 32/28nm 22/20nm <20nm
31%
13%
4%
32/28nm
22/20nm
<20nm
20% 13% 6% 5% 5% 3%
20%
13%
6%
5%
5%
3%

250nm

180nm

130nm

90nm

65/55nm

45/40nm

Synopsys Global User Survey, Feb 2012 N = 1290

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3% ≥ 2 5 0 n m 180nm 130nm 90nm 65/55nm 45/40nm Synopsys Global User Survey,

and Increasing Gate Count

50%

45%

40%

35%

30%

25%

20%

15%

10%

5%

0%

>100M, 13%

50-100M, 6%

20-50M, 7%

10-20M, 5%

5-10M, 9%

2-5M, 7%

>100M, 3%

50-100M, 3%

20-50M, 3%

10-20M, 5%

5-10M, 4%

2-5M, 6%

2010

2011

Synopsys Global User Survey, Feb 2012

© Synopsys 2012

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20-50M, 3% 10-20M, 5% 5-10M, 4% 2-5M, 6% 2010 2011 Synopsys Global User Survey, Feb 2012

and Faster Designs

100%

80%

60%

40%

20%

0%

>2GHz 1-2GHz 751MHz-1GHz 501-750MHz 401-500MHz 301-400MHz 201-300MHz 101-200MHz 51-100MHz ≤50MHz
>2GHz
1-2GHz
751MHz-1GHz
501-750MHz
401-500MHz
301-400MHz
201-300MHz
101-200MHz
51-100MHz
≤50MHz

2004

2005

2006

2007

2008

2009

2010

2011

42%

Synopsys Global User Survey, Feb 2012 N = 962

© Synopsys 2012

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≤50MHz 2004 2005 2006 2007 2008 2009 2010 2011 42% Synopsys Global User Survey, Feb 2012

… while requiring aggressive Power Management

400%

350%

300%

250%

200%

150%

100%

50%

0%

Power Management 400% 350% 300% 250% 200% 150% 100% 50% 0% 2010 2011 Synopsys Global User
Power Management 400% 350% 300% 250% 200% 150% 100% 50% 0% 2010 2011 Synopsys Global User

2010

2011

Synopsys Global User Survey, Feb 2012 N = 282

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OtherGlobal User Survey, Feb 2012 N = 282 © Synopsys 2012 14 Back-biasing/Well-biasing Library Variables (e.g.,

Back-biasing/Well-biasing

Library Variables (e.g., multi-channel length libraries)N = 282 © Synopsys 2012 14 Other Back-biasing/Well-biasing Low Vdd Standby State retention MTCMOS/Power gating

Low Vdd StandbyLibrary Variables (e.g., multi-channel length libraries) State retention MTCMOS/Power gating Lower Vdd operation

State retention(e.g., multi-channel length libraries) Low Vdd Standby MTCMOS/Power gating Lower Vdd operation Dynamic

MTCMOS/Power gatinglength libraries) Low Vdd Standby State retention Lower Vdd operation Dynamic Voltage/Frequency Scaling (DVFS)

Lower Vdd operationLow Vdd Standby State retention MTCMOS/Power gating Dynamic Voltage/Frequency Scaling (DVFS) Multi-Corner,

Dynamic Voltage/Frequency Scaling (DVFS)State retention MTCMOS/Power gating Lower Vdd operation Multi-Corner, Multi-Mode (MCMM) optimization Multi-voltage

Multi-Corner, Multi-Mode (MCMM) optimizationLower Vdd operation Dynamic Voltage/Frequency Scaling (DVFS) Multi-voltage domains Multi-Vt leakage optimization Clock

Multi-voltage domainsVoltage/Frequency Scaling (DVFS) Multi-Corner, Multi-Mode (MCMM) optimization Multi-Vt leakage optimization Clock gating

Multi-Vt leakage optimizationDynamic Voltage/Frequency Scaling (DVFS) Multi-Corner, Multi-Mode (MCMM) optimization Multi-voltage domains Clock gating

Clock gatingScaling (DVFS) Multi-Corner, Multi-Mode (MCMM) optimization Multi-voltage domains Multi-Vt leakage optimization

(DVFS) Multi-Corner, Multi-Mode (MCMM) optimization Multi-voltage domains Multi-Vt leakage optimization Clock gating

Design Challenges are Multiplying

Example of 28-nm challenges

Unidirectional Poly (and other RDRs) – Requires separate layouts, verification & test effort. GF and
Unidirectional Poly (and other RDRs)
– Requires separate layouts, verification & test effort. GF and TSMC
have different preferred orientations (N/S v. E/W)
– No poly for local routing
Device segmentation
Limited device sizes, large analog devices broken up into smaller
28 nm is 2X harder than 40 nm
pieces; Increases analog area
28 nm IP – area increases
Complexity
– Approximately 1700 design rule checks at 28nm vs. 700 at 65nm
without circuit innovation
28 nm analog layout
9% larger than 40 nm
due to limitations
on poly area
– 8x the # of corners at 65 v. 28nm
– Lower Vddmin resulting in less design headroom
– Metal resistance doubles from 40 nm to 28 nm
Global versus local Vth variations due to random doping effects
Device Aging
– Must take into account device degradation over time due to
40 nm layout

threshold voltage instability (NBTI/PBTI) and mobility degradation (HCI)

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time due to 40 nm layout threshold voltage instability (NBTI/PBTI) and mobility degradation (HCI) © Synopsys

$M

$M SoC = Software System on a chip HW & SW Development Costs 1 2 3

SoC = SoftwareSystem on a chip

HW & SW Development Costs

1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627
1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627

Months

App-Specific SW

Low-Level SW

OS Support

Design Management

Post-silicon Validation

Masks

Physical Design

RTL Verification

RTL Development

Spec Development

IP Qualification

$2.50

$2.00

$1.50

$1.00

$0.50

$-

Source: IBS, Synopsys

Software is Half the Time to Market For a Typical SoC !

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$1.50 $1.00 $0.50 $- Source: IBS, Synopsys Software is Half the Time to Market For a

And Half the Cost

$175 $150 Software $125 Hardware $100 $75 $50 $25 $0 Cost ($M)
$175
$150
Software
$125
Hardware
$100
$75
$50
$25
$0
Cost ($M)

© Synopsys 2012

90nm (60M)

17

65nm (90M)

45/40nm (130M)

Feature Dimension (Transistor Count)

32/28nm (180M)

Source: IBS and Synopsys, 2011

22/20nm (240M)

(90M) 45/40nm (130M) Feature Dimension (Transistor Count) 32/28nm (180M) Source: IBS and Synopsys, 2011 22/20nm (240M)

Unlike Moore… Software Guys are Pessimists

Page’s Law: 2009 Software gets twice as slow every 18 months.” Wirth’s Law: 1995 Software
Page’s Law: 2009
Software gets twice as slow every
18 months.”
Wirth’s Law: 1995
Software is getting slower more rapidly
than hardware becomes faster. ”

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Wirth’s Law: 1995 Software is getting slower more rapidly than hardware becomes faster. ” © Synopsys

What Can We Do About It?

© Synopsys 2012 19
© Synopsys 2012
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The Evolution of Synthesis
The Evolution of Synthesis

© Synopsys 2012

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The Evolution of Synthesis © Synopsys 2012 20

Placement & Routing

Ronald L. Rivest, Charles M. Fiduccia, Robert M. Mattheyses,

GE & MIT, 1982
GE & MIT,
1982

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Source: GE, 1986

M. Fiduccia, Robert M. Mattheyses, GE & MIT, 1982 © Synopsys 2012 21 S o u

Logic Synthesis

David Gregory, Karen Bartlett, Aart J. de Geus, Gary D.

Hachtel, GE & University of Colorado at Boulder,

1986
1986

22

Karen Bartlett, Aart J. de Geus, Gary D. Hachtel, GE & University of Colorado at Boulder,

© Synopsys 2012

Until Late 80’s

The Implementation Flow Was Quite Straight Forward

There Was Already a “Wall”…

• Schematic Capture Front-End • Timing Simulation
• Schematic Capture
Front-End
• Timing Simulation
• Schematic Capture Front-End • Timing Simulation • Place & Route Back-End • DRC/LVS © Synopsys
• Place & Route Back-End • DRC/LVS
• Place & Route
Back-End
• DRC/LVS

© Synopsys 2012

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• Schematic Capture Front-End • Timing Simulation • Place & Route Back-End • DRC/LVS © Synopsys

Early 90’s

The Relationship Needs Improvements Badly:

“Walls” Now Lead to Iterations, Often Out of Control

Front-End

• RTL Simulation • Logic Synthesis
• RTL Simulation
• Logic Synthesis
of Control Front-End • RTL Simulation • Logic Synthesis • Place & Route Back-End • DRC/LVS
of Control Front-End • RTL Simulation • Logic Synthesis • Place & Route Back-End • DRC/LVS
• Place & Route Back-End • DRC/LVS
• Place & Route
Back-End
• DRC/LVS
Logic Synthesis • Place & Route Back-End • DRC/LVS Sign-Off • Delay Calculation • Timing Simulation

Sign-Off

• Delay Calculation • Timing Simulation
• Delay Calculation
• Timing Simulation

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• Place & Route Back-End • DRC/LVS Sign-Off • Delay Calculation • Timing Simulation © Synopsys

Early 00’s, 130nm, 7+ Metals

PC and Astro+Blast+SilEnsemble The Relationship Matures

Still, Too Many “Walls”, and # of Iterations Too High

• RTL Simulation • Logic, Power & Test Synthesis Front-End • Floorplan • Physical Synthesis
• RTL Simulation
• Logic, Power & Test Synthesis
Front-End
• Floorplan
• Physical Synthesis
Back-End
• Floorplan
• P&R
Sign-Off
• Extraction & STA
• DRC/LVS

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Synthesis Back-End • Floorplan • P&R Sign-Off • Extraction & STA • DRC/LVS © Synopsys 2012

The Evolution Of The Relationship

Convergence !

The Evolution Of The Relationship Convergence ! 2003 90 Nanometers “Interoperability” 2005 65 Nanometers

2003

90 Nanometers “Interoperability”

Convergence ! 2003 90 Nanometers “Interoperability” 2005 65 Nanometers “Correlation” © Synopsys 2012 26

2005

65 Nanometers “Correlation”

© Synopsys 2012

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2005 65 Nanometers “Correlation” © Synopsys 2012 26 2007 45/40 Nanometers “Look Ahead” 2009… 32/28

2007

45/40 Nanometers “Look Ahead”

“Correlation” © Synopsys 2012 26 2007 45/40 Nanometers “Look Ahead” 2009… 32/28 Nanometers “In - Design”

2009…

32/28 Nanometers “In-Design”

“Correlation” © Synopsys 2012 26 2007 45/40 Nanometers “Look Ahead” 2009… 32/28 Nanometers “In - Design”

The Evolution Of The Relationship

Quick Summary

• Late 80’s - Early 90’s. Attempt #1 :

Predict the future based on the past

Wire load models, broken by nanometer wires

• Mid 90’s. Attempt #2 :

Predict the future based on the present

Front-end floorplanning, broken by “Frankenstein flows”

• Late 90’s – Today. Attempt #3 :

Partner to create the future , rather than attempt to predict it

Convergence of synthesis and place & route

But underlying mathematics is different

© Synopsys 2012

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it – Convergence of synthesis and place & route – But underlying mathematics is different ©

Logic Synthesis And Place & Route

A Revolutionary… Evolution : Convergence !

Logic Compiler, ca. 1986

Design Compiler, 2010.03

! Logic Compiler, ca. 1986 Design Compiler, 2010.03 From Equations to Gates, to… Placed and Routable

From Equations to Gates, to… Placed and Routable Gates

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Compiler, ca. 1986 Design Compiler, 2010.03 From Equations to Gates, to… Placed and Routable Gates ©
SoC
SoC

© Synopsys 2012

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SoC © Synopsys 2012 29

What is High-Level Synthesis?

Designer User inputs: • High-level algorithm Intent • Constraints c  a * b 
Designer
User inputs:
• High-level algorithm
Intent
• Constraints
c  a * b  c;
Automation using
High-Level Synthesis
HLS outputs:
• Synthesizable RTL
HLS
• C-model
Results
• RTL testbench
• Scripts for synthesis,
verification and
downstream tools

© Synopsys 2012

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Design technology and methodology

Develop and verify hardware at a higher level of

abstraction

Much smaller code with fewer bugs introduced

Rapid architecture exploration

Automate implementation and verification

Automatic optimizations that equal hand-coded QoR

Eliminate manual RTL coding & verification

Example benefits

2-5X productivity for initial designs

5-10X productivity for design re-use

Increased exploration leading to better results

Multi-million gate designs in weeks vs. months

for design re-use • Increased exploration leading to better results • Multi-million gate designs in weeks

High-Level Synthesis Advantage

Traditional Block Design Algorithm RTL Coding RTL Verification Design Cycle by cycle Spreadsheets For single
Traditional Block Design
Algorithm
RTL Coding
RTL Verification
Design
Cycle by cycle
Spreadsheets
For single architecture only
functional debug
RTL automatically generated
HLS-based Block Design
Better Designs,
Algorithm
High-Level
RTL
Design
Design
Verification
Faster
Faster design at
higher abstraction
Quickly evaluate
multiple architectures
Faster, more automatic model-to-RTL
validation, reduced RTL-level debug
Architecture
Exploration
Implementation
Implementation

© Synopsys 2012

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validation, reduced RTL-level debug Architecture Exploration Implementation Implementation © Synopsys 2012 31

Changing FPGA Design Methodology

Classic FPGA Methodology Top Down Implementation

Best Quality of Results

May not be suitable for largest FPGA designs (long runtimes and large memory

requirements)

“Divide and Conquer”

Top Down Incremental Implementation

Reduced Quality of Results

Shorter runtime -preserve unchanged parts

• “Design Preservation”, block based flows, and Incremental P&R with “SmartGuide

Emerging “Mix and Match”

Bottom Up and Top

Down Flow

Distributed development

Better design preservation and isolation

Design style adjustments needed to achieve optimal timing Quality of Results (e.g. registering module boundaries

style adjustments needed to achieve optimal timing Quality of Results (e.g. registering module boundaries © Synopsys

© Synopsys 2012

Unified RTL Flow for FPGA and SOC

FPGA Synthesis DesignWare IP Synplify Premier/Certify DW Implementation Your IP ASIC Implementation DesignWare
FPGA Synthesis
DesignWare
IP
Synplify
Premier/Certify
DW Implementation
Your IP
ASIC Implementation
DesignWare
Building Blocks
Galaxy
DW Implementation
Common RTL from prototype to production a combination of IP and tools
All DW Building blocks, minPower and Macrocell Blocks are supported in
Synplify Premier and Certify for FPGA-based prototyping

© Synopsys 2012

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and Macrocell Blocks are supported in Synplify Premier and Certify for FPGA-based prototyping © Synopsys 2012

Today’s SOC Designs

Designs are getting larger and larger.

Schedule stays the same or shorter despite the increases in design complexity.

Engineering resources are not increasing to handle this complexity.

How can EDA help manage this complexity?

© Synopsys 2012

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resources are not increasing to handle this complexity. How can EDA help manage this complexity? ©

Many Methods of Designing “SOC Design”…

Similar Approach But End Results Vary …

Final Product Varies

Approach But End Results Vary … Final Product Varies Building Blocks Instructions Instructions 1. Preheat the
Approach But End Results Vary … Final Product Varies Building Blocks Instructions Instructions 1. Preheat the

Building Blocks

End Results Vary … Final Product Varies Building Blocks Instructions Instructions 1. Preheat the oven to

Instructions

Instructions

1. Preheat the oven to 450.

2. Melt butter and chocolate together in the top of a double broiler

or in the microwave. Add sea salt.

7. Baking time will depend on your oven; start with 7 minutes for a

thin outer shell with a completely molten interior.

8. Melt a little more chocolate to drizzle on top. Sprinkle a little

more salt, and serve with berries or ice cream.

3. Meanwhile, beat together the egg, egg yolks, and sugar with a whisk or an
3. Meanwhile, beat together the egg, egg yolks, and sugar with a
whisk or an electric beater until light
and slightly
foamy.
4. Add the egg mixture to the warm chocolate; whisk quickly to
combine. Add flour and stir just to combine. The batter will be quite
thick.
5. Butter small ramekins, or use Reynolds foil cupcake liners.
6. Divide the batter evenly among the ramekins. (You can make
the cakes in advance to this point and chill them until you're ready
to bake. Be sure to bring the batter back to room temperature
before baking.)

© Synopsys 2012

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until you're ready to bake. Be sure to bring the batter back to room temperature before

Ever Increasing Chip Size Leads to Hierarchical Design

Typical Flat versus Hierarchical Threshold Hierarchical Flat Instances 3M 5M 15M … 100M+
Typical
Flat versus Hierarchical
Threshold
Hierarchical
Flat
Instances
3M
5M
15M
… 100M+

© Synopsys 2012

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Typical Flat versus Hierarchical Threshold Hierarchical Flat Instances 3M 5M 15M … 100M+ © Synopsys 2012

Ten Best Practices for Hierarchical Design

Understanding These Practices Can Help

#1 Floorplan Affects design closure #2 Top-Level Style Requires different discipline #3 Block Size Tradeoff
#1 Floorplan
Affects design closure
#2 Top-Level Style
Requires different discipline
#3 Block Size
Tradeoff size versus TAT
#4 Modeling
Modeling for top-level closure
#5 Top-Level Closure
Meeting the inter-block signals

© Synopsys 2012

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#6 Block-Level I/O Paths

Affects block design closure

#7 Block-Level Drivers/Loads

Affects block boundary closure

#8 Inter-Block Critical Paths

Absence helps chip closure

#9 Constraints Management

Affects design closure & TAT

#10 Signoff STA

Correlates to close timing

chip closure #9 Constraints Management Affects design closure & TAT #10 Signoff STA Correlates to close

#1 Floorplan

Affects Design Closure

Example 1 vs.
Example 1
vs.
Example 2 vs.
Example 2
vs.

Challenge

© Synopsys 2012

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Better Approach

Partitioning Guidelines

Logical connectivity

Clock

Voltage areas

Physical size

Multiple Instantiated Modules (MIM)

Macro Placement

Power Planning

IO Planning

– Physical size – Multiple Instantiated Modules (MIM) • Macro Placement • Power Planning • IO

#2 Top-Level Style

Requires Different Design Discipline

Channel
Channel

© Synopsys 2012

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Narrow Channel
Narrow Channel
Abutted
Abutted

Implementation Complexity

clock Data
clock
Data

#3 Block Size

Tradeoff Size versus TAT (turn around time)

   

1.5M

1.5M

1.5M

1.5M

1.5M

   

1.5M

2M

2M

Faster TAT per block but more blocks to integrate

3M

5M
5M

5M

Longer TAT per block but fewer blocks to integrate

What Is Reasonable Size Depends A Lot On Design Team Preference?
What Is Reasonable Size Depends A Lot On Design Team Preference?

Note: Block Size in instances

© Synopsys 2012

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What Is Reasonable Size Depends A Lot On Design Team Preference? Note: Block Size in instances

#4 Modeling

ETM vs. Abstract Model

Extracted Timing Model (ETM) Blocks modeled by timing arcs only Used for customized IP
Extracted Timing Model (ETM)
Blocks modeled by timing arcs only
Used for customized IP

© Synopsys 2012

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Abstract Model Interface cells of each block retained Recommended for P&R blocks
Abstract Model
Interface cells of each block retained
Recommended for P&R blocks

#5 Top-Level Closure

Meeting Timing on Inter-Block Signals

Chg graphic
Chg graphic

© Synopsys 2012

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Closing top-level inter block signals can be challenging

Can be minimized with

Proper estimation of interface

constraints

Proper floorplanning for signal connectivity between blocks

Simultaneous optimization of top-level and inter-block

signals needed

for signal connectivity between blocks • Simultaneous optimization of top-level and inter-block signals needed

#6 Block Level I/O Paths

I/O Paths Are Typically Not Finalized Early

Typical Hierarchical Structure Logic Logic Logic Logic Logic Registers Registers Registers Registers Adjacent
Typical Hierarchical Structure
Logic
Logic
Logic
Logic
Logic
Registers
Registers
Registers
Registers
Adjacent Block
Block Under Design
Adjacent Block

I/O paths are not finalized during early stage block design

Overconstraining these paths direct the tool to focus on I/O paths instead of the intra-block paths

Accuracy of proportional time budgets is affected if interfaces are

still changing

© Synopsys 2012

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paths • Accuracy of proportional time budgets is affected if interfaces are still changing © Synopsys

#6 Block Level I/O Paths

Registering Block Outputs Makes Budgeting Easier

A Better Approach Logic Logic Logic Logic Registers Registers Registers Registers Adjacent Block Block Under
A Better Approach
Logic
Logic
Logic
Logic
Registers
Registers
Registers
Registers
Adjacent Block
Block Under Design
Adjacent Block

Registering block outputs makes budgeting less dependent on completeness of the netlist and easier

Re-partitioning logic hierarchy helps manage constraints complexity

Partitioning according to power domains / logic hierarchy makes

flow easier

© Synopsys 2012

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complexity • Partitioning according to power domains / logic hierarchy makes flow easier © Synopsys 2012

#7: Block Level Drivers and Loads

Modeling I/O with Realistic Values Drives Convergence

Block Interface timing is one of the toughest issues in hierarchical flow

Realistic model of your input and output ports helps design convergence

Block A Block B A B
Block A
Block B
A
B

When designing Block A, need to consider load at output port A set_load

When designing Block B, need to consider driving cell at input port B

set_driving_cell

© Synopsys 2012

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• When designing Block B, need to consider driving cell at input port B – set_driving_cell

#7: Block Level Drivers and Loads

Inter-blocks Paths Are One Of The Toughest SOC Challenges

If no load is specified

Cell cannot be sized correctly
Cell cannot be sized
correctly

n

no load is specified Cell cannot be sized correctly n • Without good estimation of loads

Without good estimation of loads and driving cell

Integrating these blocks forces iterations unnecessary to meet timing

Budgeting can automatically generate driver and load information

Generate a quick netlist to run through budgeting for more accurate results

© Synopsys 2012

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and load information – Generate a quick netlist to run through budgeting for more accurate results

#8: Inter-Block Critical Paths

Absence Helps Chip Closure

Block to Block path, crossing Top Top to Block path If tool cannot see complete
Block to Block path,
crossing Top
Top to Block
path
If tool cannot see complete path, may be
.
challenge to stitch them at top-level

© Synopsys 2012

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Avoid critical paths crossing

multiple blocks

Makes timing closure difficult

Contain them within the same

block or if you must cross multiple blocks, minimize the number of blocks

Budgeting, sizing, and load estimations are needed to solve inter-block critical paths violations

number of blocks • Budgeting, sizing, and load estimations are needed to solve inter-block critical paths

#8: Inter-Block Critical Paths

Shielding Helps Chip Closure

Without Shielding With Shielding
Without Shielding
With Shielding

Use shielding to reduce crosstalk effects between the block- and top- level t significantly improve timing closure in inter-block critical paths

Use new Transparent Interface Optimization (TIO) in IC Compiler

© Synopsys 2012

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in inter-block critical paths • Use new Transparent Interface Optimization (TIO) in IC Compiler © Synopsys

#9: Constraints Management

Pay Attention to Constraints

Eg: Infeasible Path, insufficient for 1 clock cycle Eg: Infeasible Path, i/p delay too large
Eg: Infeasible Path, insufficient for 1 clock cycle
Eg: Infeasible Path, i/p delay too large

© Synopsys 2012

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Infeasible paths are paths that are impossible to meet timing

Missing false path/multi-cycle path constraints

Unreasonable input/output delay constraints

Other things to watch out

size_only attributes

dont_touch attributes

Multi-cycle paths

False paths

Etc.

size_only attributes – dont_touch attributes – Multi-cycle paths – False paths – Etc.

#10 Signoff Correlation

Tighter Correlation Helps Close Timing

Signoff Correlation Tighter Correlation Helps Close Timing • Use IC Compiler signoff correlation checker system –

Use IC Compiler signoff correlation checker system

Performs both consistency and correlation check with user controllable accuracy level

Supports both pre-route and post-route checks

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check with user controllable accuracy level – Supports both pre-route and post-route checks © Synopsys 2012

#10 Signoff Correlation Flows

Flows for Pre-route and Post-route Correlation Checks

Flows Flows for Pre-route and Post-route Correlation Checks Pre-Route Flow • Focus on environment and library

Pre-Route Flow

Pre-route and Post-route Correlation Checks Pre-Route Flow • Focus on environment and library setup for pre-route

Focus on environment and library setup for pre-route correlation

Certain variables for correlation may have runtime and/or QoR impact on optimization

Correlation setup may change and re-check may be needed for

post-route

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QoR impact on optimization • Correlation setup may change and re-check may be needed for post-route

Today’s Designs Are Big & Hierarchical

Today’s Designs Are Big & Hierarchical Source: L. Besson, STMicroelectronics © Synopsys 2012 52 Timing Signoff

Source: L. Besson, STMicroelectronics

© Synopsys 2012

52

Timing Signoff Challenges

More effects, more variation

Impacts accuracy vs. runtime

Hierarchical P&R vs. flat signoff

Large machines and runtime

Interactions between top & block

30-40% blocks are tough to close

10 to 20 ECO iterations

• Lot’s of scenarios to analyze

more machines, more reports

are tough to close – 10 to 20 ECO iterations • Lot’s of scenarios to analyze

The Nanometer Challenges

Top Issues to Look at

The Nanometer Challenges Top Issues to Look at (1) SION Dielectric/Polysilicon Gate; (2) High-k Dielectric/Metal Gate

(1) SION Dielectric/Polysilicon Gate; (2) High-k Dielectric/Metal Gate

© Synopsys 2012

Source: ITRS 2009; C.A. Malachowsky, NVIDIA, EDPS 2009; P. Saxena , Intel, ISPD 2003

53

Gate © Synopsys 2012 Source: ITRS 2009; C.A. Malachowsky, NVIDIA, EDPS 2009; P. Saxena , Intel,
IC Design Methodology
IC Design Methodology

© Synopsys 2012

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IC Design Methodology © Synopsys 2012 54

But, Synthesis has Evolved

But, Synthesis has Evolved © Synopsys 2012 55 • Synthesis has evolved beyond logic mapping •

© Synopsys 2012

55

Synthesis has evolved

beyond logic mapping

• It’s now predicting and

resolving congestion for physical design

Synthesis prediction of physical effects evolution is key to progress

resolving congestion for physical design • Synthesis prediction of physical effects evolution is key to progress

And, Physical Design Under Heavy Load

And, Physical Design Under Heavy Load © Synopsys 2012 56 • Increasingly, Physical Design is the

© Synopsys 2012

56

Increasingly, Physical

Design is the driver for

implementation schedule

• It’s where the rubber meets the road speed, die-size, power, yield

P&R evolution key to progress

• It’s where the rubber meets the road – speed, die-size, power, yield • P&R evolution

What’s on Designer’s Mind?

Design & Project Management!

How close are we to our design goals? What’s the status of the blocks right
How close are we to our design goals?
What’s the status of the blocks
right now?
Is everyone using the same tool
version and the standard scripts?
How can I use the experience
How much compute and license
from this project to plan the
resources are we using?
next one better?
What’s taking up the most time?
Which step? Which block?
© Synopsys 2012
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Many Flavors Of “Methodology”…

Imagination Is the Only Limit…

Many Flavors Of “Methodology”… Imagination Is the Only Limit… © Synopsys 2012 58 Source: www.bk.com 2010

© Synopsys 2012

58

Source: www.bk.com 2010

Many Flavors Of “Methodology”… Imagination Is the Only Limit… © Synopsys 2012 58 Source: www.bk.com 2010

Past “Guidance” doesn’t Always Apply to the Present

create_clock -period [0.7 * target]

set_max_area to “0”

Use small blocks for fast turnaround time

to “0” • Use small blocks for fast turnaround time high performance small area Things have

high performance

Use small blocks for fast turnaround time high performance small area Things have changed but users

small area

Things have changed but users are still

using the above techniques!

2000-2005

2005-2008

2009-2010

2011-

“Correlation”

“Look-ahead”

“In-Design”

“Exploration”

Synthesis Design Planning Place & Route DRC / LVS © Synopsys 2012 59 Signoff
Synthesis
Design
Planning
Place
& Route
DRC / LVS
© Synopsys 2012
59
Signoff
Synthesis Place & Route DRC / LVS Signoff
Synthesis
Place
& Route
DRC / LVS
Signoff
Synthesis Place & Route DRC / LVS Signoff
Synthesis
Place
& Route
DRC / LVS
Signoff
Synthesis Place & Route DRC / LVS Signoff Exploration Implementation
Synthesis
Place
& Route
DRC / LVS
Signoff
Exploration
Implementation
Place & Route DRC / LVS Signoff Synthesis Place & Route DRC / LVS Signoff Exploration

The Past vs. The Present

Wireload Model (WLM) results in higher frequency during Synthesis than using Design Compiler Topographical (DCT) technology …

Figure 1 Figure 2
Figure 1
Figure 2

With WLM, these two circuits have the same delay

1 Figure 2 With WLM, these two circuits have the same delay With DCT, the delay

With DCT, the delay is a reflection of the x-y location of the cells

Which is more realistic?

© Synopsys 2012

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delay With DCT, the delay is a reflection of the x-y location of the cells Which

Ten Best Practices for Design Methodology

#1 Libraries Know Your Attributes #2 Setup Correlation and Runtime #3 Scripts Impacts Your Design
#1 Libraries
Know Your Attributes
#2 Setup
Correlation and Runtime
#3 Scripts
Impacts Your Design
#4 Constraints
Watch Your Constraints
#5 Analyze
Analyze-Fix-Proceed
#6 Methodology One or Two Flows #7 Optimization Adjust Accordingly #8 Signoff Review Your Environment
#6 Methodology
One or Two Flows
#7 Optimization
Adjust Accordingly
#8 Signoff
Review Your Environment
#9 Performance
Leverage Your EDA Partner
#10 Low Power
Architecture Drives Power

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Your Environment #9 Performance Leverage Your EDA Partner #10 Low Power Architecture Drives Power © Synopsys

#1 Libraries: Know Your Attributes

Why is my design larger in area? Why is it taking so long to run?

my design larger in area? Why is it taking so long to run? Original Area After

Original Area

After Optimization
After
Optimization

New Area

Watch for dont_use, dont_touch, and size_only usage in your libraries and scripts

Attributes are user-controlled to guide optimization Restricting optimization may lead to problems

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are user-controlled to guide optimization • Restricting optimization may lead to problems © Synopsys 2012 62

Technology and IP

Make Sure to Have a Good Quality Library

A properly designed set of library

cells give optimization engines more

choice

Avoid cells sensitive to minor change in load, impedes convergence

Footprint-equivalent cells are useful for final-stage optimization w/ minimal perturbation to other design metrics

Std. cell pins should be on grid - (especially complex cells with small drive strength: higher pin density)

Multiple variants for each flop (drive

strengths, delays, setup times,

)

Library quality enabler for targeted performance

© Synopsys 2012

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Example: Cell Sensitivity To Load Uncertainty Cell A Cell B D B * A C
Example:
Cell Sensitivity To Load Uncertainty
Cell A
Cell B
D
B
*
A
C
load
C*
Delay
© Synopsys 2012 63 Example: Cell Sensitivity To Load Uncertainty Cell A Cell B D B

#2 Setup: Correlation and Runtime

What do designers do when they run into these?

Netlist v1.0 SDC v1.0 Netlist v1.1 SDC v1.1 What happened??? • Compile • 3.2M •
Netlist v1.0
SDC v1.0
Netlist v1.1
SDC v1.1
What
happened???
• Compile
• 3.2M
• Compile
• 6.8M
instances
instances??
• Found issues after days of
engineering work
• Size_only on 3.7M cells
• SDC with all cells set with
set_disable_clock_gating on

© Synopsys 2012

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work • Size_only on 3.7M cells • SDC with all cells set with set_disable_clock_gating on ©

Review Your Settings and Input

Understand the Different Objectives

• Detect design issues and dirty DC Utility Checker constraints styles that can lead to
• Detect design issues and dirty
DC Utility
Checker
constraints styles that can lead to
bad runtime/memory and QoR
ICC Utility
• Detect readiness of physical design
before going into various
Checker
implementation stages
• Detects application variables,
PT Utility
Checker
settings and design issues causing
runtime or memory increase

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variables, PT Utility Checker settings and design issues causing runtime or memory increase © Synopsys 2012

#3 Scripts: Impacts Your Design

When someone tells you “Tool A” is X times faster than “Tool B”

tells you “Tool A” is X times faster than “Tool B” Incomplete Complete Need to put

Incomplete

“Tool A” is X times faster than “Tool B” Incomplete Complete Need to put things in

Complete

Need to put things in perspective …

First Step: review your script

– How was the script migrated to “Tool A”?

Did you also update the script to leverage the latest technologies?

Early stage of your design, think fast mode

Final stage of your design, think QoR

© Synopsys 2012

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• Early stage of your design, think fast mode • Final stage of your design, think

Tool Input can Impact Results

Understand How the Tool Can Help Meet Design Goals

Results Understand How the Tool Can Help Meet Design Goals © Synopsys 2012 67 • Today’s

© Synopsys 2012

67

• Today’s design requires completeness

Synopsys tools are tailored for

performance, but they also have a mode to run fast

Recommendations

The typical complaint is long runtime, choose your goal setting accordingly

Make sure your script is up to date for

your end goal and to take advantage

of the latest features

accordingly – Make sure your script is up to date for your end goal and to

#4 Constraints: Watch Your Constraints

Symptoms of over-constraining: long runtime, excessive buffering and huge violations

Original Clock period Input Delay Output Delay Time Available for logic
Original Clock period
Input Delay
Output Delay
Time Available
for logic

Over-constraining could guide the tool to focus on artificial critical paths

Over-constraining happens with

Unrealistic input and/or output delays

Tightening the clock period

Specifying large clock uncertainty

Synopsys tools are designed to work towards meeting design goals… but don’t expect miracles!
Synopsys tools are designed to work towards meeting design goals…
but don’t expect miracles!

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Synopsys tools are designed to work towards meeting design goals… but don’t expect miracles! © Synopsys

Understanding EDA Tool will help

Simple Illustration Will DC do this transformation?

CLKA wns = -0.300 CLKB wns = -0.100 Circuit A
CLKA wns = -0.300
CLKB wns = -0.100
Circuit A
CLKA wns = -0.300 CLKB wns = -0.100 Circuit A CLKA wns = -0.280 CLKB wns
CLKA wns = -0.280 CLKB wns = -0.150 Circuit B
CLKA wns = -0.280
CLKB wns = -0.150
Circuit B

Default Weights

Delay Cost Before

Delay Cost After

CLKA weight = 1 CLKB weight = 1

0.30

 

0.28

0.10

0.15

Total WNS Cost

0.40

<

 

0.43

Cost = ∑ p i * w i

Total cost increased Transformation rejected

Worst WNS = -0.300

Adjusted Weights Delay Cost Before Delay Cost After CLKA weight = 10 CLKB weight =
Adjusted Weights
Delay Cost Before
Delay Cost After
CLKA weight = 10
CLKB weight = 1
3.00
2.80
0.10
0.15
Total WNS Cost
3.10
> 2.95
© Synopsys 2012
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Total cost reduced Transformation accepted

Worst WNS = -0.280

WNS Cost 3.10 > 2.95 © Synopsys 2012 69 Total cost reduced Transformation accepted Worst WNS

#5 Analyze: Analyze-Fix-Proceed

#5 Analyze: Analyze-Fix-Proceed Push Button Flow d o e s n o t e x i

Push Button Flow

does not exists

Push Button Flow d o e s n o t e x i s t s

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Know your circuit to guide the tool
Know your circuit
to guide the tool
Push Button Flow d o e s n o t e x i s t s

Synopsys Galaxy Implementation Flow

DC Graphical
DC Graphical

compile_ultra -spgSynopsys Galaxy Implementation Flow DC Graphical insert_dft compile_ultra – spg -incr IC Compiler place_opt -spg

insert_dftGalaxy Implementation Flow DC Graphical compile_ultra -spg compile_ultra – spg -incr IC Compiler place_opt -spg

compile_ultra – spg -incr spg -incr

compile_ultra -spg insert_dft compile_ultra – spg -incr IC Compiler place_opt -spg clock_opt route_opt
IC Compiler
IC Compiler

place_opt -spg clock_opt route_opt
clock_opt place_opt -spg route_opt
route_optplace_opt -spg clock_opt

signoff_optIC Compiler place_opt -spg clock_opt route_opt

place_opt -spg clock_opt route_opt signoff_opt StarRC PrimeTimeSI Signoff extraction Signoff STA Analyze
StarRC PrimeTimeSI
StarRC
PrimeTimeSI

Signoff extractionclock_opt route_opt signoff_opt StarRC PrimeTimeSI Signoff STA Analyze results between design stages ©

Signoff STAsignoff_opt StarRC PrimeTimeSI Signoff extraction Analyze results between design stages © Synopsys 2012 71

Analyze results between design stages
Analyze
results
between
design
stages

© Synopsys 2012

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StarRC PrimeTimeSI Signoff extraction Signoff STA Analyze results between design stages © Synopsys 2012 71

#6 Methodology: One or Two Flows

Design specifications and constraints changes

constantly during the design cycle

One flow for both exploration & Implementation
One flow
for both
exploration &
Implementation
cycle One flow for both exploration & Implementation 180 nanometers (2000) 225K gates, 11 RAMs 150

180 nanometers (2000) 225K gates, 11 RAMs 150 MHz

© Synopsys 2012

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Exploration flow target for early specs & constraints Implementation flow for final design realization
Exploration flow
target for
early specs
& constraints
Implementation
flow
for final
design
realization
Implementation flow for final design realization 45 nanometers (2010) 96mm 2 , ~ 300M transistors 7-9W

45 nanometers (2010) 96mm 2 , ~ 300M transistors

7-9W

Implementation flow for final design realization 45 nanometers (2010) 96mm 2 , ~ 300M transistors 7-9W

Exploration Throughout Galaxy

DC Explorer

Early RTL Exploration

Accelerates Design Schedules

Design Compiler

Look-ahead & Physical Guidance

Creates a better starting point

IC Compiler

Design Exploration

Creates initial floorplan

Block Feasibility

Determines physical feasibility

Galaxy Constraint Analyzer

Continuous improvement

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Exploration Implementation RTL RTL RTL Exploration Synthesis Design Design Exploration Planning Block Block
Exploration
Implementation
RTL
RTL
RTL
Exploration
Synthesis
Design
Design
Exploration
Planning
Block
Block
Feasibility
Implementation
Physical
RTL Exploration Synthesis Design Design Exploration Planning Block Block Feasibility Implementation Physical

#7 Optimization: Adjust Accordingly

Adjust your constraints to model effects of downstream design steps

An Illustration

Design Compiler
Design
Compiler

Account for clock trees

No hold-timing fixing

Be careful with critical range

Do not over-constrain

© Synopsys 2012

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clock trees • No hold-timing fixing • Be careful with critical range • Do not over-constrain
clock trees • No hold-timing fixing • Be careful with critical range • Do not over-constrain

Manage Design Constraints Throughout

Guidelines For Convergent Timing Closure

Synthesis and placement

Do not over-constrain during

synthesis

Use DC SPG flow

Account for max_transition and clock uncertainty

Specify pre-CTS estimated constraints

CTS

Remove pre-CTS estimated constraints

Route

Remove/adjust pre-route constraints

Adjust crosstalk thresholds

© Synopsys 2012

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Timing Closure Profile 1,100 1,050 1029 1,000 Timing Closure 971 950 Profile 913 900 850
Timing Closure Profile
1,100
1,050
1029
1,000
Timing Closure
971
950
Profile
913
900
850
800
Do
Not
over
Synthesis
Place
Clock
Route
Complicate your flow
Addnl. Customization For High-Performance
Tuned For Hi-Performance/Low Power
RM (Baseline)
MHz
Complicate your flow Addnl. Customization For High-Performance Tuned For Hi-Performance/Low Power RM (Baseline) MHz

#8 Signoff: Review your Environment

Unlike wine, scripts grow stale with age

Runtime (CPU Hrs) 60 50 40 30 20 10 0 1.1 1.2 5.5 37.0 50+
Runtime (CPU Hrs)
60
50
40
30
20
10
0
1.1
1.2
5.5
37.0
50+
Instances (Million)
Memory Usage (GB) 172 GB 128 112 96 80 64 48 32 16 0 1.1
Memory Usage (GB)
172 GB
128
112
96
80
64
48
32
16
0
1.1
1.2
5.5
37.0
50+
Instances (Million)

Designs run at customer site using revised

PrimeTime scripts and latest release version

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(Million) Designs run at customer site using revised PrimeTime scripts and latest release version © Synopsys

PrimeTime Scripts: Key Areas to Review

Environment and setup

Use latest release and

ensure adequate hardware resources

Reading parasitics

Use binary parasitics when possible

Multiple timing updates

Eliminate redundant/legacy

update_timing steps

Inefficient TCL scripting and

reporting

© Synopsys 2012

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Inefficient TCL scripting and reporting © Synopsys 2012 77 PrimeTime Design Utility Checker can help with
PrimeTime Design Utility Checker can help with some of these tasks
PrimeTime Design Utility Checker
can help with some of these tasks
TCL scripting and reporting © Synopsys 2012 77 PrimeTime Design Utility Checker can help with some

#9 Performance: Leverage Your EDA Partner

Starting Point

Reduce time-to-results

Built on Synopsys RM

Understand the new technologies and features

Easy to use

Automated methodology to

achieve 90% of target quickly

Additional advanced techniques to reach final goal

Minimize number of iterations

or “trial and errors”

Reduce ECO efforts

Iterations Synthesis P&R Signoff + ECO Typical Flow HSLP Flow Design Schedule
Iterations
Synthesis
P&R
Signoff + ECO
Typical Flow
HSLP Flow
Design Schedule

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ECO efforts Iterations Synthesis P&R Signoff + ECO Typical Flow HSLP Flow Design Schedule © Synopsys

HSLP Implementation Best Practices

Reduces Time-to-Results

High Performance, Low Power (HSLP) Flow Requires Customization

Typical Flow on Regular designs Typical Flow on High Performance designs Targets 100% 90% Typical
Typical Flow on
Regular
designs
Typical Flow on
High Performance designs
Targets
100%
90%
Typical Flow
75%
HSLP Flow
With HSLP
Implementation
Best Practices
Design-specific
Reduces time-to-results
customization
Time

© Synopsys 2012

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HSLP Implementation Best Practices Design-specific Reduces time-to-results customization Time © Synopsys 2012 79

#10 Low Power: Architecture Drives Power

DESIGN TECHNIQUES

0.9V 0.7V 0.9V OFF 0.9V 0.9V 0.9V
0.9V
0.7V
0.9V
OFF
0.9V
0.9V
0.9V
OFF 0.9V 0.7V 0.9V OFF SR 0.9V 0.7V 0.9V
OFF
0.9V
0.7V
0.9V
OFF
SR
0.9V
0.7V
0.9V

Multiple Voltage (MV) Domains

Multi-Supply with shutdown

No State Retention

Multi-Voltage with shutdown

Multi-voltage with shutdown & State Retention

© Synopsys 2012

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VDDI VDDO L IN S
VDDI
VDDO
L
IN
S

OUT

VSS

Level Shifters
Level
Shifters

  
  
  

  

VDD VDDB IN OUT ISO EN
VDD
VDDB
IN
OUT
ISO
EN

VSS

Isolation Cells
Isolation
Cells
  VDD VDDB IN OUT ISO EN VSS Isolation Cells VDD on/off Gate Gate Gate
VDD on/off Gate Gate Gate Power Switches (MTCMOS)
VDD
on/off
Gate
Gate
Gate
Power
Switches
(MTCMOS)

VDD

VDDB RR VSS
VDDB
RR
VSS
Retention Registers
Retention
Registers
Switches (MTCMOS) VDD VDDB RR VSS Retention Registers          

 

 

VDD VDDB IN OUT AO
VDD
VDDB
IN
OUT
AO

VSS

Always- on Logic
Always-
on Logic
Registers            VDD VDDB IN OUT AO VSS
Registers            VDD VDDB IN OUT AO VSS
Registers            VDD VDDB IN OUT AO VSS

Registers            VDD VDDB IN OUT AO VSS
New Techniques and Challenges
New Techniques and Challenges

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New Techniques and Challenges © Synopsys 2012 81

The Race to 20nm Is On!

Leading The Way In 20nm Design

Leading The Way In 20nm Design

© Synopsys 2012

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The Race to 20nm Is On! Leading The Way In 20nm Design © Synopsys 2012 82

The 20 nm Challenge: Single Exposure

“Last Pitch With Single Exposure ~ 80 Nanometers…”

We Can Print This,… But We Cannot Print This
We Can Print This,…
But We Cannot Print This

Source M. van den Brink, ASML, ITF 2009; P. Magarshack , STMicroelectronics, 2010

© Synopsys 2012

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We Cannot Print This Source M. van den Brink, ASML, ITF 2009; P. Magarshack , STMicroelectronics,

The Solution: Double Patterning

A Significant Change

The Solution: Double Patterning A Significant Change We Can Print This, and This,… And Then This!
We Can Print This, and This,… And Then This!
We Can Print This, and This,…
And Then This!

© Synopsys 2012

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The Solution: Double Patterning A Significant Change We Can Print This, and This,… And Then This!

Synopsys Solution

DPT Ready IC Compiler P&R, and IC Validator DRC

Solution DPT Ready IC Compiler P&R, and IC Validator DRC Wide Spacing Enforced Two-Color Decomposed Design
Wide Spacing Enforced
Wide Spacing Enforced
Two-Color Decomposed Design
Two-Color Decomposed Design

Source: Synopsys Research 2011

© Synopsys 2012

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and IC Validator DRC Wide Spacing Enforced Two-Color Decomposed Design Source: Synopsys Research 2011 © Synopsys

Synopsys Solution

DPT Ready IC Compiler P&R, and IC Validator DRC

Synopsys Solution DPT Ready IC Compiler P&R, and IC Validator DRC Source: Synopsys Research 2011 ©
Synopsys Solution DPT Ready IC Compiler P&R, and IC Validator DRC Source: Synopsys Research 2011 ©
Synopsys Solution DPT Ready IC Compiler P&R, and IC Validator DRC Source: Synopsys Research 2011 ©

Source: Synopsys Research 2011

© Synopsys 2012

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Synopsys Solution DPT Ready IC Compiler P&R, and IC Validator DRC Source: Synopsys Research 2011 ©

The Challenge: Planar CMOS

Insufficient Performance, Excessive Power

Planar CMOS Insufficient Performance, Excessive Power 32 Nanometer Planar Performance  Power  Source: K.
32 Nanometer Planar Performance  Power 
32 Nanometer Planar
Performance  Power 

Source: K. Kuhn, Intel, IDF 2011

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Excessive Power 32 Nanometer Planar Performance  Power  Source: K. Kuhn, Intel, IDF 2011 ©

The Solution: Non-Planar CMOS

FinFET or Tri-Gate CMOS

The Solution: Non-Planar CMOS FinFET or Tri-Gate CMOS 22 Nanometer Tri-Gate Performance  Power  Source:
22 Nanometer Tri-Gate Performance  Power 
22 Nanometer Tri-Gate
Performance  Power 

Source: K. Kuhn, Intel, IDF 2011

© Synopsys 2012

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or Tri-Gate CMOS 22 Nanometer Tri-Gate Performance  Power  Source: K. Kuhn, Intel, IDF 2011

The Solution: Non-Planar CMOS

The First “Revolution”

The Solution: Non-Planar CMOS The First “Revolution” Source: M. Bohr, Intel, YouTube 2011 © Synopsys 2012
The Solution: Non-Planar CMOS The First “Revolution” Source: M. Bohr, Intel, YouTube 2011 © Synopsys 2012

Source: M. Bohr, Intel, YouTube 2011

© Synopsys 2012

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The Solution: Non-Planar CMOS The First “Revolution” Source: M. Bohr, Intel, YouTube 2011 © Synopsys 2012

There Are Many Flavors, But…

Reality and Fantasy Are not the Same Thing !

There Are Many Flavors, But… Reality and Fantasy Are not the Same Thing ! © Synopsys
There Are Many Flavors, But… Reality and Fantasy Are not the Same Thing ! © Synopsys
There Are Many Flavors, But… Reality and Fantasy Are not the Same Thing ! © Synopsys
There Are Many Flavors, But… Reality and Fantasy Are not the Same Thing ! © Synopsys
There Are Many Flavors, But… Reality and Fantasy Are not the Same Thing ! © Synopsys
There Are Many Flavors, But… Reality and Fantasy Are not the Same Thing ! © Synopsys
There Are Many Flavors, But… Reality and Fantasy Are not the Same Thing ! © Synopsys

© Synopsys 2012

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There Are Many Flavors, But… Reality and Fantasy Are not the Same Thing ! © Synopsys

FinFET Advantages

FinFET vs Planar Transistor

Planar Inversion Layer FinFET Fin
Planar
Inversion Layer
FinFET
Fin

Source: Intel

© Synopsys 2012

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Superior drive current

Active region spans the fin height and thickness (3 sides)

Ids α (2*Hfin+Tfin) as opposed to just thickness for planar

Reduced leakage

Depleted substrate

Enhanced electron

mobility

High-K gate oxide

Metal gates in place of PolySilicon

Strained silicon

Multiple fins possible to increase total drive

strength for higher performance

of PolySilicon – Strained silicon – Multiple fins possible to increase total drive strength for higher

This Is Not The End of Moore’s Law!

But the Gap Between Intel and the Crowd Is Widening

of Moore’s Law! But the Gap Between Intel and the Crowd Is Widening Source: M. Bohr,

Source: M. Bohr, Intel, IDF 2011

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of Moore’s Law! But the Gap Between Intel and the Crowd Is Widening Source: M. Bohr,

3D ICs: Technology Trends

Four Main Categories of “> 2D-IC” Ahead

1 Memory (Wide I/O) Memory “Cube” “Cube” on Logic 3
1
Memory
(Wide I/O) Memory
“Cube”
“Cube” on Logic
3
2
2
C4
C4
(Wide I/O) Memory “Cube” “Cube” on Logic 3 2 C4 Silicon Interposer TSV 3D Stack Bump

Silicon Interposer

TSV 3D Stack Bump 4
TSV
3D Stack
Bump
4

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I/O) Memory “Cube” “Cube” on Logic 3 2 C4 Silicon Interposer TSV 3D Stack Bump 4

3D-IC Two Basic Configurations Emerging

Addressing Gigascale Design Challenges

Silicon Interposer (2.5D) • Horizontally connected dies • Drivers: Consumer, Storage, Networking • Benefits:
Silicon Interposer (2.5D)
• Horizontally connected dies
• Drivers: Consumer, Storage, Networking
• Benefits: Yield, Cost, TTM & Flexibility
3D-IC
• Vertically stacked dies with TSVs
• Drivers: Wireless handset, Processors
• Benefits: Performance, form factor

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dies with TSVs • Drivers: Wireless handset, Processors • Benefits: Performance, form factor © Synopsys 2012

The ”Memory Cube” Now

8 die stack 560 microns 50 microns 1
8 die stack
560 microns
50 microns
1

Source: C.-G. Hwang, Samsung, IEDM 2006

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”Memory Cube” Now 8 die stack 560 microns 50 microns 1 Source: C.-G. Hwang, Samsung, IEDM
IP Market, an opportunity for Latin America
IP Market, an opportunity for Latin
America

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IP Market, an opportunity for Latin America © Synopsys 2012 96

IP

Intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or chip layout design

that is the intellectual property of one party

IP cores may be licensed to another party or can be

owned and used by a single party alone

IP cores can be used as building blocks within ASIC

chip designs or FPGA logic designs

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party alone IP cores can be used as building blocks within ASIC chip designs or FPGA

IP

IP cores in the electronic design industry have had a profound impact on the design of systems on a chip

IP core licensor spread the cost of development among multiple chip

makers

IP cores for standard processors, interfaces, and internal functions have

enabled chip makers to put more of their resources into developing the differentiating features of their chips new innovations faster

Licensing and use of IP cores in chip design came into common practice in the 1990s

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innovations faster Licensing and use of IP cores in chip design came into common practice in

Semiconductor IP Market Segments

2011 Design IP Revenue: $1.9B

Physical libaries

3% Other IP 1% 4% Memory Cells/Blocks 10% Microprocessors 39% Wired Interfaces 19% Fixed Function
3%
Other IP
1%
4%
Memory Cells/Blocks
10%
Microprocessors
39%
Wired Interfaces
19%
Fixed Function
(GPUs, Security)
DSP
5%
15%

Block Libraries

GP Analog/MS

4%

Processors

(CPUs, GPUs, DSPs)

Source: Gartner, March 2012

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DSP 5% 15% Block Libraries GP Analog/MS 4% Processors (CPUs, GPUs, DSPs) Source: Gartner, March 2012

Semiconductor IP Market Size

Synopsys Share

2,000.0 14.0% 1,800.0 12.0% 1,600.0 10.0% 1,400.0 1,200.0 8.0% 1,000.0 6.0% 800.0 600.0 4.0% 400.0
2,000.0
14.0%
1,800.0
12.0%
1,600.0
10.0%
1,400.0
1,200.0
8.0%
1,000.0
6.0%
800.0
600.0
4.0%
400.0
2.0%
200.0
0.0
0.0%
CY04
CY05
CY06
CY07
CY08
CY09
CY10
CY11
Semiconductor IP Market Size
964.0
1,068.3
1,267.3
1,378.2
1,464.1
1,351.0
1,695.0
1,910.9
Synopsys Share
7.9%
7.6%
7.3%
7.2%
7.2%
9.1%
11.3%
12.4%
$M
Synopsys Share

Source: Gartner, March 2012

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7.9% 7.6% 7.3% 7.2% 7.2% 9.1% 11.3% 12.4% $M Synopsys Share Source: Gartner, March 2012 ©

Top Semiconductor IP Vendors

Rank Company 2010 2011 Growth 2011 Share 1 ARM Holdings 575.8 732.5 27.2% 38.3% 2
Rank
Company
2010
2011
Growth
2011 Share
1
ARM Holdings
575.8
732.5
27.2%
38.3%
2
Synopsys
191.8
236.2
23.2%
12.4%
3
Imagination Te
91.5
126.4
38.1%
6.6%
4
MIPS Technolog
85.3
72.1
-15.5%
3.8%
5
Ceva
44.9
60.2
34.1%
3.2%
6
Silicon Image
38.5
42.8
11.2%
2.2%
7
Rambus
41.4
38.9
-6.0%
2.0%
8
Tensilica
31.5
36.3
15.2%
1.9%
9
Mentor Graphic
27.3
23.6
-13.8%
1.2%
10
AuthenTec
19.6
22.8
16.3%
1.2%
Source: Gartner, March 2012

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27.3 23.6 -13.8% 1.2% 10 AuthenTec 19.6 22.8 16.3% 1.2% Source: Gartner, March 2012 © Synopsys

Total Number of IP Blocks per SoC

% Design Reuse

IP Vendors Also Need to Provide More Functions and Functionality

120

100

80

60

40

20

0

Avg. # IP Blocks per SoC % Design Reuse
Avg. # IP Blocks per SoC
% Design Reuse

Subsystems

40 20 0 Avg. # IP Blocks per SoC % Design Reuse Subsystems Blocks 2005 2006
40 20 0 Avg. # IP Blocks per SoC % Design Reuse Subsystems Blocks 2005 2006
40 20 0 Avg. # IP Blocks per SoC % Design Reuse Subsystems Blocks 2005 2006
40 20 0 Avg. # IP Blocks per SoC % Design Reuse Subsystems Blocks 2005 2006

Blocks

2005

2006

2007

2008

2009

2010

2011

2012

2013

2014

Source: Semico, October 2010

70

60

50

40

30

20

10

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2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 Source: Semico, October 2010 70 60

Subsystems:

The Next Evolution in The IP Market

SoC Ready: Pre-integrated and Verified
SoC Ready:
Pre-integrated
and Verified

What is a Subsystem?

Complete Solution: HW, SW, Prototype

Seamlessly Drop- in and Go

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and Verified What is a Subsystem? Complete Solution: HW, SW, Prototype Seamlessly Drop- in and Go

Thank You

© Synopsys 2012

Thank You © Synopsys 2012 104

104

Thank You © Synopsys 2012 104