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# CHAPTER 7 SOLUTIONS

4/03/10

7-1)

D N 2 0.4
1
36

12 V .
1 D N1 0.6
2

a ) Vo Vs
b) I Lm
iLm

Vo2
122

1.67 A.
Vs DR 36(0.4)(6)

Vs D
36(0.4)

1.44 A.
Lm f 100(10) 6 (100, 000)

iLm
2.39 A.
2
i
I Lm ,min I Lm Lm 0.947 A.
2
VD
12(0.4)
c) Vo o
0.16 V .
RCf 6(50)(10) 6 (100, 000)
Vo 0.16

1.33%
Vo
12
I Lm ,max I Lm

7-2)

D N2
0.6

1
4.5

16.9 V .
1 D N1
0.4

0.4

a ) Vo Vs
b) I Lm

Vo2
(16.9) 2

7.03 A.
Vs DR 4.5(0.6)(6)

iLm

Vs D
4.5(0.6)

1.08 A.
Lm f 10(10) 6 (250, 000)

iLm
7.57 A.
2
i
I Lm ,min I Lm Lm 6.49 A.
2
D
(0.6)
c) Vo

1.6%
RCf 15(10)(10) 6 (250, 000)
I Lm ,max I Lm

7-3)

D N2
N 2 V o 1 D 3 1 .32

0.145
N1 V s
D
1 D N1
44 .32

a ) Vo Vs
or

N1
6.90
N2

b) I Lm

Vo2
32

0.640 A.
Vs DR 44(0.32)(1)

## iLm 0.4 I Lm 0.4(0.640) 0.256 A.

Lm

Vs D
44(0.32)

184 H .
iLm f (0.256)(300, 000)

## 7-4) Example design

Vs 24 V . Po 40 W . Vo 40 V .
N 2 Vo 1 D

N1 Vs D
Let D 0.4 (arbitrary )
then
N 2 40 1 0.4
N1

0.4
2.5, or
N1 24 0.4
N2
N 2
Vo
40
(2.5) 4.17 A

(1 D) R N1
(1 0.4)40
V 2 402
where R o
40
P
40
Let iLm 40% of I Lm 0.4(4.16) 1.67 A
I Lm

## Let f 100 kHz

VD
24(0.4)
Lm s

57.6 H
iLm f 1.67(100, 000)
C

D
0.4

20 F
40(.005)(100, 000)
Vo
f
Vo

iLm
2
2
V
VD
0 o s
Vs DR 2 Lm f

I Lm ,min I Lm
I Lm ,min

## Vo2 2 Lm f 52 (2)(500)(106 )40, 000

R

11.7
(Vs D) 2
[24(0.385)]2
R 11.7 continuous current
R 11.7 discontinuous current

## 7-6) Switch is closed for DT, current returns to zero at t = t x:

I Lm ,max

Vs DT
Lm

diLm Vo N1

dt
Lm N 2
1
Vo N1 t
V o N
Vs DT
iLm (t )

d iLm ( DT )

(t DT )
Lm N 2 DT
Lm N
Lm
2
V N
V DT
I LM (t t x ) 0 o 1 (t x DT ) s
Lm N 2
Lm
Switch open :

tx

Vs DT N 2

DT
Vo N1

7-7)

N 2
100(.35)(1) 35 V .
N1

a ) Vo Vs D

Vo
1 D
1 .35

0.16%
2
6
Vo
8Lx Cf
8(70)(10) 33(10) 6 (150, 000) 2
Vo 35

1.75 A.
R 20
N
D
.35
iLx Vs 2 Vo
[100(1) 35]
2.17 A.
6
(70)(10) (150, 000)
N1
Lx f
2.17
I Lx ,max 1.75
2.83 A.
2
2.17
I Lx ,min 1.75
0.67 A.
2
V DT
100(.35)
c) iLm s

0.233 A.
Lm
1(10) 3150, 000

b) I Lx

## d ) isw I1 iLm i pri

I sw,max I Lx ,max (1/1) I Lm ,max 2.83 0.233 3.06 A.

7-8)

N 2
1
170(0.3) 5.1 V .
10
N1
Vo
1 D
1 0.3

0.175%
2
6
Vo
8Lx Cf
8(20)(10) 10(10) 6 (500, 000) 2

a ) Vo Vs D

b)
The currents in the converter are shown below. The winding currents are for the windings
in the ideal transformer model, not the physical windings. The physical primary winding
current is the sum of winding #1 and Lm currents.

c) iLm

Vs DT
170(0.3)

0.3 A.
Lm
340(10) 6 500, 000

## Peak energy in Lm : Wmax

P

1
1
2
Lm iLm (340)(10) 6 (0.3) 2 15.3 J
2
2

W
Wf 15.3(10) 6 (500, 000) 7.65 W .
T

7-9)

N 2
N
2
Vo 50

0.625
D

Vs 80
N1
N
1

a ) Vo Vs D
If

N3
1, then D 0.5
N1

N 2 0.625
N

## 2.08 or 1 0.48 (not unique)

N1
0.3
N2

Vo2 502
V 50

10 ; I Lx o
5 A.
P 250
R 10
V (1 D)
50(1 .3)
iLx o

3.5 A.
Lf
100(10) 6100, 000
3.5
I Lx ,min 5
3.25 A. 0 continuous current
2
Vo
1 D
1 0.3
b)

0.058%
2
6
Vo
8 Lx Cf
8(100)(10) 150(10) 6 (100, 000) 2
R

7-10)

N 2

100(0.25)

N1

a ) Vo Vs D

1
5 V.
5

using Lx 20 H ,
Vo
1 D
1 0.25

0.33%
2
6
Vo
8Lx Cf
8(20)(10) 10(10) 6 (375, 000) 2
b)
The currents in the converter are shown below. The winding currents are for the windings
in the ideal transformer model, not the physical windings. The physical primary winding
current is the sum of winding #1 and Lm currents.

c) iLm

Vs DT
100(0.25)

0.20 A.
Lm
333(10) 6 375, 000

## Peak energy in Lm : Wmax

P

1
1
2
Lm iLm (333)(10) 6 (0.2) 2 6.66 J
2
2

W
Wf 6.66(10) 6 (375, 000) 2.5 W .
T

7-11)

N 2
N
1
Vs D 125(0.3)

0.75

Vo
50
N1
N
2
V
50
b) I Lx o
2 A.; I Lx ,min (0.4)(2) 0.8 A.; iLx 2(2 0.8) 2.4 A.
R 25
V (1 D)T
V (1 D )T
50(1 0.3)
iLx o
Lx o

58.3 H .
Lx
iLx
2.4(250, 000)
a ) Vo Vs D

c)

Vo
1 D

C
Vo
8Lx Cf 2

1 D
1 0.3

4.8 F .
6
8(58.3)(10) (0.005)(250, 000) 2
Vo
2
8 Lx
f
Vo

7-12)

Let

N1
1, then D 0.5
N3

## Let D 0.35, then

N1 Vs D (170)(.35)

1.2396
N2
Vo
48
Rounding , let

N1
1.25
N2

Vo N1
48

(1.25) 0.353
Vs N 2
170
Let f 200 kHz , and design for iLx 40% of I Lx

Then D

Lx

Vo (1 D)
48(1 0.353)

124 H
0.4 I Lx f
0.4(3.125)200, 000

where I Lx I o

Po 150

3.125 A.
Vo 48

## Alternatively, solving for the minimum Lx for continuous current ,

I Lx ,min 0 I Lx
Lx ,min

iLx Vo Vo (1 D)

2
R
2 Lx f

(1 D) R (1 0.353)(15.36)

24.9 H
2f
2(200, 000)

where R

Vo2 482

15.36
Po 150

## Lx must be greater than 24.9 H with margin, (e.g ., 25% greater )

making Lx 31 H
Using Lx 124 H ,
C

1 D
1 0.353

1.63 F
6
2
8(124)(10)
(0.01)(200,
000)
Vo
2
8 Lx
f
V
o

7-13)

150 Vs 175 V .
Vo 30 V .
20 Po 50 W 0.667 I o 1.667 A.
Example design :
N
Let 1 1, then D 0.5
N3
Let D 0.3 for Vs 150 V .
Then

N1 Vs D (150)(0.3)

1.5
N2
Vo
30

For Vs 175 V ., D

Vo N1
30

(1.5) 0.35
Vs N 2
175

0.3 D 0.35,
which is an acceptable range of D. Other choices are possible.
Using the design criterion of iLx 40% of I Lx ,
Lx

Vo (1 D)
0.4 I Lx f

## The worst case is for the smallest D and the smallest I Lx .

Letting f 250 kHz (arbitrary ),
30(1 0.3)
Lx
315 H
0.4(0.667)(250, 000)
1 D
1 0.3
C

2.22 F
6
8(315)(10) (0.002)(250, 000) 2
Vo
2
8 Lx
f
Vo
7-14)
The current in the physical primary winding is the sum of i L1 and iLm in the model. The physical
currents in windings 2 and 3 are the same as in the model.

7-15)

N s
D 2(50)(0.5)(0.35) 17.5 V .
N

a ) Vo 2Vs

Vo 17.5

2.19 V .
R
8
V
17.5
iLx o (0.5 D)T
(0.5 0.35)150, 000 0.29 A.
Lx
60(10) 6

b) I Lx

iLx
0.29
2.19
2.33 A.
2
2
i
0.29
I Lx ,min I Lx Lx 2.19
2.04 A.
2
2
Vo
1 2D
1 2(0.35)
c)

0.018%
2
Vo
32 Lx Cf
32(60)(10) 6 39(10) 6 (150, 000) 2
I Lx ,max I Lx

7-16)

7-17)

## Sw1 closed : vP1 Vs 50 vLm Lm

diLm
dt

diLm VLm
50

25(10)3 A / s
3
dt
Lm 2(10)
0.35
2.33 s iLm 25(10)3 2.33(10) 6 58.3 mA.
150, 000
Sw2 closed : vP 2 Vs , VP1 Vs
For DT

diLm
25(10)3 A / s
dt
Both switches open : VP1 0

diLm
0
dt

7-18) The input voltage vx to the filter is Vs(Ns / Np) when either switch is on, and vx is zero when both
switches are off. (See Fig. 7-8.) The voltage across L x is therefore

N s
0 t DT
N

vLx Vs
Vo

DT t T / 2

N
1
T

VLx Vs s DT Vo DT
0
2
T
/
2

N p

N
Vo 2Vs s D
N p

7-19)

Vs

2(1 D)

Vo

N s

N p

24
1
17.1 V .
2(1 0.65)
2

2
o

V
17.12

1.22 A.
Vs R 24(10)

I Lx

N p
2(24)(2) 96 V .
N s

VSw,max 2Vs
7-20)

Vs

2(1 D)

Vo

N s
N / N s 50
V
o p

Vs 2(1 D) 30
N p

## Let D 0.7 ( D 0.5)

N s 50
(2)(1 0.7) 1.0
N p 30
Vo2 502
Vo2
502
R

62.5; I Lx

1.33 A.
Po
40
Vs R 30(62.5)

7-21)

Ps Po
Vs I Lx Vo I o
N p 2(1 D)T

N s

I x I o I Lx

Vs I Lx Vo I Lx

N
Vo Vs S
N
p

N p
2(1 D)
N d

2(1 D)

7-22)
The simulation is run using a Transient Analysis with a restricted time of 3 to 3.02 ms,
representing two periods of steady-state operation. The steady-state output voltage has an average
value of approximately 30 V and peak-to-peak ripple of approximately 600 mV, ignoring the
negative spike. The average transformer primary and secondary currents are 912 mA and 83.5
mA, respectively. The output voltage is lower than the predicted value of 36 V because of the
nonideal switch and diode, mostly from the switch. The output voltage ripple is 2%, matching the
predicted value. The converter would operate much better with a switch that has a lower on
resistance.

30.5V
Output voltage
(3.0041m,30.295)

(3.0200m,30.057)
30.0V

(3.0141m,29.697)

29.5V
3.000ms
3.004ms
3.008ms
V(Output)
AVG(V(Output))

3.012ms

3.016ms

3.020ms

Time

4.0A
Primary current

(3.0200m,912.072m)

2.0A

0A
I(TX1:1)

AVG(I(TX1:1))

200mA

0A

(3.0200m,83.489m)

Secondary current
SEL>>
-200mA
3.000ms
I(TX1:3)

3.005ms
AVG(I(TX1:3))

3.010ms
Time

3.015ms

3.020ms

7-23)
Using a nonideal switch and diode produces lower values for the currents. For i Lx, the maximum,
minimum, and average values in PSpice are 1.446 A, 0.900 A, and 1.17 A, compared to 1.56 A,
1.01 A, and 1.28 A, respectively. However, the peak-to-peak variation in i Lx in PSpice matches
that of the ideal circuit (0.55 A).

2.0A
(3.6286m,900.720m)
(3.6114m,1.4463)

SEL>>
0A
I(Lx)
2.0A

(3.6114m,1.5068)

0A

(3.6287m,603.330m)

-2.0A
I(L1)
2.0A
(3.6114m,1.4463)

0A

(3.6287m,903.647m)

-2.0A
-I(L2)
1.0A
0A

(3.6115m,539.288m)

-1.0A
3.60ms
I(L3)

3.61ms

3.62ms

3.63ms
Time

3.64ms

3.65ms

3.66ms

7-24)
Design for co= -210 and a gain of 20 dB for a cross over frequency of 12 kHz.

## From Eq. 7 85, K 3.73 : co 2 12000 75400 radis

co 75400

K
3.73
R
For gain 20 dB, 2 10
R1
Let R1 1 k , R2 10 k
1
1
C1
4.95 nF ; C2
355 pF
R2 z
p R2

7-25)

## comp 45 (105) 150

comp
150
tan
3.73
2
2
Gain 15 dB 9.5 dB 24.5 dB
K tan

G 1024.5/20 16.8
R2
16.8
R1
Let R1 1 k and R2 16.8 k
C1

K
3.73

7.07 nF
2 f co R2 2 (5000)(16,800)

C2

1
1

508 pF
K 2 f co R2 3.73(2 5000)(16,800)

7-26)
Using Vs = 6 V as in Example 7-8, the frequency response of the open-loop system shows that
the crossover frequency is approximately 16.8 kHz. The phase angle at the crossover frequency is
17, which is much less than the desired value of at least 45. Therefore, the system does not have
the desired degree of stability.

120

Phase
80

40

Magnitude (dB)
(16.814K,16.866)
(16.814K,48.439m)

-40
10Hz
100Hz
DB(V(error))
P(V(error))

1.0KHz

10KHz

Frequency

7-27)
a) A frequency response of the circuit yields Vo -2.5 dB and 103 at 10 kHz.

100KHz

40
Magnitude

-0

(10.000K,-2.5181)

Phase

-40

-80

(10.000K,-102.646)

-120
1.0Hz
10Hz
DB(V(Output))

100Hz
1.0KHz
P(V(Output))
Frequency

10KHz

100KHz

b) With Vp = 3, the gain of the PWM function is 20log10(1/3) = -9.54 dB. The required
gain of the compensated error amplifier is then 2.5 + 9.54 = 12.06 dB, corresponding to a
gain magnitude of 4.0. The phase angle of the compensated error amplifier at the
crossover frequency to give a phase margin of 45 is

## Let R1 =1k, then R 2 = 4 k.

comp
148
tan
3.49
2
2

K tan
C1

K
3.49

13.8 nF
2 f co R2 2 (10,000)(4000)

C2

1
1

1.14 nF
K 2 f co R2 (3.49)2 (10,000)(4000)

c) Referring to Example 7-9, the PSpice simulation results are shown indicating a stable
control system. The switching frequency was not specified, and 50 kHz was used here.
Use initial conditions for the capacitor voltage at 8 V and the inductor current at 2 A.

10

Output voltage

Inductor current
step change

0
0s

0.5ms
V(OUTPUT)
I(L1)

1.0ms

1.5ms
Time

2.0ms

2.5ms

3.0ms

7-28)
a) The gain at 8 kHz is approximately -2.44 dB, and the phase angle is -100.

40
Magnitude

-0

(8.0358K,-2.4358)

Phase

-40

(8.0358K,-100.156)

-80

-120
1.0Hz
10Hz
DB(V(Output))

100Hz
1.0KHz
P(V(Output))
Frequency

10KHz

100KHz

b) This design is for fco = 8 kHz. With Vp = 3, the gain of the PWM function is 20log10(1/3) =
-9.54 dB. The required gain of the compensated error amplifier is then 2.44 + 9.54 = 11.98 dB,
corresponding to a gain magnitude of 3.97. The phase angle of the compensated error amplifier at
the crossover frequency to give a phase margin of 45 is

## Let R1 =1k, then R 2 = 3.97 k.

comp
145
tan
3.17
2
2

K tan
C1

K
3.17

15.9 nF
2 f co R2 2 (8000)(3970)

C2

1
1

1.58 nF
K 2 f co R2 (3.17)2 (8000)(3970)

c) Referring to Example 7-9, the PSpice simulation results are shown indicating a stable
control system. The switching frequency was not specified, and 50 kHz was used here.
Use initial conditions for the capacitor voltage at 8 V and the inductor current at 1.6 A.

10
Output voltage

Inductor current

step change
0
0s
I(L1)

0.5ms
V(Output)

1.0ms

1.5ms

2.0ms

2.5ms

3.0ms

Time

If designing for fco = 10 kHz, the gain of the converter is -4.38 dB, and co = -98. R1 =
1k, R2 = 4.97k, C1 = 9.58 nF, and C2 = 1.07 nF.

7-29)
2

90

195 90
K tan comp
tan
8.68
4
4

## f co 15 kHz co 2 f co 94, 248 rad / s.

20 log10 (G ) 15 dB
G 1015/20 5.62
Using Eq. (7 - 112) and letting R1 1 k
R2

GR1
1.91 k
K

C1

K
16.4 nF
co R2

C2

1
1.89 nF
co R2 K

C3

K
31.3 nF
co R1

R3

co

1
115
KC3

7-30)

20 log10

V p

17.54
20

G 10

7.54

## Using 45 for the phase margin,

comp 45 (140) 185
2

185 90
K tan
6.61
4

## co 2 f co 2 (15, 000) 94, 248 rad / s

Let R1 1 k
R2

2.93 k

C1

K
9.31 nF
co R2

C2

1
1.41 nF
co R2 K

C3

K
27.3 nF
co R1

R3

7-31)

G R1

co

1
151
KC3

1
9.54 dB
3

Using Vs 20 V ,
gain at 10 kHz 9.16 dB co 133
1
gain of pwm 20 log10 9.54 dB
3
Total gain 9.16 9.54 18.7 dB
18.7

G 10 20 8.61

## comp 45 (133) 178

Using equations 7 - 104 and 7 - 112,
K = 5.55
Let R1 1 k , R2 5.55 k
C1 10.3 nF
C2 1.85 nF
C3 37.5 nF
R3 180
100

Magnitude
0

(10.000K,-9.1569)

Phase

-100

-200
1.0Hz
10Hz
DB(V(Output))

(10.000K,-133.095)

100Hz
1.0KHz
P(V(Output))
Frequency

10KHz

100KHz