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Electric Arcs in DC Systems

Characterization, Detection and Extinction

Delft University of Technology


Aditya Shekhar
June 25, 2015

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

1 / 35

Outline
1

Load-side Series Arc Detection in Low Voltage DC Microgrids


Proposed Arc Detection Algorithm
Choice of Filter Time Constants
Impact of Circuit Parameters
Experimental Validation
Bus Transfer Switching with HVDC GIS Disconnector
Experimental Setup and Simulation Model
Parameter Estimation
Recovery and Re-strike Voltage
Analysis of Bus Transfer Experiments
The Big Picture

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

2 / 35

Next Subsection
1

Load-side Series Arc Detection in Low Voltage DC Microgrids


Proposed Arc Detection Algorithm
Choice of Filter Time Constants
Impact of Circuit Parameters
Experimental Validation
Bus Transfer Switching with HVDC GIS Disconnector
Experimental Setup and Simulation Model
Parameter Estimation
Recovery and Re-strike Voltage
Analysis of Bus Transfer Experiments
The Big Picture

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

3 / 35

Fundamental Concept
110

Rdc

Rarc
Iarc

Vdc

Cload

100

L
O
A
D

Vload

Load Voltage (V)

Ldc

Initial electrode dependent


voltage drop to be detected

90
80
70
60

Equivalent Circuit

50
1

4
5
Time (ms)

10

Measured load voltage: drop of 13.3 V.

Detection of series arcs from load voltage drop (plug out).


Selectivity in parallel load.

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

4 / 35

Proposed Arc Detection Algorithm


1
fs 1

Vflp

Fast Low Pass Filter

If V > Vdetect

+
Vload

Slow Low Pass Filter

1
ss 1

Vslp

Detach load to eliminate arc

Band Pass Filter

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

5 / 35

Selectivity for Parallel Loads


Idc

Ldc

Rdc

Vdc

Vcom

Lcab1

Rcab1

Rarc1

IL2

CL1

VL1

Rarc2

IL2

CL2

VL2

Icab1

Lcab2

Rcab2

Icab2

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

Constant
Power

Constant
Power

June 25, 2015

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Validation - Simulation Results


5
Load 2 keeps running
Current (A)

Load 1 selectively
ramped to zero
on arc detection

Arc detected

Load Current 1
Load Current 2

2
Arc extinguished

1
0
1

4
5
Time (ms)

10

105
Load 1 Voltage
Load 2 Voltage
Vslp, Load 1

Voltage(V)

100
95
Vdetect=10 V

90
85

flp=0.0001 s

80
75
1

Vflp, Load 1
slp = 0.001 s

Aditya Shekhar (TU Delft)

4
5
Time (ms)

Electric Arcs in DC Systems

10

June 25, 2015

7 / 35

Next Subsection
1

Load-side Series Arc Detection in Low Voltage DC Microgrids


Proposed Arc Detection Algorithm
Choice of Filter Time Constants
Impact of Circuit Parameters
Experimental Validation
Bus Transfer Switching with HVDC GIS Disconnector
Experimental Setup and Simulation Model
Parameter Estimation
Recovery and Re-strike Voltage
Analysis of Bus Transfer Experiments
The Big Picture

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

8 / 35

Intuitive Understanding: Filter Time Constants


V with Fast LPF Tc=1 ms

14

V with Fast LPF Tc=0.5 ms

14

12

12

10

10

V with Fast LPF Tc=0.1 ms

18
16
14

6
V

=10V

4
6
Time (ms)

Slow LPF Tc=0.01 s


Slow LPF Tc=0.02 s

detect

10

Voltage(V)

Voltage(V)

Voltage(V)

12

Slow LPF Tc=0.03 s

6
4

Slow LPF Tc=0.07 s

2
0

Slow LPF Tc=0.4 s

Slow LPF Tc=0.05 s


Slow LPF Tc=0.1 s

10

4
6
Time (ms)

10

4
6
Time (ms)

10

It would be nice to have:

High value of slow LPF time constant.


Low value of fast LPF time constant.

150 Hz to 1.5 kHz bandpass is chosen nally...

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

9 / 35

Next Subsection
1

Load-side Series Arc Detection in Low Voltage DC Microgrids


Proposed Arc Detection Algorithm
Choice of Filter Time Constants
Impact of Circuit Parameters
Experimental Validation
Bus Transfer Switching with HVDC GIS Disconnector
Experimental Setup and Simulation Model
Parameter Estimation
Recovery and Re-strike Voltage
Analysis of Bus Transfer Experiments
The Big Picture

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

10 / 35

Frequency Domain Analysis


Capacitance= 10 F
Capacitance= 22 F
Capacitance= 47 F
Capacitance= 100 F
Capacitance= 215 F
Capacitance= 464 F
Capacitance= 1000 F

14000

Natural Frequency (Hz)

12000
10000
8000
f

6000

LC

4000
2000
0
0

3.5

400
600
Inductance (H)

Aditya Shekhar (TU Delft)

800

Q=0.25
Q=0.5
Q=1
Q=2
Q=3

3
2.5
2
1.5

= R1

L
C

1
0.5
0
0

200

Magnitude Response
Magnitude Response (|Vc|/||Vi|)

16000

2
3
4
Normalized Frequaency (f/f0)

1000

Electric Arcs in DC Systems

June 25, 2015

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Detection Voltage at Discrete BPF Output


Grid Inductance=47 H, Resistance=0.125

10
5
0

0.5

0.504

10
5
0

0.505

0.5

0.501

0.502
0.503
Time (s)

0.504

10
5
0

0.5

0.505

0.501

0.504

0.505

10
5
0

0.5

0.501

0.502
0.503
Time (s)

0.504

0.505

Grid Inductance=1000 H, Resistance=2

15

Load Capacitance=10 F
Load Capacitance=22 F
Load Capacitance=47 F
Load Capacitance=100 F
Load Capacitance=216 F
Load Capacitance=465 F
Load Capacitance=1000 F

10
5
0

0.502
0.503
Time (s)

Grid Inductance=465 H, Resistance=1

15
Voltage(V)

Voltage(V)

0.502
0.503
Time (s)

Grid Inductance=216 H, Resistance=0.5

15

Voltage(V)

0.501

Grid Inductance=100 H, Resistance=0.25

15
Voltage(V)

Voltage(V)

15

0.5

0.501

0.502
0.503
Time (s)

Aditya Shekhar (TU Delft)

0.504

0.505

Electric Arcs in DC Systems

June 25, 2015

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Maximum Detection Voltage

Voltage to
Band pass
filter

14

12
15

12
10
10
8
5
6
0
10
10
5
Quality Factor

Aditya Shekhar (TU Delft)

Maximum Detection Voltage (V)

Maximum Detection Voltage (V)

10
8
6
4
2

5
0

Natural Frequency (kHz)

Electric Arcs in DC Systems

0
0

4
6
8
Natural Frequency (kHz)

June 25, 2015

10

13 / 35

Detection Boundary

Threshold Voltage = 8 V

10

Detection
Time (ms)

8
Quality Factor

Quality Factor

Voltage to
Band pass
filter

Threshold Voltage = 7 V

10

6
4
2

1
6
4

0.8

2
0.6

0
0

10

4
5
6
7
Natural Frequency (kHz)
Threshold Voltage = 9 V

0
0

10

4
5
6
7
Natural Frequency (kHz)
Threshold Voltage = 10 V

10
0.4

0.2

8
Quality Factor

Quality Factor

10

8
6
4
2
0
0

6
4

Black indicates
no detection

2
1

4
5
6
7
Natural Frequency (kHz)

Aditya Shekhar (TU Delft)

10

0
0

Electric Arcs in DC Systems

4
5
6
Natural Frequency (kHz)

10

June 25, 2015

14 / 35

Next Subsection
1

Load-side Series Arc Detection in Low Voltage DC Microgrids


Proposed Arc Detection Algorithm
Choice of Filter Time Constants
Impact of Circuit Parameters
Experimental Validation
Bus Transfer Switching with HVDC GIS Disconnector
Experimental Setup and Simulation Model
Parameter Estimation
Recovery and Re-strike Voltage
Analysis of Bus Transfer Experiments
The Big Picture

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

15 / 35

Ldc

Real Time Arc Detection


6.2 ms
2
80

2
4
Time (ms)

Voltage (V)

90

Tdetect=2 ms

4
Voltage (V)

L
O
A
D

Vload

5.5 ms
2
80

70

Voltage Across Load Capacitor


Detection Signal from C2000

Threshold Voltage = 8 V
100

90

2
4
Time (ms)

Threshold Voltage = 9 V

100
95

=2.5 ms

detect

=2.8 ms

4.2 ms
2
80

Voltage (V)

detect

Voltage (V)

T
90

90
3

2.3 ms

85

2
80
1

75
4

2
4
Time (ms)

Aditya Shekhar (TU Delft)

70
5

Voltage (V)

Voltage (V)

Cload

100
Tdetect=1.25 ms

Voltage (V)

Iarc
Vdc

Voltage (V)

100

70

Rarc

Threshold Voltage = 7 V

Threshold Voltage = 6 V

70

Rdc

0
10

Time (ms)

Electric Arcs in DC Systems

June 25, 2015

16 / 35

Next Subsection
1

Load-side Series Arc Detection in Low Voltage DC Microgrids


Proposed Arc Detection Algorithm
Choice of Filter Time Constants
Impact of Circuit Parameters
Experimental Validation
Bus Transfer Switching with HVDC GIS Disconnector
Experimental Setup and Simulation Model
Parameter Estimation
Recovery and Re-strike Voltage
Analysis of Bus Transfer Experiments
The Big Picture

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

17 / 35

Bus Transfer in HVDC Substations


Before making DS2, current
(green) flows from feeder 1 to
feeder 2 via busbar coupling (BC).

DS1

DS2

With both DS1 and DS2 closed,


parallel buses share current from
feeder 1 to feeder 2

DS1

DS2

DS1

BC

Feeder 1

Feeder 2

After breaking DS1, current (red)


flows from feeder 1 to feeder 2 via
busbar coupling (BC).

DS2

BC

Feeder 1

Feeder 2

BC

Feeder 1

Feeder 2

Vbus
I2
Itot

R2

L2

VDS

I1
L1

Aditya Shekhar (TU Delft)

R1

Electric Arcs in DC Systems

June 25, 2015

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Experimental Setup
Power
Supply

Bus 1
Inductance

Control
Room

Bus 2
Inductance
Automatic
Grounding
Stick

Manual
Grounding
Stick

Oscilloscope
Box
GIS
Disconnector

Motor
Controller

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

19 / 35

Equivalent Circuit
Ibn
Sn

Lnn Rnn

Itot
Lm

Rm

I1
L1

VC Cnn

Dn

I2

Vout

L2
R2

Vbus

R1
VDS
n=3

Aditya Shekhar (TU Delft)

n=3

Electric Arcs in DC Systems

June 25, 2015

20 / 35

Next Subsection
1

Load-side Series Arc Detection in Low Voltage DC Microgrids


Proposed Arc Detection Algorithm
Choice of Filter Time Constants
Impact of Circuit Parameters
Experimental Validation
Bus Transfer Switching with HVDC GIS Disconnector
Experimental Setup and Simulation Model
Parameter Estimation
Recovery and Re-strike Voltage
Analysis of Bus Transfer Experiments
The Big Picture

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

21 / 35

Developed Graphical User Interface


2.

3.

1.

4.

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

22 / 35

Equivalent Circuits for Analysis


Inductances with GIS Open
Lm

Rm

Lm
Itot

L11

L1
Vbus

Vout
Lnn

R11

R1

Currents and voltages are falling


exponentials.

Aditya Shekhar (TU Delft)

Rm Itot

I2
I1

I1
Rnn

Inductances with GIS Closed

L2

L1

R2
Lds Vbus

R1

VDS

Rds

Currents and voltages are sum of


two exponentials.

Electric Arcs in DC Systems

June 25, 2015

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Inductance Computation
dI
1
dt (1)

dI1
dt (2)

dI
1
dt (n)

Aditya Shekhar (TU Delft)

I1

(1)

I1

(2)

I1

(n)

Vbus

(1)

Vbus (2)

R1

.
.

Electric Arcs in DC Systems

Vbus

(n)

June 25, 2015

24 / 35

Inductance of GIS Disconnector


Lds
0.2
0

Voltage (V)

0.2
0.4
0.6
0.8

Vds
2
L dI
dt + RI2
2
L dI
dt
RI2

1
1.2
0

0.5

1.5

2
2.5
Time (s)

3.5

4.5
4

x 10

Voltage Drop across this due to current gradient must be

removed to estimate the actual arc voltage.

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

25 / 35

Corrected Arc Voltage


0.8

0.6
Voltage (p.u.)

Restrike

Disconnector Voltage
Uarc,fast

0.7

Uarc,lp

0.5
0.4
0.3
0.2
0.1
0
7.4

7.5

Aditya Shekhar (TU Delft)

7.6

7.7

7.8

7.9
Time (s)

Electric Arcs in DC Systems

8.1

8.2

8.3

8.4
x 10

June 25, 2015

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Comparison of Measured and Simulated Results


Simulated Current
Measured Current

600
400
200
0

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045

1500
Capacitor Voltage (V)

Total Current (A)

800

Simulated Capacitor Voltage


Measured Capacitor Voltage
1400
1300
1200
1100

Time (s)

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045


Time (s)

Simulated Buck Output Voltage


Measured Buck Output Voltage

Simulated Bus Voltage


Measured Bus Voltage

300
Voltage (V)

150
Bus Voltage (V)

400

200

100
50
0

200
100

50
100

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045


Time (s)

Time (s)

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

27 / 35

Next Subsection
1

Load-side Series Arc Detection in Low Voltage DC Microgrids


Proposed Arc Detection Algorithm
Choice of Filter Time Constants
Impact of Circuit Parameters
Experimental Validation
Bus Transfer Switching with HVDC GIS Disconnector
Experimental Setup and Simulation Model
Parameter Estimation
Recovery and Re-strike Voltage
Analysis of Bus Transfer Experiments
The Big Picture

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

28 / 35

Derived Analytical Expression


Recovery voltage is the voltage that appears across the electrodes of
the GIS disconnector at the instant of arc extinction.

Restrike Voltage

is the voltage across the disconnector just before the instant of arc reignition.

Vbus =

Itot

I1



Lm

Lin

Lm

Aditya Shekhar (TU Delft)



Lm

Lm

Lm

P

=1

Pn

Lnn



L1

Electric Arcs in DC Systems

Lin

VC

Itot

P3
n


=1

Ibn

nn

Lm

June 25, 2015

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Eect of Capacitor Voltage and Source


Inductance
(a)

(b)

1200

(c)

1200

1200

1000

1000

800

800

Lnn=0.1 mH
Lnn=0.2 mH

1000

Lnn=1.5 mH
Lnn=5.5 mH

Bus Voltage (V)

Bus Voltage (V)

800
600
400

Bus Voltage (V)

Lnn=0.5 mH

600
400

600
400

200

200

200

200
4

4.5
Time (ms)

Aditya Shekhar (TU Delft)

200
4

4.5
Time (ms)

Electric Arcs in DC Systems

200
4

4.5
Time (ms)

June 25, 2015

30 / 35

Eect of Switching Frequency and Source


Inductance
(a)

(b)

700

(c)

700

700

600

600

500

Lnn=0.5 mH

500

500

400

400

Lnn=1.5 mH

400

Lnn=5.5 mH

300
200
100

Bus Voltage (V)

Lnn=0.2 mH

Bus Voltage (V)

Bus Voltage (V)

Lnn=0.1 mH
600

300
200
100

300
200
100

100

100

100

200
4

4.5
Time (ms)

Aditya Shekhar (TU Delft)

200
4

4.5
Bus Voltage (V)

Electric Arcs in DC Systems

200
4

4.5
Time (ms)

June 25, 2015

31 / 35

Next Subsection
1

Load-side Series Arc Detection in Low Voltage DC Microgrids


Proposed Arc Detection Algorithm
Choice of Filter Time Constants
Impact of Circuit Parameters
Experimental Validation
Bus Transfer Switching with HVDC GIS Disconnector
Experimental Setup and Simulation Model
Parameter Estimation
Recovery and Re-strike Voltage
Analysis of Bus Transfer Experiments
The Big Picture

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

32 / 35

Graphical User Interface Developed for Analysis

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

33 / 35

The Big Picture???

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

34 / 35

Thank You!

Aditya Shekhar (TU Delft)

Electric Arcs in DC Systems

June 25, 2015

35 / 35

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