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B.E. 6 - E.C.
Subject: VLSI Technology and Design
Subject Code: 161004
Pre-GTU Assignment
Theory
1. Explain VLSI Design flow using Y-chart.
2. Discuss following approaches (with examples) used to reduce complexity of IC design:
1. Hierarchy,
2. Regularity, 3. Modularity and
4. Locality.
3. iscuss following criteria which are considered to measure the quality of chip design.
1. Testability 2. Yield and manufacturability 3.Reliability 4. Technology updateability
4. Explain the energy band diagram of MOS structure at surface inversion and derive the
expression for the maximum possible depth of the depletion region.
5. Discuss the four components of threshold voltage (VT) in detail.
6. With neat sketch explain gradual channel approximation and derive the equation for drain
current in linear region mode and saturation mode.
7. Effect of channel length modulation and substrate bias on drain current of NMOS
transistor.
8. Derive threshold voltage equation for short channel effect.
9. Discuss MOSFET capacitances in brief.
10. Explain Full-scaling and Constant voltage scaling in detail.
11. Draw circuit of resistive load inverter. Derive VIH, VIL, VOL and VOH for resistive load
inverter.
12. Draw the inverter circuit with depletion type nMOS load. Mention the operating regions
of driver and load transistors for different input voltages. Derive critical voltage points
VOH, VOL and VIL for depletion load nMOS inverter.
13. Draw the CMOS Inverter circuit and Voltage Transfer Characteristic (VTC) for different
operating regions of the nMOS and pMOS transistors. Derive critical voltage points VIL,
VIH.
14. Draw two-input CMOS NOR gate and obtain expression for switching threshold voltage
(Vth). Assume that both NMOS transistors are identical. Similarly, PMOS transistors are
also identical.
15. Explain two input depletion load NOR gate and derive the necessary equations for the
same.
16. Justify importance of transmission gate. Draw six-transistor CMOS transmission gate
implementation of the XOR function. Verify its functionality.
17. Discuss CMOS transmission gate for all operating regions and plot equivalent resistance
of CMOS transmission gate as a function of output voltage.
18. Discuss Ad Hoc testable design techniques
19. List out possible electrical and logical faults observed in the circuit. Define controllability
and observability.
20. Discuss Built-in Self Test (BIST) techniques.
21. Discuss process flow for the fabrication of an n-type MOSFET on p-type silicon.
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22. Why do we need isolation between MOS transistors fabricated on a single chip? Explain

etched field-oxide isolation and LOCOS isolation techniques with diagrams.

23. How will you calculate propagation delay times PHL and PLH for CMOS Inverter?
24. Write a note on CMOS Ring Oscillator circuit.
25. Explain Elmore delay calculation method for complex RC network. Derive the formula
for Elmore delay DN.
26. Draw CMOS negative edge-triggered master-slave D flip-flop and explain its working.
27. Draw CMOS implementation of D latch with two inverters and two CMOS TG gates.
Explain its working.
28. By taking suitable examples, discuss the ratioed and ratio-less dynamic logic circuits.
29. Explain the basic principle of pass transistor circuit. Explain logic 1 transfer and logic
0 transfer.
30. Draw the circuit diagram of Domino CMOS logic gate and discuss it in detail.
31. Discuss dynamic CMOS logic (precharge evaluate logic) with illustration of the
cascading problem in dynamic CMOS logic.
32. What is the need for voltage bootstrapping? Explain dynamic voltage bootstrapping
circuit with necessary mathematical analysis.
33. Explain Latch up problem in CMOS inverter. Mention causes and remedy for avoiding
latch up.
34. Explain On Chip Clock Generation and Distribution.
35. Give comparison between FPGA and CPLD
36. General architecture of FPGA.
37. a) Compare Enhancement MOSFET & Depletion MOSFET.
b) Explain Principle of domino logic circuit.

Examples
a) Consider a MOS system with the following parameters:
tox = 200A ,
GC = - 0.85 V,
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Na = 2*10 cm-3,
Qox = q* 2 *1011 C/cm^2
1) Determine the threshold voltage VT0 under zero bias at room temperature
(T = 300 K). Note that ox = 3.970 and si = 11.7 0.
2) Determine the type (p-type or n-type) and amount of implant.
b) Calculate the threshold voltage VTO at VSB = 0, for a polysilicon gate n-channel MOS
transistor, with the following parameters: Substrate doping density NA =10^16 cm-3,
polysilicon gate density ND = 2 x 10^20 cm-3, gate oxide thickness tox=500 Angstrom
and oxide interface fixed charge density Nox = 4 x 10^10 cm^-2, F( gate) = 0.55V.
Physical constants:
Thermal voltage =KT/q = 0.026 volt
Energy Gap of silicon (Si) =Eg = 1.12 eV
Intrinsic Carrier Concentration of silicon = ni = 1.45 x 1010 cm3
Dielectric constant of vaccume = o = 8.85 x 10-14 F/cm
Dielectric constant of silicon = si = 11.7 x o F/cm
Dielectric constant of silicon dioxide = ox = 3.97 x o F/cm

c) Calculate the threshold voltage for a polysilicon gate nMOS transistor with the following
parameters: NA= 2 x 10^16 cm^-3, ND= 2 x 10^19 cm^-3, tox = 300 x 10^-8 cm, and
Nox= 10^10 cm^-2. Take kT/q = 26 mV, ni = 1.45 x 10 ^10 cm ^-3, q = 1.6 x 10^-19 C,
ox= 3.97 x 8.85 x 10^-14 F/cm, si= 11.7 x 8.85 x 10 ^-14 F/cm.
d) Calculate the threshold voltage VTO under zero bias at room temperature T=300K), for
a polysilicon gate n-channel MOS transistor, with the following arameters: substrate
doping density NA = 1016 cm-3, polysilicon gate doping density ND = 1020 cm-3, tox =
500A, and oxide interface fixed charge density NOX = 2 x 1010 cm-3. Take 0 =
8.85x10-14 F/cm, si = 11.7 x 0F/cm, ox = 3.97 x 0 F/cm.
e) Design of a depletion-load NMOS inverter:
nCox = 30 A/V^2 ,
VT0 = 0.8 V (enhancement-type),
VT0 = - 2.8 V,(depletion-type),
= 0.38 V^1/2,
|2 F| = 0.6 V,
VDD = 5 V.
1) Determine the (W/L) ratios of both transistors such that:
i) the static (DC) power dissipation for Vin= VOH is 250 W, and
ii) VOL = 0.3 V.
2) Calculate VIL and VIH values, and determine the noise margins
f) Consider a CMOS inverter circuit with the following parameters:
VDD = 3.3 V,
For NMOS VTO, n = 0.6 V, nCox = 60 A/V^2, (W/L)n=8
For PMOS VTO, p = - 0.7 V, pCox=25 A/V^2, (W/L)p=12.
Calculate noise margin and Vth of the circuit.
g) Design a resistive load inverter with R = 1k, such that VOL= 0.6V. The enhancement
type nMOS driver transistor has the following parameters:
VDD = 5.0V
VTO = 1.0 V
= 0.2 V^1/2
=0
nCox= 22.0 A/V^2
a. Determine the required aspect ratio, W/L.
b. Determine VIL and VIH.
h) Consider the CMOS inverter, with the following device parameters:
nMOS VTO,n = 0.6 V nCox = 60 A/V2
pMOS VTO,p = -0.8 V pCox = 20 A/V2
Also: VDD = 3V, _ = 0.
a. Determine the (W/L) ratios of the nMOS and the pMOS transistor such that the
switching threshold is Vth = 1.5V.
b. Calculate noise margin.

i) Consider a resistive-load inverter circuit with VDD =5 V, Kn =10A/V2 , VTO=0.8V,

RL=200k,and W/L=4.Calculate the critical Voltages (VOH,VOL,VIL & VIH) on the VTC
and find the noise margins of the circuit.
j) Implement the following Boolean function using CMOS.
F = [(C+D+E) . (B+A)].
Find a equivalent CMOS inverter circuit for simultaneous switching of all inputs, assume
that (W/L)p = 15 for all pMOS transistors and (W/L)n = 10 for all nMOS transistors.
k) Answer the following:
(I)
Implement following Boolean functions using transmission gates
F = BC+BC + BCA
(II)
Draw the Gate level schematic and CMOS Implementation of D-latch.

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Subject Faculties

HOD (E&C)

(1) Nirmal R. Bhalani

(2) Payal Kheradia