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K22P64M120SF5
Rev 4, 11/2014
MK22FX512VLH12
MK22FN1M0VLH12
Performance
Up to 120 MHz ARM Cortex-M4-based core with DSP
instructions delivering 1.25 Dhrystone MIPS per MHz
Memories and memory interfaces
Up to 1 MB program flash memory and 128 KB RAM
Up to 128 KB FlexNVM and 4 KB FlexRAM on
FlexMemory devices
FlexBus external bus interface
System peripherals
Multiple low-power modes; low leakage wakeup unit
Memory protection unit with multi-master protection
16-channel DMA controller
External watchdog monitor and software watchdog
Security and integrity modules
Hardware CRC module
128-bit unique identification (ID) number per chip
Analog modules
Two 16-bit SAR ADCs
Two 12-bit DACs
Three analog comparators (CMP)
Voltage reference
64 QFP
10 x 10 x 1.4 mm Pitch 0.5 mm
Communication interfaces
USB full-/low-speed On-the-Go controller
USB Device Charger detect
Controller Area Network (CAN) module
One SPI module
Three I2C modules
Three UART modules
Secure Digital host controller (SDHC)
I2S module
Timers
Two 8-channel Flex-Timers (PWM/Motor Control)
Two 2-channel Flex-Timers (PWM/Quad Decoder)
Periodic interrupt timers and 16-bit low-power timer
Carrier modulator transmitter
Real-time clock
Programmable delay block
Clocks
3 to 32 MHz and 32 kHz crystal oscillator
PLL, FLL, and multiple internal oscillators
Operating Characteristics
Voltage range: 1.71 to 3.6 V
Flash write voltage range: 1.71 to 3.6 V
Temperature range (ambient): 40 to 105C
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. 20132015 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information 1
Part Number
Memory
Flash (KB)
SRAM (KB)
MK22FX512VLH12
512 KB
128
40
MK22FN1M0VLH12
1 MB
128
40
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type
Description
Resource
Selector
Guide
Solution Advisor
Product Brief
K20PB1
Reference
Manual
K22P64M50SF5RM1
Data Sheet
K22P64M50SF51
Package
drawing
LQFP 64-pin:
98ASS23234W1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2
Freescale Semiconductor, Inc.
System
Internal
and external
watchdogs
Program
flash
RAM
Clocks
Phaselocked loop
Debug
interfaces
DSP
DMA
FlexMemory
Frequencylocked loop
Interrupt
controller
Floating
point
Low-leakage
wakeup
Serial
programming
interface
Low/high
frequency
oscillators
Internal
reference
clocks
Security
and Integrity
CRC
Analog
16-bit ADC
Timers
Communication Interfaces
2
FlexTimers
I C
I S
Carrier
modulator
transmitter
UART
USB OTG
LS/FS/HS
SPI
USB LS/FS
transceiver
Random
number
generator
Analog
comparator
Hardware
encryption
6-bit DAC
Tamper
detect
12-bit DAC
Periodic
interrupt
timers
USB charger
detect
Voltage
reference
Low power
timer
USB voltage
regulator
Programmable
delay block
Human-Machine
Interface (HMI)
GPIO
Independent
real-time
clock
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................8
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 10
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 14
2.2.7 Designing with radiated emissions in mind..........15
2.2.8 Capacitance attributes.........................................15
2.3 Switching specifications...................................................15
2.3.1 Device clock specifications..................................15
2.3.2 General switching specifications......................... 16
2.4 Thermal specifications..................................................... 17
2.4.1 Thermal operating requirements......................... 17
2.4.2 Thermal attributes................................................17
3 Peripheral operating requirements and behaviors.................. 18
3.1 Core modules.................................................................. 18
3.1.1 Debug trace timing specifications........................18
3.1.2 JTAG electricals.................................................. 19
3.2 System modules.............................................................. 22
3.3 Clock modules................................................................. 22
3.3.1 MCG specifications..............................................22
3.3.2 Oscillator electrical specifications........................25
3.3.3 32 kHz oscillator electrical characteristics........... 27
4
Freescale Semiconductor, Inc.
4
5
6
7
8
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
55
150
TSDR
260
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Description
Min.
Max.
Unit
Notes
VHBM
-2000
+2000
VCDM
-500
+500
-100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5
Freescale Semiconductor, Inc.
General
Symbol
Description
Min.
Max.
Unit
VDD
0.3
3.8
IDD
185
mA
VDIO
0.3
5.5
VAIO
Analog1,
0.3
VDD + 0.3
ID
VDDA
25
25
mA
VDD 0.3
VDD + 0.3
VUSB0_DP
0.3
3.63
VUSB0_DM
0.3
3.63
0.3
3.8
VBAT
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
High
Low
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
General
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
VDDA
1.71
3.6
0.1
0.1
0.1
0.1
1.71
3.6
0.7 VDD
0.75 VDD
0.35 VDD
0.3 VDD
0.06 VDD
-5
mA
VBAT
VIH
VIL
VHYS
Input hysteresis
IICDIO
IICAIO
IICcont
3
mA
-5
+5
-25
+25
mA
VODPU
VDD
VDD
VRAM
1.2
VPOR_VBAT
VRFVBAT
Notes
1. All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode
connection to VDD. If VIN is less than VDIO_MIN, a current limiting resistor is required. If VIN greater than VDIO_MIN
(=VSS-0.3V) is observed, then there is no need to provide current limiting resistors at the pads. The negative DC
injection current limiting resistor is calculated as R=(VDIO_MIN-VIN)/|IICDIO|.
2. Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL
and XTAL are analog pins.
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
7
Freescale Semiconductor, Inc.
General
3. All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO_MIN or
greater than VAIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VAIO_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO_MAX)/|
IICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative injection
currents.
4. Open drain outputs must be pulled to VDD.
Description
Min.
Typ.
Max.
Unit
VPOR
0.8
1.1
1.5
VLVDH
2.48
2.56
2.64
VLVW1H
2.62
2.70
2.78
VLVW2H
2.72
2.80
2.88
VLVW3H
2.82
2.90
2.98
VLVW4H
2.92
3.00
3.08
80
mV
1.54
1.60
1.66
VHYSH
VLVDL
VLVW1L
1.74
1.80
1.86
VLVW2L
1.84
1.90
1.96
VLVW3L
1.94
2.00
2.06
VLVW4L
2.04
2.10
2.16
60
mV
VHYSL
Notes
VBG
0.97
1.00
1.03
tLPO
900
1000
1100
Description
8
Freescale Semiconductor, Inc.
Min.
Typ.
Max.
Unit
0.8
1.1
1.5
Notes
General
Description
Min.
Typ
Max.
Unit
VDD 0.5
VDD 0.5
VDD 0.5
VDD 0.5
100
mA
Notes
IOHT
VOL
0.5
0.5
0.5
0.5
100
mA
IOLT
IIND
2,
0.002
0.5
0.002
0.5
PTD7
0.004
VIN = VDD
IIND
VDD = 3.6 V
18
26
VDD = 3.0 V
12
19
VDD = 2.5 V
13
VDD = 1.7 V
50
IOZ
0.25
RPU
20
35
50
RPD
20
35
50
IIND
1.
2.
3.
4.
9
Freescale Semiconductor, Inc.
General
5. Measured at VDD supply voltage = VDD min and Vinput = VDD
Symbol
tPOR
Description
After a POR event, amount of time from the point VDD
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
VLLS0 RUN
VLLS1 RUN
VLLS2 RUN
VLLS3 RUN
LLS RUN
VLPS RUN
STOP RUN
Min.
Max.
Unit
300
183
183
105
105
5.0
4.4
4.4
Notes
Description
Analog supply current
Min.
Typ.
Max.
Unit
Notes
See note
mA
33.57
36.2
mA
33.51
36.1
mA
General
Description
Min.
Typ.
Max.
Unit
Notes
@ 1.8V
@ 3.0V
IDD_RUN
3, 4
46.36
50.1
mA
46.31
49.9
mA
57.4
mA
@ 125C
IDD_WAIT
18.2
mA
IDD_WAIT
7.2
mA
IDD_VLPR
1.21
mA
IDD_VLPR
1.88
mA
IDD_VLPW
0.80
mA
IDD_STOP
0.528
2.25
mA
@ 70C
1.6
mA
@ 105C
5.2
20
mA
@ 40 to 25C
78
700
@ 70C
498
2400
@ 105C
1300
3600
@ 40 to 25C
5.1
15
@ 70C
28
80
@ 105C
124
300
@ 40 to 25C
3.1
7.5
@ 70C
14.5
45
@ 105C
63.5
195
2.0
6.9
32
IDD_VLPS
IDD_LLS
11
Freescale Semiconductor, Inc.
General
Description
Min.
Typ.
Max.
Unit
30
112
@ 40 to 25C
1.25
2.1
@ 70C
6.5
18.5
@ 105C
37
108
0.745
1.65
6.03
18
37
108
0.268
1.25
3.7
15
22.9
95
0.19
0.22
0.49
0.64
2.2
3.2
@ 70C
Notes
@ 105C
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
IDD_VBAT
@ 1.8V
@ 40 to 25C
@ 70C
@ 105C
0.68
0.8
1.2
1.56
3.6
5.3
0.81
0.96
1.45
1.89
4.3
6.33
@ 3.0V
@ 40 to 25C
@ 70C
@ 105C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus 40 Mhz and FlexBus clock, and 24 MHz flash clock. MCG configured for
PEE mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
12
Freescale Semiconductor, Inc.
General
5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI
mode.
6. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
7. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
8. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
9. Includes 32kHz oscillator current and RTC operation.
2.2.5.1
13
Freescale Semiconductor, Inc.
General
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
0.1550
23
dBV
VRE2
50150
27
dBV
VRE3
150500
28
dBV
VRE4
5001000
14
dBV
IEC level
0.151000
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated EmissionsTEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
14
Freescale Semiconductor, Inc.
General
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated EmissionsTEM Cell and
Wideband TEM Cell Method
Description
Min.
Max.
Unit
CIN_A
pF
CIN_D
pF
Description
Min.
Max.
Unit
120
MHz
20
MHz
Bus clock
60
MHz
FlexBus clock
50
MHz
fFLASH
Flash clock
25
MHz
fLPTMR
LPTMR clock
25
MHz
Notes
VLPR
mode1
fSYS
MHz
fBUS
Bus clock
MHz
15
Freescale Semiconductor, Inc.
General
Description
Min.
Max.
Unit
FB_CLK
FlexBus clock
MHz
fFLASH
Flash clock
0.8
MHz
fERCLK
16
MHz
LPTMR clock
25
MHz
fLPTMR_pin
16
MHz
MHz
fI2S_MCLK
12.5
MHz
fI2S_BCLK
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
Description
Min.
Max.
Unit
Notes
1.5
Bus clock
cycles
1, 2
100
ns
16
ns
100
ns
Bus clock
cycles
Slew disabled
1.71 VDD 2.7V
12
ns
ns
36
ns
24
ns
Slew enabled
Slew disabled
16
Freescale Semiconductor, Inc.
General
Description
Min.
Max.
Unit
12
ns
ns
36
ns
24
ns
Notes
Slew enabled
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. 75 pF load
5. 15 pF load
Description
Min.
Max.
Unit
TJ
40
125
TA
Ambient temperature
40
105
Symbol
Description
Unit
Single-layer (1s)
RJA
Thermal resistance,
junction to ambient
(natural convection)
C/W
Four-layer (2s2p)
RJA
Thermal resistance,
junction to ambient
(natural convection)
C/W
Single-layer (1s)
RJMA
Thermal resistance,
C/W
junction to ambient
(200 ft./min. air speed)
Notes
17
Freescale Semiconductor, Inc.
Board type
Symbol
Description
Unit
Notes
Four-layer (2s2p)
RJMA
Thermal resistance,
C/W
junction to ambient
(200 ft./min. air speed)
RJB
Thermal resistance,
junction to board
C/W
RJC
Thermal resistance,
junction to case
C/W
JT
Thermal
characterization
parameter, junction to
package top outside
center (natural
convection)
C/W
Notes
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental ConditionsNatural Convection (Still Air), or EIA/
JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental ConditionsForced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal
Test Method Environmental ConditionsJunction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard,
Microcircuits, with the cold plate temperature used for the case temperature. The
value includes the thermal resistance of the interface material between the top of
the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal
Test Method Environmental ConditionsNatural Convection (Still Air).
18
Freescale Semiconductor, Inc.
Description
Min.
Max.
Unit
Tcyc
Clock period
Frequency dependent
(limited to 50 MHz)
MHz
Twl
ns
Twh
ns
Tr
ns
Tf
ns
Ts
Data setup
ns
Th
Data hold
ns
Unit
TRACECLK
Tr
Tf
Twh
Twl
Tcyc
TRACE_CLKOUT
Ts
Th
Ts
Th
TRACE_D[3:0]
Description
Min.
Max.
Operating voltage
2.7
3.6
V
MHz
10
25
19
Freescale Semiconductor, Inc.
Description
Min.
Max.
50
1/J1
ns
Boundary Scan
50
ns
20
ns
10
ns
J4
ns
J5
20
ns
J6
2.6
ns
J7
25
ns
J8
25
ns
Unit
J3
J9
ns
J10
ns
J11
17
ns
J12
17
ns
J13
100
ns
J14
ns
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
MHz
Boundary Scan
10
20
40
1/J1
ns
Boundary Scan
50
ns
25
ns
12.5
ns
J2
J3
J4
ns
J5
20
ns
J6
ns
J7
25
ns
Description
Min.
Max.
Unit
J8
25
ns
J9
ns
J10
1.4
ns
J11
22.1
ns
J12
22.1
ns
J13
100
ns
J14
ns
J2
J3
J3
TCLK (input)
J4
J4
TCLK
J5
Data inputs
J6
Data outputs
J8
Data outputs
J7
Data outputs
21
Freescale Semiconductor, Inc.
TCLK
J9
TDI/TMS
J10
TDO
J12
TDO
J11
TDO
TCLK
J14
J13
TRST
22
Freescale Semiconductor, Inc.
Description
Min.
Typ.
Max.
Unit
fints_ft
32.768
kHz
fints_t
31.25
39.0625
kHz
Iints
Notes
20
0.3
0.6
%fdco
0.2
0.5
%fdco
fdco_t
0.5
%fdco
fdco_t
0.3
%fdco
fintf_ft
MHz
fintf_t
MHz
25
Iintf
floc_low
(3/5) x
fints_t
kHz
floc_high
(16/5) x
fints_t
kHz
31.25
39.0625
kHz
20
20.97
25
MHz
40
41.94
50
MHz
60
62.91
75
MHz
80
83.89
100
MHz
23.99
MHz
47.97
MHz
71.99
MHz
,2
1
FLL
ffll_ref
fdco
3, 4
640 ffll_ref
Mid range (DRS=01)
1280 ffll_ref
Mid-high range (DRS=10)
1920 ffll_ref
High range (DRS=11)
2560 ffll_ref
5, 6
732 ffll_ref
Mid range (DRS=01)
1464 ffll_ref
Mid-high range (DRS=10)
23
Freescale Semiconductor, Inc.
Description
Min.
Typ.
Max.
Unit
95.98
MHz
180
150
ms
48.0
120
MHz
1060
600
2.0
4.0
MHz
Notes
2197 ffll_ref
High range (DRS=11)
2929 ffll_ref
Jcyc_fll
tfll_acquire
ps
PLL
fvco
Ipll
Ipll
fpll_ref
Jcyc_pll
Jacc_pll
fvco = 48 MHz
120
ps
75
ps
fvco = 48 MHz
1350
ps
600
ps
1.49
2.98
Dunl
4.47
5.97
Dlock
tpll_lock
10-6
150
+ 1075(1/
fpll_ref)
10
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (fdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
24
Freescale Semiconductor, Inc.
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
3.6
IDDOSC
IDDOSC
Notes
1
32 kHz
600
nA
4 MHz
200
8 MHz (RANGE=01)
300
16 MHz
950
24 MHz
1.2
mA
32 MHz
1.5
mA
32 kHz
7.5
4 MHz
500
8 MHz (RANGE=01)
650
16 MHz
2.5
mA
24 MHz
3.25
mA
32 MHz
mA
Cx
2, 3
Cy
2, 3
RF
10
200
RS
2, 4
25
Freescale Semiconductor, Inc.
1.
2.
3.
4.
5.
Description
Min.
Typ.
Max.
Unit
0.6
VDD
0.6
VDD
Notes
3.3.2.2
Symbol
Description
Min.
Typ.
Max.
Unit
fosc_lo
32
40
kHz
fosc_hi_1
MHz
fosc_hi_2
32
MHz
fec_extal
50
MHz
tdc_extal
40
50
60
750
ms
250
ms
0.6
ms
ms
tcst
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
26
Freescale Semiconductor, Inc.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
Symbol
Description
Min.
Typ.
Max.
Unit
VBAT
Supply voltage
1.71
3.6
100
Cpara
pF
Vpp1
0.6
RF
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.3.3.2
Symbol
fosc_lo
tstart
Description
Min.
Typ.
Max.
Unit
Oscillator crystal
32.768
kHz
1000
ms
700
VBAT
mV
2, 3
Notes
27
Freescale Semiconductor, Inc.
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 20. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
thvpgm8
thversscr
Notes
7.5
18
13
113
ms
104
904
ms
416
3616
ms
Notes
3.4.1.2
Symbol
Description
Min.
Typ.
Max.
Unit
0.5
ms
trd1blk512k
1.8
ms
trd1sec4k
100
tpgmchk
95
trdrsrc
40
tpgm8
90
150
tersblk128k
110
925
ms
tersblk512k
435
3700
ms
15
115
ms
ms
tersscr
tpgmsec1k
FlexNVM devices
2.2
ms
trdonce
30
tpgmonce
90
tersall
870
7400
ms
tvfykey
30
Description
Min.
Typ.
Max.
Unit
Notes
200
tswapx02
90
150
tswapx04
90
150
tswapx08
30
32 KB EEPROM backup
70
ms
tpgmpart128k
75
ms
70
tsetram32k
32 KB EEPROM backup
0.8
1.2
ms
tsetram64k
64 KB EEPROM backup
1.3
1.9
ms
tsetram128k
2.4
3.1
ms
175
275
teewr8bers
32 KB EEPROM backup
385
1700
teewr8b64k
64 KB EEPROM backup
475
2000
teewr8b128k
650
2350
175
275
32 KB EEPROM backup
385
1700
teewr16b64k
64 KB EEPROM backup
475
2000
teewr16b128k
650
2350
360
550
32 KB EEPROM backup
630
2000
teewr32b64k
64 KB EEPROM backup
810
2250
teewr32b128k
1200
2650
29
Freescale Semiconductor, Inc.
3.4.1.3
Symbol
Description
IDD_PGM
IDD_ERS
3.4.1.4
Symbol
Min.
Typ.
Max.
Unit
Average current
adder during high
voltage flash
programming
operation
3.5
7.5
mA
Average current
adder during high
voltage flash erase
operation
1.5
4.0
mA
Reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
50
years
tnvmretp1k
20
100
years
nnvmcycp
Cycling endurance
10 K
50 K
cycles
50
years
tnvmretd1k
20
100
years
nnvmcycd
Cycling endurance
10 K
50 K
cycles
Data Flash
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
50
years
20
100
years
20 K
50 K
cycles
nnvmcycee
2
3
nnvmwree16
70 K
175 K
writes
nnvmwree128
630 K
1.6 M
writes
nnvmwree512
2.5 M
6.4 M
writes
nnvmwree2k
10 M
25 M
writes
nnvmwree4k
20 M
50 M
writes
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40C Tj 125C.
3. Write endurance represents the number of writes to each FlexRAM location at -40C Tj 125C influenced by the
cycling endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem.
Minimum and typical values assume all byte-writes to FlexRAM.
30
Freescale Semiconductor, Inc.
3.4.1.5
When the FlexNVM partition code is not set to full data flash, the EEPROM data set
size can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that
can be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout
the entire lifetime of a given application. The EEPROM endurance equation and graph
shown below assume that only one configuration is ever used.
Writes_subsystem =
Write_efficiency n nvmcycee
where
Writes_subsystem minimum number of writes to each FlexRAM location for
subsystem (each subsystem can have different endurance)
EEPROM allocated FlexNVM for each EEPROM subsystem based on
DEPART; entered with the Program Partition command
EEESPLIT FlexRAM split factor for subsystem; entered with the Program
Partition command
EEESIZE allocated FlexRAM based on DEPART; entered with the Program
Partition command
Write_efficiency
0.25 for 8-bit writes to FlexRAM
0.50 for 16-bit or 32-bit writes to FlexRAM
nnvmcycee EEPROM-backup cycling endurance
31
Freescale Semiconductor, Inc.
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
EP1
fSYS/2
MHz
EP1a
fSYS/8
MHz
EP2
2 x tEZP_CK
ns
EP3
ns
EP4
ns
EP5
ns
EP6
ns
EP7
18
ns
EP8
ns
EP9
12
ns
32
Freescale Semiconductor, Inc.
EZP_CK
EP3
EP2
EP4
EZP_CS
EP9
EP7
EP8
EZP_Q (output)
EP5
EP6
EZP_D (input)
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
Frequency of operation
FB_CLK
MHz
FB1
Clock period
20
ns
FB2
11.5
ns
FB3
0.5
ns
FB4
8.5
ns
FB5
0.5
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
33
Freescale Semiconductor, Inc.
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
FB_CLK
MHz
1/FB_CLK
ns
Frequency of operation
Notes
FB1
Clock period
FB2
13.5
ns
FB3
ns
FB4
13.7
ns
FB5
0.5
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
34
Freescale Semiconductor, Inc.
FB1
FB_CLK
FB3
FB5
FB_A[Y]
Address
FB4
FB2
FB_D[X]
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
35
Freescale Semiconductor, Inc.
FB1
FB_CLK
FB2
FB3
FB_A[Y]
FB_D[X]
Address
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB4
FB_BEn
FB5
AA=1
FB_TA
FB_TSIZ[1:0]
AA=0
TSIZ
3.6 Analog
36
Freescale Semiconductor, Inc.
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
3.6
VDDA
Supply voltage
-100
+100
mV
VSSA
Ground voltage
-100
+100
mV
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
VADIN
Input voltage
VREFL
31/32 *
VREFH
VREFL
16-bit mode
10
pF
CADIN
RADIN
RAS
Input
capacitance
Input series
resistance
Analog source
resistance
(external)
VREFH
fADCK
1.0
18.0
MHz
fADCK
2.0
12.0
MHz
Crate
5
20.000
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
5
37.037
461.467
Ksps
37
Freescale Semiconductor, Inc.
Description
Conditions
Typ.1
Min.
Max.
Unit
Notes
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
3.6.1.2
Symbol
Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
0.215
1.7
mA
38
Freescale Semiconductor, Inc.
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
fADACK
Description
ADC
asynchronous
clock source
Sample Time
TUE
DNL
INL
EFS
EQ
ENOB
Conditions1
Min.
Typ.2
Max.
Unit
Notes
ADLPC = 1, ADHSC = 0
1.2
2.4
3.9
MHz
ADLPC = 1, ADHSC = 1
2.4
4.0
6.1
MHz
tADACK =
1/fADACK
ADLPC = 0, ADHSC = 0
3.0
5.2
7.3
MHz
ADLPC = 0, ADHSC = 1
4.4
6.2
9.5
MHz
LSB4
LSB4
LSB4
LSB4
VADIN =
VDDA5
Total
unadjusted error
12-bit modes
6.8
<12-bit modes
1.4
2.1
Differential nonlinearity
12-bit modes
0.7
1.1 to
+1.9
<12-bit modes
0.2
12-bit modes
1.0
<12-bit modes
0.5
12-bit modes
5.4
<12-bit modes
1.4
1.8
16-bit modes
1 to 0
13-bit modes
0.5
Integral nonlinearity
Full-scale error
Quantization
error
Effective
number of bits
0.3 to 0.5
2.7 to
+1.9
0.7 to
+0.5
bits
Avg = 32
12.8
14.5
Avg = 4
11.9
13.8
Avg = 4
SINAD
THD
Signal-to-noise
plus distortion
See ENOB
Total harmonic
distortion
bits
bits
12.2
13.9
11.4
13.1
Avg = 32
bits
LSB4
dB
dB
-94
dB
Spurious free
dynamic range
-85
82
95
78
dB
dB
90
Avg = 32
Table continues on the next page...
Kinetis K22F Sub-Family Data Sheet, Rev4, 11/2014.
39
Freescale Semiconductor, Inc.
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
Description
EIL
Input leakage
error
Conditions1
Typ.2
Min.
Max.
IIn RAS
Unit
Notes
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
VTEMP25
Temp sensor
slope
1.55
1.62
1.69
mV/C
Temp sensor
voltage
25 C
706
716
726
mV
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
ENOB
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
10
11
12
Figure 16. Typical ENOB vs. ADC_CLK for 16-bit differential mode
40
Freescale Semiconductor, Inc.
14.00
13.75
13.50
13.25
13.00
ENOB
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
10
11
12
Figure 17. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
3.6
IDDHS
200
IDDLS
20
VAIN
VSS 0.3
VDD
VAIO
20
mV
CR0[HYSTCTR] = 00
mV
CR0[HYSTCTR] = 01
10
mV
CR0[HYSTCTR] = 10
20
mV
CR0[HYSTCTR] = 11
30
mV
VH
VCMPOh
Output high
VDD 0.5
VCMPOl
Output low
0.5
tDHS
20
50
200
ns
tDLS
80
250
600
ns
40
delay2
INL
0.5
0.5
LSB3
DNL
0.3
0.3
LSB
41
Freescale Semiconductor, Inc.
0.08
0.07
0.06
HYSTCTR
Setting
0.05
00
0.04
01
10
11
0.03
0.02
0.01
0
0.1
0.4
0.7
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Figure 18. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
42
Freescale Semiconductor, Inc.
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1.3
1.6
1.9
Vin level (V)
2.2
2.5
2.8
3.1
Figure 19. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
VDACR
Reference voltage
1.13
3.6
1
2
CL
100
pF
IL
mA
Notes
43
Freescale Semiconductor, Inc.
3.6.3.2
Symbol
Description
Min.
Typ.
Max.
Unit
150
700
Notes
tDACLP
100
200
tDACHP
15
30
0.7
Vdacoutl
DAC output voltage range low highspeed mode, no load, DAC set to 0x000
100
mV
Vdacouth
DAC output voltage range high highspeed mode, no load, DAC set to 0xFFF
VDACR
100
VDACR
mV
INL
LSB
DNL
LSB
DNL
LSB
0.4
0.8
%FSR
Gain error
0.1
0.6
%FSR
60
90
dB
TCO
3.7
V/C
TGE
0.000421
%FSR/C
AC
100
V/yr
Rop
250
SR
1.
2.
3.
4.
5.
V/s
1.2
1.7
0.05
0.12
-80
CT
BW
3dB bandwidth
dB
kHz
550
40
44
Freescale Semiconductor, Inc.
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
45
Freescale Semiconductor, Inc.
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
25
-40
55
85
105
125
Temperature C
Description
Min.
Max.
Unit
Notes
VDDA
Supply voltage
1.71
3.6
Operating temperature
range of the device
100
nF
1, 2
TA
Temperature
CL
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range
of the device.
46
Freescale Semiconductor, Inc.
Description
Min.
Typ.
Max.
Unit
Notes
Vout
1.1915
1.195
1.1977
Vout
1.1584
1.2376
Vout
1.193
1.197
Vstep
0.5
mV
Vtdrift
80
mV
80
1, 2
Ibg
VLOAD
Load regulation
current = 1.0 mA
200
Tstup
100
Vvdrift
mV
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Description
Min.
Max.
Unit
Notes
TA
Temperature
50
Description
Voltage reference output with factory trim
Min.
Max.
Unit
Notes
1.173
1.225
3.7 Timers
See General switching specifications.
47
Freescale Semiconductor, Inc.
Description
Min.
Typ.
Max.
Unit
VDP_SRC
0.5
0.7
0.8
2.0
VLGC
IDP_SRC
10
13
IDM_SINK
50
100
150
RDM_DWN
14.25
24.8
VDAT_REF
0.25
0.33
0.4
Description
Min.
Typ.1
Max.
Unit
VREGIN
2.7
5.5
IDDon
125
186
IDDstby
1.1
10
IDDoff
650
nA
120
mA
ILOADstby
mA
VReg33out
3.3
3.6
Notes
Typ.1
Max.
Unit
2.1
2.8
3.6
2.1
3.6
COUT
1.76
2.2
8.16
ESR
100
ILIM
290
mA
Symbol
Description
Run mode
Notes
Standby mode
VReg33out
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
Frequency of operation
30
MHz
2 x tBUS
ns
Notes
DS1
DS2
(tSCK/2) 2 (tSCK/2) + 2
ns
DS3
(tBUS x 2)
2
ns
DS4
(tBUS x 2)
2
ns
DS5
8.5
ns
DS6
ns
49
Freescale Semiconductor, Inc.
Table 38. Master mode DSPI timing (limited voltage range) (continued)
Num
Description
Min.
Max.
Unit
DS7
15
ns
DS8
ns
Notes
DSPI_PCSn
DS3
DSPI_SCK
DS7
(CPOL=0)
DSPI_SIN
DS1
DS2
DS4
DS8
First data
DSPI_SOUT
Data
Last data
DS5
First data
DS6
Data
Last data
Description
Operating voltage
Min.
Max.
Unit
2.7
3.6
15
MHz
4 x tBUS
ns
(tSCK/2) 2
(tSCK/2) + 2
ns
Frequency of operation
DS9
DS10
DS11
17.4
ns
DS12
ns
DS13
ns
DS14
ns
DS15
16
ns
DS16
16
ns
50
Freescale Semiconductor, Inc.
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
Notes
1.71
3.6
15
MHz
4 x tBUS
ns
DS1
DS2
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS3
(tBUS x 2)
4
ns
DS4
(tBUS x 2)
4
ns
DS5
10
ns
DS6
-4.5
ns
DS7
20.5
ns
DS8
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
51
Freescale Semiconductor, Inc.
DSPI_PCSn
DS3
DS4
DS8
DS7
(CPOL=0)
DS1
DS2
DSPI_SCK
DSPI_SIN
Data
First data
DSPI_SOUT
Last data
DS5
DS6
First data
Data
Last data
Description
Operating voltage
Frequency of operation
Min.
Max.
Unit
1.71
3.6
7.5
MHz
8 x tBUS
ns
(tSCK/2) - 4
(tSCK/2) + 4
ns
DS9
DS10
DS11
20
ns
DS12
ns
DS13
ns
DS14
ns
DS15
19
ns
DS16
19
ns
DSPI_SS
DS10
DS9
DSPI_SCK
DS15
(CPOL=0)
DSPI_SOUT
DS12
First data
DS13
DSPI_SIN
DS16
DS11
Last data
Data
DS14
First data
Data
Last data
52
Freescale Semiconductor, Inc.
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
S1
40
ns
S2
45%
55%
MCLK period
S3
80
ns
S4
45%
55%
BCLK period
S5
15
ns
S6
ns
S7
15
ns
S8
ns
S9
15
ns
S10
ns
53
Freescale Semiconductor, Inc.
S1
S2
S2
I2S_MCLK (output)
S3
I2S_BCLK (output)
S4
S4
S6
S5
I2S_FS (output)
S10
S9
I2S_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
S11
80
ns
S12
45%
55%
MCLK period
S13
4.5
ns
S14
ns
S15
18
ns
S16
ns
S17
4.5
ns
S18
ns
S19
21
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
54
Freescale Semiconductor, Inc.
S11
S12
I2S_BCLK (input)
S12
S15
S16
I2S_FS (output)
S13
I2S_FS (input)
S14
S15
S19
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
3.8.9.1
Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 44. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
S1
40
ns
S2
45%
55%
MCLK period
S3
80
ns
S4
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
15
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1
ns
S7
15
ns
S8
ns
S9
20.5
ns
S10
ns
55
Freescale Semiconductor, Inc.
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
S11
80
ns
S12
45%
55%
MCLK period
S13
5.8
ns
S14
ns
S15
23.5
ns
S16
ns
S17
5.8
ns
S18
ns
25
ns
S19
valid1
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
56
Freescale Semiconductor, Inc.
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
3.8.9.2
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 46. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
S1
62.5
ns
S2
45%
55%
MCLK period
S3
250
ns
S4
45%
55%
BCLK period
S5
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
45
ns
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
ns
S7
45
ns
S8
ns
S9
ns
S10
ns
57
Freescale Semiconductor, Inc.
S1
S2
S2
I2S_MCLK (output)
S3
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S4
S6
S5
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
3.6
S11
250
ns
S12
45%
55%
MCLK period
S13
30
ns
S14
ns
S15
S16
ns
S17
ns
S18
ns
72
ns
S19
30
valid1
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
58
Freescale Semiconductor, Inc.
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
I2S_TX_FS/
I2S_RX_FS (input)
S19
S14
S15
S16
S15
S16
I2S_TXD
S17
S18
I2S_RXD
3.8.9.3
3.8.9.3.1
Ordering parts
Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to freescale.com and perform a part number search for
the following device numbers: PK22 and MK22
3.8.9.4
3.8.9.4.1
Part identification
Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
3.8.9.4.2
Format
Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
59
Freescale Semiconductor, Inc.
Description
Values
Qualification status
K##
Kinetis family
K22
Key attribute
D = Cortex-M4 w/ DSP
F = Cortex-M4 w/ DSP and FPU
FFF
Silicon revision
Z = Initial
(Blank) = Main
A = Revision after main
V = 40 to 105
C = 40 to 85
PP
Package identifier
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LF = 48 LQFP (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
MP = 64 MAPBGA (5 mm x 5 mm)
LK = 80 LQFP (12 mm x 12 mm)
LL = 100 LQFP (14 mm x 14 mm)
MC = 121 MAPBGA (8 mm x 8 mm)
DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
LQ = 144 LQFP (20 mm x 20 mm)
MD = 144 MAPBGA (13 mm x 13 mm)
CC
5 = 50 MHz
7 = 72 MHz
10 = 100 MHz
12 = 120 MHz
15 = 150 MHz
16 = 168 MHz
18 = 180 MHz
Packaging type
3.8.9.4.4
32 = 32 KB
64 = 64 KB
128 = 128 KB
256 = 256 KB
512 = 512 KB
1M0 = 1 MB
2M0 = 2 MB
Example
60
Freescale Semiconductor, Inc.
3.8.9.4.5
In an effort to save space, small package devices use special marking on the chip.
These markings have the following format:
Q ## C F T PP
This table lists the possible values for each field in the part number for small packages
(not all combinations are valid):
Field
Description
Values
Qualification status
##
Kinetis family
2# = K21/K22
Speed
H = 120 MHz
K = 512 KB + Flex
1 = 1 MB
V = 40 to 105
PP
Package identifier
LL = 100 LQFP
MC = 121 MAPBGA
LQ = 144 LQFP
MD = 144 MAPBGA
DC = 121 XFBGA
This tables lists some examples of small package marking along with the original part
numbers:
Original part number
MK22FX512VLH12
3.8.9.5
3.8.9.5.1
Example
61
Freescale Semiconductor, Inc.
Description
1.0 V core supply
voltage
3.8.9.5.2
Min.
0.9
Max.
1.1
Unit
V
Example
Description
Min.
3.8.9.5.3
Max.
130
Unit
A
Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
3.8.9.5.3.1
Example
3.8.9.5.4
Description
Input capacitance:
digital pins
Min.
Max.
7
Unit
pF
Definition: Rating
62
Freescale Semiconductor, Inc.
3.8.9.5.4.1
Example
Min.
3.8.9.5.5
40
Description
Max.
0.3
Unit
1.2
30
20
10
Operating rating
Measured characteristic
3.8.9.5.6
ing
rat
e
Op
g
tin
in.
(m
ra
in.
t (m
ax
t (m
n
me
rat
e
Op
ire
qu
r
ing
ing
rat
e
Op
.)
en
rem
re
i
qu
rat
e
Op
ing
g
tin
ra
ax
(m
Fatal range
Fatal range
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
lin
nd
Ha
n.)
mi
g(
in
rat
g(
ng
li
nd
Ha
in
rat
.)
x
ma
Fatal range
Handling range
Fatal range
No permanent failure
3.8.9.5.7
63
Freescale Semiconductor, Inc.
During normal operation, dont exceed any of the chips operating requirements.
If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
3.8.9.5.8
Example 1
3.8.9.5.8.2
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
A
Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
64
Freescale Semiconductor, Inc.
Dimensions
5000
4500
4000
TJ
IDD_STOP (A)
3500
150 C
3000
105 C
2500
25 C
2000
40 C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
3.8.9.5.9
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Value
Unit
TA
Ambient temperature
25
VDD
3.3
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawings document number:
If you want the drawing for this package
64-pin LQFP
98ASS23234W
169-pin MAPBGA
98ASA00628D
65
Freescale Semiconductor, Inc.
Pinout
5 Pinout
5.1 K22 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
64
LQFP
Pin Name
NOTE
The analog input signals ADC0_DP2 and ADC0_DM2
on PTE2 and PTE3 are available only for K21 and K22
devices and are not present on K10 and K20 devices.
The TRACE signals on PTE0, PTE1, PTE2, PTE3, and
PTE4 are available only for K11, K12, K21, and K22
devices and are not present on K10 and K20 devices.
If the VBAT pin is not used, the VBAT pin should be left
floating. Do not connect VBAT pin to VSS.
The FTM_CLKIN signals on PTB16 and PTB17 are
available only for K11, K12, K21, and K22 devices and is
not present on K10 and K20 devices. For K22D devices
this signal is on ALT7, and for K22F devices, this signal
is on ALT4.
The FTM0_CH2 signal on PTC5/LLWU_P9 is available
only for K11, K12, K21, and K22 devices and is not
present on K10 and K20 devices.
The I2C0_SCL signal on PTD2/LLWU_P13 and
I2C0_SDA signal on PTD3 are available only for K11,
K12, K21, and K22 devices and are not present on K10
and K20 devices.
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
RTC_
CLKOUT
PTE0
ADC1_SE4a
ADC1_SE4a
PTE0
UART1_TX
TRACE_
CLKOUT
I2C1_SDA
PTE1/
LLWU_P0
ADC1_SE5a
ADC1_SE5a
PTE1/
LLWU_P0
UART1_RX
TRACE_D3
I2C1_SCL
VDD
VDD
VDD
VSS
VSS
VSS
USB0_DP
USB0_DP
USB0_DP
66
Freescale Semiconductor, Inc.
EzPort
Pinout
64
LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
USB0_DM
USB0_DM
USB0_DM
VOUT33
VOUT33
VOUT33
VREGIN
VREGIN
VREGIN
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
ADC0_DP0/
ADC1_DP3
10
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
ADC0_DM0/
ADC1_DM3
11
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
ADC1_DP0/
ADC0_DP3
12
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
ADC1_DM0/
ADC0_DM3
13
VDDA
VDDA
VDDA
14
VREFH
VREFH
VREFH
15
VREFL
VREFL
VREFL
16
VSSA
VSSA
VSSA
17
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
18
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
19
XTAL32
XTAL32
XTAL32
20
EXTAL32
EXTAL32
EXTAL32
21
VBAT
VBAT
VBAT
22
PTA0
JTAG_TCLK/
SWD_CLK/
EZP_CLK
PTA0
UART0_CTS_ FTM0_CH5
b
JTAG_TCLK/
SWD_CLK
EZP_CLK
23
PTA1
JTAG_TDI/
EZP_DI
PTA1
UART0_RX
FTM0_CH6
JTAG_TDI
EZP_DI
24
PTA2
JTAG_TDO/
TRACE_
SWO/
EZP_DO
PTA2
UART0_TX
FTM0_CH7
JTAG_TDO/ EZP_DO
TRACE_SWO
25
PTA3
JTAG_TMS/
SWD_DIO
PTA3
UART0_RTS_ FTM0_CH0
b
26
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
27
PTA5
DISABLED
PTA5
USB_CLKIN
FTM0_CH2
CMP2_OUT
I2S0_TX_
BCLK
JTAG_TRST_
b
28
PTA12
CMP2_IN0
CMP2_IN0
PTA12
CAN0_TX
FTM1_CH0
I2C2_SCL
I2S0_TXD0
FTM1_QD_
PHA
29
PTA13/
LLWU_P4
CMP2_IN1
CMP2_IN1
PTA13/
LLWU_P4
CAN0_RX
FTM1_CH1
I2C2_SDA
I2S0_TX_FS
FTM1_QD_
PHB
30
VDD
VDD
VDD
JTAG_TMS/
SWD_DIO
FTM0_CH1
NMI_b
EZP_CS_b
67
Freescale Semiconductor, Inc.
Pinout
64
LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
31
VSS
VSS
VSS
32
PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2
FTM_CLKIN0
33
PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0
FTM_CLKIN1
34
RESET_b
RESET_b
RESET_b
35
PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8
ADC0_SE8/
ADC1_SE8
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_
PHA
36
PTB1
ADC0_SE9/
ADC1_SE9
ADC0_SE9/
ADC1_SE9
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_
PHB
37
PTB2
ADC0_SE12
ADC0_SE12
PTB2
I2C0_SCL
UART0_RTS_
b
FTM0_FLT3
38
PTB3
ADC0_SE13
ADC0_SE13
PTB3
I2C0_SDA
UART0_CTS_
b
FTM0_FLT0
39
PTB16
DISABLED
PTB16
UART0_RX
FTM_CLKIN0 FB_AD17
EWM_IN
40
PTB17
DISABLED
PTB17
UART0_TX
FTM_CLKIN1 FB_AD16
EWM_OUT_b
41
PTB18
DISABLED
PTB18
CAN0_TX
FTM2_CH0
I2S0_TX_
BCLK
FB_AD15
FTM2_QD_
PHA
42
PTB19
DISABLED
PTB19
CAN0_RX
FTM2_CH1
I2S0_TX_FS
FB_OE_b
FTM2_QD_
PHB
43
PTC0
ADC0_SE14
ADC0_SE14
PTC0
SPI0_PCS4
PDB0_
EXTRG
FB_AD14
I2S0_TXD1
44
PTC1/
LLWU_P6
ADC0_SE15
ADC0_SE15
PTC1/
LLWU_P6
SPI0_PCS3
UART1_RTS_ FTM0_CH0
b
FB_AD13
I2S0_TXD0
45
PTC2
ADC0_SE4b/
CMP1_IN0
ADC0_SE4b/
CMP1_IN0
PTC2
SPI0_PCS2
UART1_CTS_ FTM0_CH1
b
FB_AD12
I2S0_TX_FS
46
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_PCS1
UART1_RX
FTM0_CH2
CLKOUT
I2S0_TX_
BCLK
47
VSS
VSS
VSS
48
VDD
VDD
VDD
49
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
UART1_TX
FTM0_CH3
FB_AD11
CMP1_OUT
50
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
I2S0_RXD0
FB_AD10
CMP0_OUT
51
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN0
PTC6/
LLWU_P10
SPI0_SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
FB_AD9
I2S0_MCLK
52
PTC7
CMP0_IN1
CMP0_IN1
PTC7
SPI0_SIN
USB_SOF_
OUT
I2S0_RX_FS
FB_AD8
53
PTC8
ADC1_SE4b/
CMP0_IN2
ADC1_SE4b/
CMP0_IN2
PTC8
FTM3_CH4
I2S0_MCLK
FB_AD7
54
PTC9
ADC1_SE5b/
CMP0_IN3
ADC1_SE5b/
CMP0_IN3
PTC9
FTM3_CH5
I2S0_RX_
BCLK
FB_AD6
55
PTC10
ADC1_SE6b
ADC1_SE6b
PTC10
I2C1_SCL
FTM3_CH6
I2S0_RX_FS
FB_AD5
56
PTC11/
LLWU_P11
ADC1_SE7b
ADC1_SE7b
PTC11/
LLWU_P11
I2C1_SDA
FTM3_CH7
I2S0_RXD1
FB_RW_b
68
Freescale Semiconductor, Inc.
ALT7
EzPort
LPTMR0_
ALT1
FTM0_CH2
FTM2_FLT0
Pinout
64
LQFP
Pin Name
Default
57
PTD0/
LLWU_P12
DISABLED
58
PTD1
ADC0_SE5b
59
PTD2/
LLWU_P13
60
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
PTD0/
LLWU_P12
SPI0_PCS0
UART2_RTS_ FTM3_CH0
b
FB_ALE/
FB_CS1_b/
FB_TS_b
PTD1
SPI0_SCK
UART2_CTS_ FTM3_CH1
b
FB_CS0_b
DISABLED
PTD2/
LLWU_P13
SPI0_SOUT
UART2_RX
FTM3_CH2
FB_AD4
I2C0_SCL
PTD3
DISABLED
PTD3
SPI0_SIN
UART2_TX
FTM3_CH3
FB_AD3
I2C0_SDA
61
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI0_PCS1
UART0_RTS_ FTM0_CH4
b
FB_AD2
EWM_IN
62
PTD5
ADC0_SE6b
ADC0_SE6b
PTD5
SPI0_PCS2
UART0_CTS_ FTM0_CH5
b
FB_AD1
EWM_OUT_b
63
PTD6/
LLWU_P15
ADC0_SE7b
ADC0_SE7b
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FB_AD0
FTM0_FLT0
64
PTD7
DISABLED
PTD7
CMT_IRO
UART0_TX
FTM0_CH7
ADC0_SE5b
EzPort
FTM0_FLT1
69
Freescale Semiconductor, Inc.
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2/LLWU_P13
PTD1
PTD0/LLWU_P12
PTC11/LLWU_P11
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Revision History
PTB18
ADC0_DP0/ADC1_DP3
40
PTB17
ADC0_DM0/ADC1_DM3
10
39
PTB16
ADC1_DP0/ADC0_DP3
11
38
PTB3
ADC1_DM0/ADC0_DM3
12
37
PTB2
VDDA
13
36
PTB1
VREFH
14
35
PTB0/LLWU_P5
VREFL
15
34
RESET_b
VSSA
16
33
PTA19
VREF_OUT/CMP1_IN5/CMP0_IN5/ADC1_SE18
32
41
PTA18
31
VREGIN
VSS
PTB19
30
42
VDD
29
VOUT33
PTA13/LLWU_P4
PTC0
28
43
PTA12
27
USB0_DM
PTA5
PTC1/LLWU_P6
26
44
PTA4/LLWU_P3
25
USB0_DP
PTA3
PTC2
24
45
PTA2
23
VSS
PTA1
PTC3/LLWU_P7
22
46
PTA0
21
VDD
VBAT
VSS
20
47
EXTAL32
19
PTE1/LLWU_P0
XTAL32
VDD
18
48
DAC0_OUT/CMP1_IN3/ADC0_SE23
17
PTE0
6 Revision History
The following table provides a revision history for this document.
70
Freescale Semiconductor, Inc.
Revision History
Date
Substantial Changes
11/2012
5/2013
08/2013
11/2014
71
Freescale Semiconductor, Inc.