ANNA UNIVERSITY: CHENNAI - 600 025

B.E./B.Tech. DEGREE EXAMINATIONS, Nov. /Dec. - 2014

REGULATIONS: R-2013

THIRD SEMESTER
(Common to: B.E. Electrical and Electronics Engineering/ B.E. Electronics and
Instrumentation Engineering/ B.E. Instrumentation and Control Engineering)
EE 6311 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

Duration: 3 Hours

Max. Marks: 100

1. (a) Design a logic circuit to realize the function F = AB + CD using NAND gates
only. Draw truth table for the same and verify it experimentally.

(50)

(b) Design and construct a full adder using suitable logic gates and verify its truth
table.

(50)

2. (a) Design and construct a full subtractor using suitable logic gates and verify its truth
table.

(50)

(b) Design and construct a binary to gray code converter using suitable logic gates and
verify its truth table.

(50)

3. (a) Design and construct a half adder using suitable logic gates and verify its truth
table.

(50)

(b) Design and construct a BCD to excess-3 code converter using suitable logic gates
and verify its truth table.

(50)

4. (a) Design and construct a half subtractor using suitable logic gates and verify its truth
table.
(b)

(50)
Design and construct an excess-3 code to BCD code converter using suitable

logic gates and verify its truth table.

(50)

5. (a) Design and construct a gray to binary code converter using suitable logic gates and
verify its truth table.

(50)

(b) Implement the function F = AC + AC using NOR gates only. Construct truth
table for the same and verify the results experimentally.

(50)

6. (a) Design and implement a 3-bit even parity generator using suitable logic gates and
verify its truth table.

(50)

(b) Design and implement a 3-to-8 decoder using suitable logic gates and verify its
truth table.

(50)

7. (a) Design and implement a parity checker circuit which receives 3 bit message and
an odd parity bit as inputs using suitable logic gates. Also verify its truth table.

(50)

(b) Design and implement an 8-to-3 encoder using suitable logic gates and verify its
truth table.

8. Design and implement an asynchronous/ripple 4-bit up counter using JK-FFs.

(50)

(100)

9. Design and implement an asynchronous/ripple mod-10 up counter using JK-FFs.(100)

10. Design and implement an asynchronous/ripple mod-12 up counter using JK-FFs.(100)

11. Design and implement a synchronous 3-bit up counter using JK-FFs.

(100)

12. Construct a 4-bit parallel in serial out (PISO) shift register.

(100)

13. (a) Construct a 4-bit serial in serial out (SISO) right and left shift register.
(b) Construct a 4-bit serial in parallel out (SIPO) shift register.

14. (a) Design an inverting amplifier of gain 5 using IC 741.

(50)
(50)

(50)

(b) Design an integrator circuit using IC 741. Consider the input waveform to be sine
waveform & square waveform.

15. (a) Design a non-inverting amplifier of gain 5 using IC 741.

(50)

(50)

(b) Design a differentiator circuit using IC 741. Consider the input waveform to be
sine waveform & square waveform.

(50)

16. (a) Design & construct an astable multivibrator to generate the square waveform using
IC555.

(50)

(b) Design and implement a 4 x 1 MUX using suitable logic gates & verify its
function table.

(50)

17. (a) Design & construct a monostable multivibrator to generate the rectangular pulse
waveform using IC 555.

(50)

(b) Design & implement a 1 x 4 DEMUX using suitable logic gates & verify its
function table.

(50)

18. (a) Design & construct a frequency multiplier using NE565 PLL.
(b) Design an inverting amplifier of gain 10 using IC 741.

(50)
(50)

19. (a) Design & construct an astable multivibrator to generate 1 kHz square waveform
using IC 555.

(50)

(b) Design a non-inverting amplifier of gain 10 using IC 741.

(50)

20. (a) Design & construct a monostable multivibrator to generate 1 kHz square
waveform using IC 555.

(50)

(b) Design a differentiator circuit using IC 741. Consider the input waveform to be
sine waveform & square waveform.

Marks Allocation:
Aim & Procedure

10

Circuit Diagram & Design

35

Connection & Observation

35

Result & Graph

10

Viva-voce

10

Total Marks

100

(50)