Current Programmed Control of a Single Phase

Two-Switch Buck-Boost Power Factor Correction

Circuit
Gert K. Andersen, Frede Blaabjerg
Aalborg University, Institute of Energy Technology, Denmark
gka@iet.auc.dk

Abstract- This paper presents a new Current Pro-
grammed Control (CPC) technique for the cascaded two
switch buck-boost converter suitable as a low-cost Power
Factor Correction (pfc) rectifier in a variable speed motor
drive. This new C P C technique, which is an extension of
the conventional CPC method, enables variable output dc-
voltage and is therefore suitable in a Pulse Amplitude Mod-
ulated (PAM) motor drive or as an universal input power
supply. The CPC method is very simple and requires only a
constant current reference without any changes at the tran-
sition between boost and buck operating mode and the line
current is practically unaffected by the topology mode shift.
The presented control technique is verified by simulations
and experimental results and compliance with IEC 61000-3-
2 class A is achieved. The experimental setup is based on a
commercial C P C IC for dc-dc converters.
I. INTRODUCTION
be 0 2 d 5 1/2 or 1/2 2 d 5 1 depending on the control
strategy which will be shown later. Limit cycle, hysteresis
or bang-bang current control is a simple technique which
is sensitive towards noise in the same manner as CPC and
this technique also requires two current reference genera-
tors[l4]. In addition, hysteresis control, in its most simple
structure, has a variable switching frequency. Borderline
control is basically a hysteresis control technique where the
lower boundary is zero. In addition there exist some types
of control techniques which requires no direct current ref-
erence and are therefore relative immune towards input
voltage distortions[151,[161. Compliance with IEC-61000-
3-2 depends strongly on the choice of switching frequency
and switching inductance for CPC whereas ACC and limit
cycle control are able to comply with IEC-61000-3-2 re-
gardless (practically) of the switching frequency and the

R EGULATIONS like IEC-61000-3-2 demand some sort switching inductor. A summary of these statements are
of input current shaping for single phase equipment [l]. listed in Table I.
Active current shaping is usually used in the power range
around 2 kW in order to reduce the volume of the converter CPC is an interesting control method when costs and
and the converter usually consists of a conventional diode complexity must be minimized at the expense of line cur-
bridge followed by a dc-dc switch-mode converter which rent performance.
shapes the current. An active power factor correction (pfc)
This paper describes a new simple CPC technique with
circuit with variable output dc-voltage as a supply in a low- constant command current and without ramp compensa-
cost adjustable speed induction motor drive is interesting
tion for the two-switch buck-boost pfc converter capable
from a drive-design point of view because there exists only
of complying with IEC-61000-3-2. The output dc-voltage
high switching frequency in the rectifier. The pfc control can be varied by adjusting the command current and the
technique in a low-cost motor drive must be simple and
application used here is a pfc dc voltage supply for a PAM
robust.
inverter. Since no commercial IC exists for controlling this
There exist a variety of control techniques for switch mode
converter topology a control strategy based upon existing
converters and power factor correction circuits and most of CPC ICs is developed and tested in the laboratory.
these techniques are supported by commercial and avail-
able ICs for the basic converter topologies like boost, buck,
11. CURRENTPROGRAMMED CONTROL
buck-boost, push-pull, forward, flyback, sepic, kuk etc. [2],
[3]. Different pfc control techniques are compared in [3]. Current Programmed Control (CPC) has been described
Average Current Control (ACC) is relative immune to- heavily in the literature (cf. [2]-[12]) and the major issue
wards noise because only average signals are used but ACC has been the stability analysis because conventional CPC
requires a current reference generator which may be expen- inherently becomes unstable, when the switch duty cycle
sive. CPC is inherently more sensitive towards noise and is greater than 1/2. Ramp compensation can be added in
circuit layout must be done very carefully but CPC is a sim- order to expand the range of stability. Fig. l a depicts the
ple control technique which provides cycle-by-cycle current basic idea behind CPC for continuous conduction mode.
limiting, and the use of a wave-shaping reference generator The switch is turned on at the beginning of each switch-
can be omitted. Stability of CPC has been subjected to in- ing period and the switch is turned off at the time instant
tense study in the literature (cf. [2]-[12])but stability is not when the inductor or switch current equals the command
an issue if the switch duty cycle is restricted into a range current IC. This kind of C P C is here denoted as Upper-
equal to one half of the switching period. This range can Boundary-Current-Programmed-Control (UBCPC).
0-7803-6618-2/01/$10.000 2001 IEEE 350
 TABLE I
TECHNIQUES
CONTROL FOR P F C CIRCUITS. t FORCONVENTIONAL IMPLEMENTATION. DEPENDS
ON THE NOMINAL POWER LEVEL. DCM:
DISCONTINUOUS CONDUCTION MODE, CCM: CONTINUOUS CONDUCTION MODE.

1 Control 11 Frequency t I Operating I Line Current I Cost I Complexity I

Technique Mode Harmonics
Average Constant DCM+CCM Low High High
Current
Peak Constant DCM+CCM Low/ Medium Medium
Current Medium
Current Constant DCM+CCM Low/ Low Low
Clamping Medium
Hysteresis Variable DCM+CCM Low Medium Medium
Borderline Variable Borderline Low Low Medium
Automatic Constant DCMSCCM Medium/High Low Low

4 4

O T 2 T t 0 T 2 T t
4 b) Fig. 2. Two switch Buck-boost converter topology.

Fig. 1. Waveforms of inductor current ZL and the switch control

signal q for a) Upper-Boundary-CPC and b) Down-Boundary-
CPC 111. CONVERTER
TOPOLOGY

Single phase Power Factor Correction (pfc) in the power

Fig. l b shows another CPC technique where the switch
is turned off at the beginning of each switching period and
the switch is turned on a t the time instant when the in-
ductor current drops to the command current I,. This
kind of CPC is here denoted as Down-Boundary-Current-
Programmed-Control (DBCPC).
UBCPC correspond to the conventional CPC technique
used in the literature. UBCPC has inherently an over-
current protection and the average inductor current per
switching period is always lower than the command cur-
rent. In contrary, DBCPC needs an additional over-current
protection which can be realized by a single comparator.
The average inductor current per switching period is al-
ways higher than the command current for DBCPC. Since
UBCPC detects the current during the on-time of the
switch the switch current can be measured which is not
possible in DBCPC because DBCPC detects the current
during the off-time of the switch. Detecting the switch cur-
rent enables switch protection and the current detecting re-
sistor has lower omich losses because the current only flows
during the on-time. Premature detection of the switch in-
stant can be a problem when detecting the switch current
because the switch current is the sum of the inductor cur-
rent and the diode reverse recovery current during turn-on.
Since DBCPC only detects the current during the off-time
of the switch the noise problems related to reverse recovery
current are eliminated. Both UBCPC and DBCPC will be
used in this paper.
35 1
range around 2 (kW) is usually achieved by a conventional
boost converter. If the dc-voltage has to be varied accord-
ing to the actual operating point a buck-boost or buck type
of converter must be utilized. The two switch buck-boost
rectifier shown in Fig 2 is found to the most promising
buck-boost topology in [13] for single phase power fac-
tor correction with variable dc-voltage at the power level
around 2 kW and this topology is therefore selected for
analysis in this paper. This converter is described in [17].
The converter has two operating modes: a buck mode
and a boost mode. Buck mode occurs when the rectified
voltage vref is higher than the dc-voltage U&, and boost
mode occur when the rectified voltage is lower than the
dc-voltage. The boost switch (sz) is turned off constantly
in buck mode and only the buck switch (SI) is modulated
in buck mode. The buck switch is turned on constantly
in boost mode and only the boost switch is modulated in
boost mode. A disadvantage of the buck-boost topology is
the need for a mode detection function.
Previously, no reported CPC technique has been adapted
to the present buck-boost topology and commercially con-
trol ICs are only available for UBCPC. The developed CPC
technique will be described here and is shown in Fig. 3.
When the converter operates as a boost converter UBCPC
is used with a constant current command and without ramp
compensation which means that the duty cycle is limited
to 1/2. The inductor current ripple decreases to zero as the
rectified voltage increases towards the dc-voltage because
the on state inductor voltage becomes zero. The boost
 steady-state
waveform \

(W+Z)T wT T t
4

Perturbed

Fig. 3. Simulated waveform at Vd,= 250 V. Top: rectified voltage

(v,,,), dc-voltage ( v d , ) and converter mode (mode). Middle:
Inductor current ( i ~ )and bottom: duty cycles.

switch duty cycle also drops to zero. (W+i?))T wT T t

The average input current per switch period increases

from the zero crossing towards the point where the dc- Fig. 4. Definition of waveforms for a) UBCPC and b) DBCPC.
voltage and the rectified voltage becomes equal and the
converter shifts to buck mode. If UBCPC is used in the
buck mode then the average input current per switch pe- and the current at the switching instant i ~ ( w Tis)
riod will decrease when converter shifts from boost mode
to buck mode if the same current command is used which i ~ ( u r T )= i~(O)+m,wT * (1)
introduces low order harmonics. If DBCPC is used in the i ~ ( w T-) i~(0)
w = (2)
buck mode then the average input current per switch pe- m,T
riod will continue to increase as it did in boost mode. Thus,
:$ TTQp,,p A
, nQpDp Or_ im ,--,, where i~(0) is the current at the beginning of the switching
. . m1 . m. .. .
.. .. . . . .
AI VUWL w aiiu UYWA w mc UDGU ALL UUUD~ auu U U L ~iuvus
period i'he current. at. the end or the switching
I
period
respectively and the command current is constant then the
becomes
average input current per switch period will be unaffected
by the topology mode shift. Fig. 3 also shows the duty
cycles and it appears that the buck duty cycle decreases
ZL(T) = i~(urT)+m,uT + (3)
smoothly from unity at the topology mode shift but the (4)
buck switch duty cycle is higher than 1/2 in the entire
buck range. Conventional CPC without ramp compensa- Thus in steady state (m, = M,, mu = Mu,
w = W,U =
tion becomes unstable when the duty cycle exceeds 1/2 and U ) the volt-second balance yields
the next section will describe the stability in a generalized
manner regardless if UBCPC or DBCPC is used.
0 = M,WT+M,UT + (5)
IV. STABILITY
The stability range of CPC is generalized here and the
- derivations is based on the simple model as presented in [2].
This equation shows the volt-second balance in steady
This known model assumes constant current slopes and ne-
state, where the error is zero. In the ideal case the entire
glects the effects of the modulator. The analysis assumes
range of switch duty cycle can be utilized without stability
that the current slopes (man, m , f f ) and the command cur-
problems but these ideal considerations are not sufficient in
rent I , are constant during a switch period.
reality because stability becomes a problem due to noise,
delays and other nonideal effects.
The slope before the switching instant is denoted m,
The stability will be calculated and analysed by intro-
and the slope after the switching instant is denoted mu
ducing a small perturbation ~ ( 0of) the initial inductor
and, consequently, the corresponding duration are denoted
current i~(0)(cf. Fig. 4). The current becomes
w and U respectively. Fig. 4 show the definition s of the
inductor current steady state and perturbed waveforms in iL(o) = I,(o) + E , l ( 0 ) where JE,~(o)J IIL(o)l (7)
UBCPC (Fig. 4a) and in DBCPC (Fig. 4b).
Where IL(O) is the ideal steady state inductor current
At first the ideal case is shown where the error is zero at the beginning and at the end of a switching switching
352
 ~
TABLE I1
STABILITY
FOR UBCMC A N D DBCMC.
period. It should be noted that the error relates to the
deviation from steady state operation. The current error at
the switching instant and at the end Q ( T )of the switching
period are
where G denotes the perturbed value of w. Equation
(8) shows the relation between the initial error and the
error after a switching period. After n-switching periods
the error can be written as
where
When n increases towards infinity the error becomes
Thus, the stability is determined by the variable p which
demands W < 0.5 but there has been no assumption on
whether W is the switch duty cycle D or the complement
of the switch duty Q = 1 - D cycle. Table I1 depicts the
stability range without ramp compensation for UBCMC
and DBCMC respectively.
The generalized description shows that the stability
range is inverted when changing between UBCMC and
DBCMC. Thus, stable operation with duty cycles greater
than 0.5 can be achieved without ramp compensation by
using DBCMC.
V. REALIZATION
Fig. 5 depicts the control diagram of the developed CPC
technique. The control is based on a commercial CPC con-
trol IC for dc-dc converters with limited duty cycle. In
order to implement the DBCPC technique when the con-
verter operates in buck mode the error signal and the gate
signal are both inverted. The error signal is inverted in
buck mode by the multiplier. The signal to the multiplier
from the mode signal is unity in boost mode and is equal to
-1 in buck mode. Thus the multiplier has no effect in boost
mode. The logic on the output makes the buck switch
353
Fig. 5. Control diagram.
Fig. 6 . Simulated waveforms at U&= 250 v. Top Inductor current
and the reference current. Middle: Error current and topology
mode signal. Bottom: Error current to the comparator.
turned on in the entire boost mode and the boost switch
turned off in the entire buck mode.
Fig. 6 shows simulated waveforms at v d c =250 V and fig.
7 shows measured waveforms at Vd, =250 V. The bottom
plot shows the error signal feed to the current compara-
tor and the inversion of the error signal in buck mode is
obvious.
VI. RESULTS
Simulation and experimental results are presented and
compared. Table I11 depicts the nominal system parame-
ter used. It should be noted that no design optimization
has been done in order to select the values listed in table 111.
Fig. 8 shows the inductor current, the rectified voltage,
the dc-voltage and the topology mode signal. It appears
how the converter shifts between UBCPC and DBCPC
when the rectified voltage signal crosses the dc-voltage sig-
nal.
Fig. 9 and 10 shows simulated and measured waveforms
at v d c =220 V respectively, and Fig. 11 and 12 shows simu-
lated and measured waveforms at V d c =250 v respectively.
From fig. 6-12 it can be seen that simulations and mea-
suremente exhibit similar waveforms and verifies the func-
tionality of this CPC technique developed t o the two-switch
buck-boost converter. The line current is practically unaf-
 lek 1.00MWS 2 6 ACqS
If ] i
....:.. .... . > , . . : ..... : . . . . . . . . . . .

--
<-
.a
I ........... ._I

I II I
( I ) :4.1

5.00 V M1.00ms Line/ 1O.OV

1 Fig. 9. Simulated waveforms a t u d c = 220 V. Top: Mode signal and
inductor current. Bottom: Line current.
Ref3 10.0mV 1.00ms

Fig. 7 Measured waveforms a t U&= 250 V. Top: Inductor current

(5 A/div) and the reference current. Middle: Error current and
topology mode signal (2 A/div). Bottom. Error current t o t h e
TeK
comperator (2 A/div). 500kS/s
T _ 5_2 Acqs
_..- 1 -..-1

I ' '

TABLE 111
System parameters for the buck-boost converter

Parameter Value Unit

L 600 pH
fs 28 kHz
RLoad 100 R
Lf 400 pH
c.f 4 PF
c dc 470 pF
vdc,nom 320 V
Rine 230 v,,,
fhp 50 Hz
Fig 10 Measured waveforms at U&= 220 V Top: Topology mode
signal (High:buck and 1ow:boost). Middle. Inductor current at
2 A/div Bottom. Line current at 2 A/div.
Tek 500kS/s 2 0 ACqS
.. ..... - -T ....I ...

1
I, , : t

Chl 5 0 0 mV Ch2 5 OOmV M2 .OOms L i n e 1 2.7 V

Ch3 5.OOV rSm 10.0mVR

Fig. 11. Simulated waveforms a t U&= 250 V. Top: Mode signal and
Fig. 8. Measured waveforms a t v d c =200 V. Top: Inductor current. inductor current. Bottom: Line current.
Bottom: Rectified voltage, dc-voltage and mode signal.

354

Fig. 12. Measured waveforms at U,,= 250 V. Top: Topology mode
signal (High:buck and 1ow:boost). Middle: Inductor current at
2 A/div. Bottom: Line current at 2 A/div.
Stairs:lec61000-3-2limits circles:Measured
3r
0 10 20 30
Harmonic number n
Harmonicnumber n
Fig. 13. Harmonic spectra of t h e line current and the IEC 61000-3-2
limits. Top: T h e harmonic current for t h e measurement in fig.
10. Bottom: T h e harmonic current for the measurement in fig.
12.
fected by the topology mode shift. The small disturbance
in the line current at the topology shift is due to the fact
that the input filter is exposed to a load step because the
buck switch current shifts between continuous and discon-
tinuous as the converter shifts between boost and buck.
Additional damping of the input filter can be added in
order to decrease this disturbance. The dc-voltage can di-
rectly be controlled by the command current which in total
makes it a simple pfc technique.
Fig. 13 shows the harmonic currents for the measure-
ments in fig. 10 & 12 and the limits set by IEC 61000-3-2.
It appears that the this control method complies with IEC
61000-3-2 in both cases.
VII. CONCLUSION
A new Current Programmed Control technique has been
developed to the cascaded two switch buck-boost pfc con-
verter which use constant command current and without
ramp compensation. The control circuit is build on a com-
mercial CPC IC for dc-dc converters with a maximum duty
cycle at 1/2. This new control technique enables a simple
low-cost control circuit for the two switch buck-boost con-
verter which complies with IEC-61000-3-2. This new sim-
ple pfc circuit has inherent inrush and over current protec-
tion.
The new CPC technique described and considered in this
paper is a generalization of the conventional CPC technique
which can be used in many other applications directly. Sim-
ulations and experimental results verify the functionality of
the developed CPC technique where the stability range can
be shifted between 0 5 d 5 1/2 or 1/2 5 d 5 1 without
introducing ramp compensation.
The developed control technique can be advanced by
adding ramp compensation in order to expand the range
of stability. The command current could be modulated to
emulate the rectified voltage in order to provide high power
factor performance.
I VIII. ACKNOWLEDGMENTS
The authors wish to thank the Power Electronics Labo-
ratory at the Department of Electronics and Informatics at
the University of Padova in Italy where the experimental
part of this paper has been carried out.
40 REFERENCES
P a r t 3.2: Limits- Limits for harmonic current emissions (equip-
ment input cuwent 516 A per phase), IEC 61000-3-2, Interna-
tional Standard, Edition 1.2, 1998-04
Robert W. Erickson, Fundamentals of Power Electronics, Chap-
man & Hall, 1997, ISBN 0-412-08541-0.
L. Rossetto, G. Spiazzi, P. Tenti, Control techniques for power
factor correction converters, P E M C 94, Warsaw, Poland, pp.
1310-1318, 1994.
R. D. Middlebrook Modeling Cuwent-Programmed Buck and
Boost Regulators, IEEE Transactions on Power Electronics, Vol.
4,No. 1, January, 1989, pp. 36-52.
Carlos A. Canesin, and Ivo Barbi Analysis and design of constant-
frequency peak-cuwent-controlled high-power-factor boost rectifier
with slope compensation, IEEE A P E C 1996, San Jose, USA, Vol
2, pp. 807-813.
Dragan MaksimoviC Design of the Clamped-Cuwent High-Power-
Factor Boost Rectifier, IEEE Transactions on Industrial Appli-
cations, Vol. 31, No. 5 , September/October, 1995, pp. 986-992.
Joel P. Gregner, C. Q. Lee Linear Peak Cuwent Mode Control:
A Simple Active Power Factor Correction Control Technique For
Continuous Conduction Mode, IEEE PESC 1996, Baveno, Italy,
Vol 1, pp. 196-202.
Richard Redl, Brian P. Erisman Reducing Distortion in Peak-
Current-Controlled Boost Power-Factor Correctors, IEEE CIEP
1994, Puebla, Mexico, pp. 92-100.
K. Mahabir, G. Verghese, J . Thottuvelil, A. Heyman Linear av-
eraged and sampled data models f o r larqe siqnal control of hiqh
power factor AD-DC converters, I E E E PESC 1990, pp. 372-381.
[lo] David J . Perreault, George C. Verghese Time-Varyzng Eflects
in Models for Cuwent-Mode Control, IEEE PESC 1995, Atlanta,
USA, Vol 1, pp. 621-628.
[ll] Erik A. Mayer and Roger J. King Previously Unobserved Eflects
of Delay on Current-Mode Control, IEEE PESC 1999.
[12] Yen-Wu Lo, and Roger J . King Sampled-Data Modeling of the
Averaged-Input Current-Mode- Controlled Buck Converter, IEEE
Transactions on Power Electronics, Vol. 14, No. 5 , September,
1999, pp. 918-927.
[13] Gert K. Andersen Average Current Control of a Buck+Boost
PFC Rectifier for Low Cost Motor Drives, IEEE NORPIE/2000,
day three.
(141 Manjusha Dawande, Gopal K. Dubey, Bang-Bang Current Con-
trol with Predecided Switching Frequency for Switch-Mode Recti-
355
 fiers, IEEE Transactions on Industrial Electronics, Vol. 46, No.
1, February 1999, pp. 61-66.
(151 Dragan Maksimovic, Yungtaek Jang, and Robert W. Erickson,
Nonlinear-Carrier Control for High-Power-Factor Boost Recti-
fiers, IEEE Transactions on Power Electronics, Vol. 11, no. 4,
July, pp. 578-584, 1996.
(16) Jay Rajagopalan, Red C. Lee, and Pa010 Nora, A General
Techniquefor Derivation of Average Current Mode Control Laws
for Single-phase POWer-FaCtoT-CoWeCtaOn Circuits Without In-
put Voltage Sensing, IEEE llansactions on Power Electronics,
Vol. 14, No. 4, July 1999, pp. 663-672.
[17] M. C. Ghanem, K. Al-Haddad and G . Roy, A new single phase
buck-boost converter with unity power factor, IEEE IAS 93, Part
2, pp. 785-792, 1993.

356