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Abstract
We investigate the application of Semidenite Programming (SDP) techniques to the VLSI macrocell
oorplanning problem. We propose a new mixedinteger SDP formulation of the problem which leads
to new SDP relaxations. This approach has been implemented and we report global lower bounds for some
MCNC benchmark macrocell problems.
Introduction
A. Vannelli
Department of Electrical and Computer
Engineering, University of Waterloo
Waterloo, Ontario, N2L 3G1, Canada
vannelli@cheetah.vlsi.uwaterloo.ca
Semidenite Relaxations
Proceedings of the 9th International Database Engineering & Application Symposium (IDEAS05)
1098-8068/05 $20.00 2005 IEEE
C, X
C Sn (linear objective),
Ai , X = bi , i = 1, . . . , m; Ai Sn , bi R
X0
(1)
3.1
Area constraints
=0
This obviously
implies wi hi = ai .
Requiring i ai = aF is not restrictive, because most
benchmark problem satisfy it. Moreover, this requirement is directly in the spirit of xed-outline oorplanning where, in addition to minimizing the connectivity
costs, one also wants to minimize dead-space in the
layout.
3.2
Fit-in-the-chip constraints
hi ) yi
1
2 (hF
hi ).
(4)
(5)
Proceedings of the 9th International Database Engineering & Application Symposium (IDEAS05)
1098-8068/05 $20.00 2005 IEEE
x2i
2 (wF
wi )
xi
1
2 (wF
2
wi ) ,
xi
wi )
1
2 (wF
(6)
0.
(7)
1
2 (hF
hi )
yi
yi
1
(h
F hi )
2
0.
(8)
3.3
3.4
i
wi
wi
ai
0,
i
hi
hi
ai
0.
(9)
ij =
+1
1
(10)
Once this direction is selected, we determine the relative position of modules i and j in that direction using
a second binary variable:
+1
1
(12)
= xj xi
x
0 Sij
x
2Sij
(13)
(14)
x
(1 ij ) + 12 (1 + ij )(1 ij ) Uij
(15)
x
+ (xj xi )
(16)
0 Sij
x
1
1
x
.
Sij + (xj xi ) 2 (1 ij ) + 2 (1 + ij )(1 + ij ) Uij(17)
x
Sij
1
2
|yi yj |
It is important to notice that only one of the two inequalities has to be satised for each pair of modules.
These constraints are commonly modeled using binary
variables [12] or complementary constraints [3]. We derive here a new formulation which, like in [5], uses only
two binary variables per pair of modules. The rst
variable ij is used to decide the direction in which the
non-overlap is enforced:
dxij
x
= (xj xi ), dxij =
or ij = 1 (xj xi ), and Sij
x
xi xj 0; 0 xi xj Uij .
Non-overlap constraints
|xi xj |
y
Sij
1
2
(1
y
Sij
+ (yj yi )
(18)
y
1
1
(19)
2 (hi + hj ) 2 (1 + ij )Qij .
y
y
dij 2Sij = yj yi
(20)
y
0 Sij
(21)
y
1
+ ij ) + 2 (1 ij )(1 ij ) Uij
(22)
y
0 Sij + (yj yi )
(23)
y
1
1
(24)
.
2 (1 + ij ) + 2 (1 ij )(1 + ij ) Uij
Proof: From the paragraph preceding the theorem, if ij = 1, the equations (12), (15), (17) ensure
non-overlap between modules i and j in the x direction
and compute exactly dxij . At the same time, (19) is
equivalent to dyij 0 12 (hi + hj ) Qyij which is obviy
y
, 0 Sij
+ yj yi and then
ous. By (22),(24): 0 Sij
y
using (20), we obtain: dij yi yj , dyij yj yi , which
is the linear relaxation of dyij = |yj yi |. This proves
that when ij = 1, the constraints (12)-(24) enforce
separation in the x direction and compute exactly the
distance dxij while performing a linear relaxation of dyij .
The case ij = 1 is proved similarly.
Note that (15),(17),(22),(24) can be expanded as:
x
Sij
x
Sij
+ (xj
y
Sij
y
+ (yj
Sij
Proceedings of the 9th International Database Engineering & Application Symposium (IDEAS05)
1098-8068/05 $20.00 2005 IEEE
1
4
x
(3 ij ij ij ij ) Uij
,
(25)
x
xi ) (3 ij + ij + ij ij ) Uij
,(26)
y
1
(27)
4 (3 + ij ij + ij ij ) Uij ,
y
1
yi ) 4 (3 + ij + ij ij ij ) Uij .(28)
1
4
4.1
3.5
Complete formulation
dy
ip
(31)
Area: (3)
Aspect: (9)
Fit-in-the-chip: (7), (8)
We rst ensure that our formulation satises the following transitivity property between the modules:
suppose that three modules i, j, k are separated in the
same direction, then in that direction, if i precedes j
and j precedes k, then i precedes k. Such transitivity
constraints were used in [2] for the single row placement
problem. Note that:
The modules i, j, k are separated in the same direction if and only if ij = jk = ik .
The transitivity property in the selected direction
is then : ij = jk ij = ik .
Therefore, our transitivity property is stated as:
ij = jk = ik
ij = ik .
and
(33)
ij = jk
Proposition 4.1 A sucient condition to have (33)
is : i, j, k such that i < j < k,
(ij + jk )(ij + ik )(ij + jk )(ij ik ) = 0. (34)
Note the restriction i < j < k introduced.
Proof: For any i, j, k, one of the following cases
holds: (i) i < j < k, (ii) k < i < j, (iii) j < k <
i, (iv) i < k < j, (v) j < i < k, (vi) k < j <
i. From the denition of ij and ij , we have also:
i < j. Case (i) is
ij = ji and ij = ji ,
straightforward. For case (ii), we have:
(34)
(1 + ki kj + ki ij + kj ij )
(1 ki kj + ki ij kj ij ) = 0,
(1 + ik jk + ik ij + jk ij )
(1 ik jk ik ij + jk ij ) = 0,
(1 + ij ik + ij jk + ik jk )
(1 ij ik + ij jk ik jk ) = 0,
(33).
y
x
dxij , dyij , dxip , dyip , Sij
, Sij
R, i < j,
wi , hi , xi , yi R, i < j.
Often when deriving LP relaxations for integer problems, valid equalities or inequalities are added to the
ij ik ij jk + ik jk
ij ik ij jk ik jk
+ij ik ij ik ij ik ij jk + ij ik ik jk
+ij jk ij ik ij jk ij jk + ij jk ik jk
+ik jk ij ik ik jk ij jk + ik jk ik jk .
(35)
Proceedings of the 9th International Database Engineering & Application Symposium (IDEAS05)
1098-8068/05 $20.00 2005 IEEE
4.2
Circuit
apte
hp
N
tn
where tn =
, ttn =
. This vector con2
2
tains all our binary variables and their required products. Then, the classical rank-one SDP formulation
matrix is:
4.3
(36)
1
2
(3 + ij + ij ij ij ) hF .
Computational results
Bounds
CPU
(sec.)
2
3
5
8
10
2
3
5
8
10
2
3
5
8
10
3135.9
3021.6
2918.5
2848.8
2434.0
2434.0
2051.0
1539.8
1217.1
1153.1
976.98
893.25
822.11
783.80
773.23
891
789
848
815
793
1665
2290
2930
2835
2721
8156
8230
8294
7840
7855
bin binT 0.
Ratio
5.1
Circuit
Bounds
apte
xerox
hp
2847.7
1153.1
773.23
Anjos-Vannelli
Solution
Gap
(%)
5205.4
6538
2101.2
45.3
82.4
63.2
Kuh-Murata
Solution
Gap
(%)
4353.5
4976.5
1779.8
34.6
76.8
56.6
Proceedings of the 9th International Database Engineering & Application Symposium (IDEAS05)
1098-8068/05 $20.00 2005 IEEE
Bounds
apte
xerox
hp
3119.1
1153.1
781.38
5
4
3
Anjos-Vannelli
Solution
Gap
(%)
5205.4
6538
2101.2
40.1
82.3
62.8
Kuh-Murata
Solution
Gap
(%)
4353.5
4976.5
1779.8
28.3
76.8
56.1
Acknowledgment
The authors thank C. Luo for providing the layouts
obtained using the Anjos-Vannelli approach.
References
5.2
Conclusion
We have presented a new mixed-integer and semidenite programming formulation for the VLSI macrocell oorplanning problem. The formulation models exactly the dierent constraints of the problem. The SDP
relaxation of this formulation gives the rst non-trivial
lower bounds on the optimal value for the small MCNC
benchmark problems. However, the computation time
of these relaxations is very large. We are working on
several extensions of this work: solving larger MCNC
benchmark problems, improving the bounds and SDP
solvers, deriving rounding schemes.
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Proceedings of the 9th International Database Engineering & Application Symposium (IDEAS05)
1098-8068/05 $20.00 2005 IEEE