Active-HDL Help

Copyright Aldec, Inc.

HDL Entry and Simulation Tutorial

Table Of Contents
Introduction ...................................................................................................................................... 1
HDL Entry and Simulation Tutorial............................................................................................... 1
Introduction............................................................................................................................... 1
Starting Active-HDL.................................................................................................................. 1
Creating a New Workspace...................................................................................................... 2
Creating a New Design ............................................................................................................ 2
Code Editing ............................................................................................................................. 6
Simulation............................................................................................................................... 14

Introduction
HDL Entry and Simulation Tutorial

Introduction
This tutorial will guide you through the advanced Active-HDL design tool. This tutorial requires
basic knowledge of VHDL. If you have none, ALDEC EVITA Interactive Active-HDL Tutorial will
be a good starting point.
The Framework
The Active-HDL framework is based on a standard (Microsoft Foundation Class)-like GUI
interface. Each window can be docked, overlapped, or application-like. The main parts of ActiveHDL are:

Design Browser
Workspace/Design Explorer
HDL Editor
Block Diagram Editor
State Machine Editor
Standard Waveform Viewer/Editor
Accelerated Waveform Viewer
Console
Library Manager
Dataflow
Advanced Dataflow
List
Call Stack
Processes
Watch
Memory Viewer
Design Profiler
Code Coverage
Toggle Coverage
Code and Toggle Coverage Viewer

Starting Active-HDL
To start the program, go to the Start/Programs group and click the Active-HDL icon. The
Active-HDL should start loading, which is indicated by the The Active-HDL Welcome screen.
When the loading process finishes, the following dialog appears:

HDL Entry and Simulation Tutorial

The Getting Started Window.

Select the Create new workspace option and click the OK button.

Creating a New Workspace

The New Workspace wizard has only one step. In this step you need to provide the name and
location of the workspace.
Make sure that the Add New Design to Workspace checkbox is selected.

When the New Workspace wizard finishes its job, the New Design Wizard will be invoked.

Creating a New Design

Specifying the Design Contents
In the first step of the New Design Wizard dialog, you should specify the contents of the design
you are creating. Select the Create an empty design option, and then click Next.
Setting Synthesis and Implementation Tools
Specify the desired synthesis and implementation tools for the current design. Choose the default
family, block diagram configuration and default HDL language. Click Next.

Introduction
Entering the Design Name
In the next wizard dialog you will specify the design name, design folder, design type and working
library name.

The New Design Wizard Window.

In the Type design name, type Tutorial. In the Select the location of the design folder field,
type or select the desired folder, and then click Next.
Accepting Design Properties
The last dialog is a confirmation dialog. Your design properties are displayed in the dialog. If they
are correct, click the Finish button.

Use the Back button if the settings are incorrect.

Use the Cancel button if you do not want to create the new design.
Click the Finish button to complete the design specification.

Creating the Skeletal Source File

Choose the New/VHDL Source option from the File menu. New Source File Wizard allows you
to create components and add them to your design. Click Next when the following dialog
appears.

HDL Entry and Simulation Tutorial

Now, specify the name of the component, plus the name of its entity as shown on the picture
below.

Click Next to enter port descriptions.

Ports Wizard
To enter a port, click the New button and type the port name in the Name box. You can specify
the port direction using the Port Direction options. If you want to enter a bus, you can set its
range in the Array Indexes box.
Add the following ports:

CLK - in port
RESET - in port
Q[3:0] - out bus port , range [3:0]

After you have added a port, click the Type button. This will bring up a dialog that allows you to
choose the type of the port.

Introduction

The Design Wizard Window - Ports.

Choose the STD_LOGIC option for single ports and STD_LOGIC_VECTOR for the bus. This will
attach the IEEE library and packages declarations to the generated code. Click the OK button to
go back to the New Design Wizard dialog and click Finish to close the wizard.
Design Browser
The Design Browser is a window showing the design contents. As a result of previous
operations it will display the following contents:

The Design Browser Window.

As you can see in the figure above, the design name is Tutorial. At this point, the design contains
only the Counter.vhd file and working library identical with the design name.
Compile the source file by choosing the Compile option from the shortcut menu. To invoke the
menu, click with the right mouse button over the file name.

HDL Entry and Simulation Tutorial

Compiling the source file

After successful compilation the icon will appear close to the file name along with the
allowing the expansion of the design structure.

.
The Design Browser Window After Compile Command.
Click the

icon to expand the view.

The Design Browser Window With Expanded Structure.

The window shows an entity-architecture pair.

Code Editing

sign

Introduction
HDL Editor
The HDL Editor is a text editor with HDL keywords coloring and standard editing features. ActiveHDL offers another useful feature that allows grouping, collapsing and expanding particular VHDL
constructs to improve readability of the code.

The HDL Editor Window.

Language Assistant
Let us now define the structure of the Counter component.
Select the Language Assistant option in the Tools menu, or click the
The following window will appear:

icon on the toolbar.

The Language Assistant Window.

Expand the Tutorial label. The following items will appear:

The Language Assistant Window.

HDL Entry and Simulation Tutorial

Click the Counter label.

The Language Assistant Window.

In the right panel of the window, there is a VHDL process describing a BCD counter. Lets paste
this template into the counter design by performing the following steps.
1. Minimize the Language Assistant window and in the HDL Editor find the following line:
-- enter your statements here -2. Place the cursor in the next line.
3. Select the Counter label in the Language Assistant tree.
4. Select Use from the shortcut menu.
5. The template is placed at the cursor location.
Adding Libraries
The edited code requires some additional packages to be included. To do so, add after the use
IEEE.std_logic_1164.all statement :
use IEEE.std_logic_unsigned.all;
To auto-format the VHDL code click the
button.

icon, and to generate the structure use the

The result is:

The HDL Editor Window With Counter Code.

Introduction
Compiling Sources
Go to the Design Browser window, select the counter.vhd file and click the right mouse button.
Choose the Compile option from the shortcut menu.

The Shortcut Menu.

If the source file contains an error, the sign appears at the file name. Erroneous line is
underlined and the VHDL console window displays the error description. To see the exemplary
error message, change e.g. the library name in the use clause from std to srd, and try to compile
the file.

The HDL Editor Document with Indicated Errors.

You need to correct the package name, and recompile the source file. This time there should be
no errors, and the icon should appear close to the file name.
Creating New Component - Decoder
Using the same procedure as described in the Creating the Skeletal Source File section of this
tutorial, create a new component.
Type Decoder as the name of the file.

HDL Entry and Simulation Tutorial

The New Source Wizard Window -Name.

Enter ports as shown in the following window. Select the STD_LOGIC_VECTOR type for each
port. Click on the Finish button to create the skeleton file.

The New Source Wizard Window - Ports.

The Design Browser shows:

The Design Browser Window.

We will now fill in the architecture template of the Decoder file using the Language Assistant.

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Introduction

The Decoder VHDL Source.

Switch to the HDL Editor and place the cursor in the architecture block, right after the -enter your statements here -- line.
Select the Decoder name in the left panel of the Language Assistant window, and choose the
Use option from the shortcut menu.

The Decoder.vhd file Contents.

The template (code) will be pasted to the decoder.vhd file. Save the file.
Creating a Top Level File
To create a new blank VHDL file, double-click the Add New File icon from the Design Browser
and select the VHDL Source Code icon as it is shown in the picture below.

The Add New File Window.

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HDL Entry and Simulation Tutorial

Type top in the Name edit box and press OK.
1. Go to the Language Assistant and find Top in the Tutorial folder.
2. Select Use from the shortcut menu to paste the template into the Top.vhd file.
3. Go to the File menu and choose the Save option.

The Top Level architecture.

The Design Browser contents after the above operations is shown below:

The Design Browser Contents.

The HDL Editor contents, after structure generation and auto-formatting.

The HDL Editor Window with Contents.

Let us now recompile the entire design. Use the Compile All option available from the rightbutton pop-up menu.

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Introduction

Compiling all design files

Viewing the Design Structure
To specify the top-level entity of the design, invoke the list to see available entity-architecture
pairs. Select the top unit.

Selecting the top-level unit.

You can do the same operation by selecting the top-level unit in the tree and choosing the Set as
Top-Level option available from the right-button pop-up menu. You can also use the Settings
command available under the Design menu. This will display the Design Settings dialog in
which you can select the top-level entity on the Top-level Selection tab. Go to the Design
Browser and select the Structure tab:

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HDL Entry and Simulation Tutorial

The Contents Of Structure Tab.

The Structure tab shows the structure of a design. In the Top design, which has the Root
attribute, there are two instantiated components: Counter and Decoder. Each of these
components has one process, which is shown in the tree.
Viewing Local Data
Each design unit can contain ports, signals and variables. Active-HDL allows easy browsing
through the unit data. If you click a component label on the Structure tab of the Design
Browser, its local data will be displayed in the lower part of the window.

Selected Model Ports.

Let us verify the design and simulate it.

Simulation
Starting Simulation

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Introduction
To begin a simulation, you have to initialize the simulator first, using the Initialize Simulation
option from the Simulation menu. After the simulator has been initialized, you have to open a
new Waveform window. Click the New Waveform toolbar button . The new Waveform
window appears.

The Waveform Viewer Window.

To add signals to the simulator, use the drag-and-drop method. Open the Structure tab of the
Design Browser window, select the the Top design with Root attribute and while holding down
the left button, drag it to the right-section of the waveform window and then release the mouse
button. This is a standard drag-and-drop operation.

Adding Signals From Design Browser Window.

If you want to delete a signal, select it and press Delete.
Active-HDL allows inspection of simulation results in the tabled format with delta time precision.
The List Viewer window enables signal values monitoring without the ability to force signals with
the desired values. To open the Viewer window click the New List toolbar button . The window
below will appear as a result.

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HDL Entry and Simulation Tutorial

The List Viewer Window.

Adding the signals to the List Viewer window is similar to the Waveform Viewer behavior. Drag
the required signals from the Structure tab of the Design Browser window. The List Viewer
window with signals added should look as follows.

List Viewer window with added signals

The List Viewer window is an interactive display which mirrors all simulation actions and results.
Assigning Stimulators
Go to the left panel of the Waveform Viewer window and select the CLK signal. Press the right
button to invoke a context menu.

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Introduction
Assigning Stimulators to Signals.
Choose the Stimulators option. The following window appears:

The Stimulators Window.

Choose Clock from the Type list:

Applying Clock Stimulator To Signal.

Place the mouse pointer in the Frequency box and set the value of 10 MHz. Click the Apply
button to assign the stimulator. Next, select the RESET signal in the Waveform Viewer window,
and then select the Formula item from the Stimulators dialog.
When the dialog appears, type the formula expression as follows:
1 0, 0 10000

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HDL Entry and Simulation Tutorial

Applying Formula Stimulator To Signal.

Click Apply, and then Close.
Lets simulate!
Perform several simulation steps by clicking the Run For button. You will receive the following
results on the Waveform tab.

The Simulation Results

The Internal bus has been expanded in the picture below by clicking the + sign next to the label.

The Simulation Results.

Choose End Simulation from the Simulation menu. Save the waveform under the file name:
Waveform Editor 1.awf.
To display the results in the tabled format and monitor delta time changes switch to the opened
List Viewer window. The results should be displayed in the similar manner.

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Introduction

Simulation results in the List Viewer

To display results with delta precision click the

icon on the toolbar.

Using Simple Test Bench

Active-HDL allows you to perform the simulation in yet another way by using the automatically
generated test benches.
Switch to the Design Browser and Files tab. Choose Generate Test Bench from the shortcut
menu as shown below:

Test Bench Generation

As a result the Test Bench Generator Wizard will appear. In the first window select the Entity
and Architecture for which the test bench will be generated. Accept the names proposed by the
Wizard and click Next.

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HDL Entry and Simulation Tutorial

Test Bench Generator Wizard

The next step is based on the previously saved waveform. Check the Test vectors from file
check box. In the Select a waveform file field, browse for the Waveform Editor 1.awf file and
click Next.

Importing test vectors from file.

In the next stage enter the entity name, the name of the Test Bench file and the destination
folder. Accept the default settings and click the Next button.

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Introduction

Test Bench settings

In the last step you can enable the configuration generation for timing simulation. By default this
option is turned off. Finish the test bench generation by clicking the Finish button.
Finishing Test Bench Generation.
A new folder was created in the Design Browser window in which the test bench file was stored
with the Top_TB_runtest.do macro command file for automatic compilation and simulation.

New Test Bench folder

To start simulation using the generated Test Bench right click the Top_TB_runtest.do macro
command file and select the Execute command.

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HDL Entry and Simulation Tutorial

Executing the macro command file

The execution of the macro command file results in the automatic recompilation and simulation
which results are shown in the following figure.

Simulation results
Source Code Tracking
Active-HDL allows you to step through the code during simulation. The appropriate source code
is automatically opened while using Trace Into, Trace Over, or Trace Out buttons. The
statement which will be executed next, is shown in the HDL Editor window in yellow.
First you need to end the previous simulation run by selecting the End Simulation option from
the Simulation menu and reinitialize it by selecting Initialize option.
From the View menu choose the Watch, Processes and Call Stack options to invoke the
Watch, Processes and Call Stack windows.
The Processes window shows the status of design processes. The Watch window enables you
to examine values of signals and variables.
The Call Stack window is a debugging tool that displays a list of subprograms (procedures and
functions) being executed in the currently executed process. The term process is used here to
mean any concurrent statement modeling a sequential process in the elaborated model. Such

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Introduction
statements are process statements, concurrent signals assignment statements, concurrent
assertion statements, and concurrent procedure call statements (exactly the same as for the
Processes window). For each subprogram the window displays the following information:

Formal parameters along with their actual values.

Variables, constants, and files declared locally in subprogram bodies along with their
current values.

During the debugging process the following commands are available:

Trace into - executes a single VHDL statement. If a subprogram call is encountered, the
execution descends into the subprogram body.
Trace over - executes a single VHDL command. If a subprogram call is encountered, the
statements contained within the subprogram body are executed in a single step.
Trace out - executes as many VHDL statements as are required to complete the execution
of a subprogram. If subprograms are nested, the command completes the execution of the
innermost subprogram only.
Using these commands you can observe:

signal value changes in the Watch window,

particular processes activity in the Processes window,
variables, constants and files declared locally in subprogram bodies along with their
current values in the Call Stack window

Switch to the Structure Tab in the Design Browser window.

Select the TOP_TB entity and by using the drag-and-drop technique drag the signals contained
within the entity to the Watch window.
Right-click anywhere inside the Processes window and select the Show all option to enable
displaying active and inactive processes in the current simulation cycle.

Displaying all design processes

Using the Trace Over button observe the changes in the opened windows.
The exclamation mark in front of the signal name in the Watch window indicates the signal value
change for the current simulation cycle (CLK signal in the figure below).

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HDL Entry and Simulation Tutorial

The Watch Window
In the Processes window you can view the list of processes and their current status (ready or
wait). The ready status means that the process is currently active and is automatically moved up
to the top of the displayed list.

The Processes Window

In the Call Stack window you can observe only the values of the variable declared in the process
responsible for the counting.

The Call Stack Window

The Dataflow window is a tool providing a graphical view of signals flowing in and out of
processes during simulation. The term process is used here to mean any concurrent statement
modeling a sequential process in the elaborated model. Such statements are process statements,
concurrent signals assignment statements, concurrent assertion statements, and concurrent
procedure call statements (exactly the same as for the Processes window). The window provides
two different views:

with a process in the center of the window,

with a signal in the center of the window.

When a process is displayed in the center, it is represented as a rectangular box with input
signals on the left side and output signals on the right. Input signals are those read by the
process. Output signals are those updated by the process. When a signal is displayed in the
center, it is represented as a vertical thick line with processes connected to it on both sides.
Processes on the left side update the signal. Processes on the right side read the signal. You can
switch between these two views by clicking items in the Dataflow window.
In both views, signals are displayed with their names and processes are displayed with their
labels (either assigned explicitly by the user or generated automatically by the simulator). For
signals, the Dataflow window also displays their current values.
End the previous simulation run by selecting the End Simulation option from the Simulation
menu and reinitialize it by selecting Initialize option.
Select any signal from the Structure tab of the Design Browser window and choose the
Dataflow option from the context menu. As a result the Dataflow window shown below will be
invoked.

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Introduction

The Dataflow window

Click the RESET signal name in the Dataflow window. This will take you to the next frame shown
next.

Following the Dataflow objects

Now click the UUT/CNT/line__28 process name.

The Dataflow window

Using the F5 keyboard key or Run For toolbar button observe the value changes of the Q
counter in the Dataflow window.

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HDL Entry and Simulation Tutorial

The signal changes in the Dataflow window

Thank You for using Active-HDL!

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