STD10PQ

www.agelectronica.
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www.agelectronica.com
STD10PF06
P - CHANNEL 60V - 0.18 - 10A TO-252

STripFET POWER MOSFET
TYPE
STD10PF06
V DSS
R DS(o n)
ID
60 V
< 0.20
10 A
TYPICAL RDS(on) = 0.18

EXCEPTIONAL dv/dt CAPABILITY
100% AVALANCHE TESTED
LOW GATE CHARGE
APPLICATION ORIENTED
CHARACTERIZATION
ADD SUFFIX T4 FOR ORDERING IN TAPE
& REEL
DESCRIPTION
This Power MOSFET is the latest development of
STMicroelectronics unique Single Feature
Size strip-based process. The resulting transistor shows extremely high packing density for low
on-resistance, rugged avalanche characteristics
and less critical alignment steps therefore a remarkable manufacturing reproducibility.
3
1
DPAK
TO-252
(Suffix T4)
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
MOTOR CONTROL
DC-DC & DC-AC CONVERTERS
ABSOLUTE MAXIMUM RATINGS

Symb ol
V DS
V DGR
VGS
Parameter
Value
Unit
Drain-source Voltage (VGS = 0)
60
Drain- gate Voltage (R GS = 20 k)
60
20
Gate-source Voltage
o
ID
Drain Current (continuous) at Tc = 25 C
10
ID
Drain Current (continuous) at Tc = 100 oC
Drain Current (pulsed)
40
40
0.27
W /o C
V/ns
I DM ()
P tot
Total Dissipation at T c = 25 C
Derating F actor
dv/dt
T st g
Tj
Peak Diode Recovery voltage slope

Storage T emperature
Max. Operating Junction Temperature
-65 to 175
175
() Pulse width limited by safe operating area

( 1) ISD 10 A, di/dt 300 A/s, VDD V(BR)DSS, Tj TJMAX
Note: For the P-CHANNEL MOSFET actual polarity of voltages and current has to be reversed
April 1999
1/8
STD10PF06
THERMAL DATA
R thj -case
R thj -amb
R thc-sink
Tl
Thermal Resistance Junction-case

Thermal Resistance Junction-ambient
Thermal Resistance Case-sink
Maximum Lead Temperature F or Soldering Purpose
Max
Max
T yp
3.75
100
1.5
275
C/W
C/W
o
C/W
o
C
o
AVALANCHE CHARACTERISTICS
Symbo l
Parameter
Max Value
Unit
IAR
Avalanche Current, Repetitive or Not-Repetitive

(pulse width limited by Tj max)
10
E AS
Single Pulse Avalanche Energy

(starting Tj = 25 o C, ID = IAR , V DD = 25V)
50
mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)

OFF
Symbo l
V (BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Con ditions

I D = 250 A
V GS = 0
I DSS
V DS = Max Rating
Zero Gate Voltage
Drain Current (V GS = 0) V DS = Max Rating
IGSS
Gate-body Leakage
Current (VDS = 0)
Min.
Typ.
Max.
60
Unit
V
T c = 125 oC
V GS = 20 V
1
10
A
A
100
nA
Max.
Unit
ON ()
Symbo l
Parameter
Test Con ditions

ID = 250 A
V GS(th)
Gate Threshold Voltage V DS = V GS
R DS(on)
Static Drain-source On
Resistance
V GS = 10V
I D(o n)
On State Drain Current
V DS > ID(o n) x R DS(on )ma x

V GS = 10 V
Min.
2
ID = 5 A
Typ.
3.4
0.18
0.20
10
DYNAMIC
Symbo l
g f s ()
C iss
C os s
C rss
Parameter
Test Con ditions
Forward
Transconductance
V DS > ID(o n) x R DS(on )ma x
ID = 5 A
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V DS = 25 V
V GS = 0
f = 1 MHz
Min.
Typ.
Max.
Unit
850
230
75
pF
pF
pF
2/8
STD10PF06
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
Parameter
Test Con ditions
Min.
Typ.
Max.
Unit
t d(on)
tr
Turn-on Delay T ime

Rise Time
V DD = 30 V
ID = 6 A
R G = 4.7
V GS = 10 V
(Resistive Load, see fig. 3)
20
40
Qg
Q gs
Q gd
Total G ate Charge

Gate-Source Charge
Gate-Drain Charge
V DD = 48 V ID = 12 A V GS = 10 V
16
4
6
21
nC
nC
nC
Typ.
Max.
Unit
ns
ns
SWITCHING OFF
Symbo l
Parameter
Test Con ditions
Min.
t d(of f)
tf
Turn-off Delay T ime

Fall T ime
V DD = 30 V
ID = 6 A
V GS = 10 V
R G = 4.7
(Resistive Load, see fig. 3)
40
10
ns
ns
tr (Voff)
tf
tc
Off-voltage Rise T ime

Fall T ime
Cross-over Time
V DD = 48 V
I D = 12 A
V GS = 10 V
R G = 4.7
(Induct ive Load, see fig. 5)
10
17
30
ns
ns
ns
SOURCE DRAIN DIODE

Symbo l
Parameter
Test Con ditions
ISD
I SDM ()
Source-drain Current
Source-drain Current
(pulsed)
V SD ()
Forward On Voltage
I SD = 10 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 12 A
di/dt = 100 A/s
T j = 150 o C
V DD = 30 V
(see test circuit, fig. 5)
t rr
Q rr
I RRM
Min.
Typ.
V GS = 0
Max.
Unit
10
40
A
A
2.5
100
ns
260
5.2
() Pulsed: Pulse duration = 300 s, duty cycle 1.5 %

() Pulse width limited by safe operating area
Safe Operating Area
Thermal Impedance
3/8
STD10PF06
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STD10PF06
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/8
STD10PF06
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For

Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching

And Diode Recovery Times
6/8
STD10PF06
TO-252 (DPAK) MECHANICAL DATA

mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
0.64
0.9
0.025
0.035
B2
5.2
5.4
0.204
0.212
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
6.2
0.236
0.244
6.4
6.6
0.252
0.260
4.4
4.6
0.173
0.181
9.35
10.1
0.368
0.397
L2
0.8
L4
0.031
0.6
0.023
0.039
A1
C2
A2
DETAIL A
L2
=
=
E
=
B2
DETAIL A
L4
0068772-B
7/8
STD10PF06
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are
subjec t to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a trademark of STMicroelectronics
1999 STMicroelectronics Printed in Italy All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
8/8
http://www.st.com
.

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P - CHANNEL 60V - 0.18 - 10A TO-252

TYPICAL RDS(on) = 0.18

INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Drain-source Voltage (VGS = 0)

Drain- gate Voltage (R GS = 20 k)

Drain Current (continuous) at Tc = 25 C

Drain Current (continuous) at Tc = 100 oC

Drain Current (pulsed)

Peak Diode Recovery voltage slope

() Pulse width limited by safe operating area

Thermal Resistance Junction-case

Avalanche Current, Repetitive or Not-Repetitive

Single Pulse Avalanche Energy

ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)

Test Con ditions

Test Con ditions

Gate Threshold Voltage V DS = V GS

On State Drain Current

V DS > ID(o n) x R DS(on )ma x

Test Con ditions

V DS > ID(o n) x R DS(on )ma x

Test Con ditions

Turn-on Delay T ime

Total G ate Charge

Test Con ditions

Turn-off Delay T ime

Off-voltage Rise T ime

SOURCE DRAIN DIODE

Test Con ditions

() Pulsed: Pulse duration = 300 s, duty cycle 1.5 %

Safe Operating Area

Static Drain-source On Resistance

Gate Charge vs Gate-source Voltage

Normalized On Resistance vs Temperature

Source-drain Diode Forward Characteristics

Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuits For

Fig. 4: Gate Charge test Circuit

Fig. 5: Test Circuit For Inductive Load Switching

TO-252 (DPAK) MECHANICAL DATA

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