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Proceedings of the Third International Conference on Digital Information Processing, E-Business and Cloud Computing, Reduit, Mauritius 2015

Design and Evaluation of Pulse Triggered Flip-Flop Based on Split Output TSPC Latch for Low Power High Performance Digital Circuit

Sandeep Singh Gill 1 and Gurinderjit Kaur 2 1, 2 Guru Nanak Dev Engineering College, Ludhiana, India

1 ssg@gndec.ac.in

ABSTRACT

In this paper a Pulse Triggered Flip-Flop based on Split Output TSPC Latch suitable for low power high performance application is proposed. The Pulse Triggered Flip-Flop is constructed using a split output TSPC latch with embedded logic. Proposed flip-flop has the advantages of simple structure, less number of transistors, low dissipation power and lower transistor area. Proposed circuit is simulated in cadence analog design environment with 0.25µm CMOS technology. Simulation results show that by using the proposed circuit, dissipation power can be reduced by 40%, number of transistors by 40%, current drawn by 48% and transistor area can be reduced by 68%.

KEYWORDS: Pulse triggered flip-flops (PTFF), Split Output TSPC latch, Semi dynamic flip-flop (SDFF), Hybrid latch flip-flop (HLFF), Embedding logic, Low power.

1. INTRODUCTION

Most digital circuits today are constructed using static CMOS logic and edge- triggered flip-flops. Although such techniques have been adequate in the past and will remain adequate in the future for low performance design, they will become inefficient for high- performance components as the number of transistors are increasing resulting in increase of area. Some conventional high performance flip-flops like Hybrid Latch Flip-Flop (HDFF) and Semi Dynamic Flip-Flop (SDFF) have the disadvantage that they have large amount of power dissipation due to redundant

ISBN: 978-1-941968-14-7 ©2015 SDIWC

transistors at internal nodes, including the issue of increase in the number of transistors. Designers will therefore need to adopt new techniques and circuits that can improve the performance by lowering power dissipation and area of the design for low power digital circuits with less number of transistors.

2. REVIEW OF EXISTING FLIP-FLOPS

A design was developed by Sun

Microsystems Inc. used in UltraSPARC-III micro-processors using a Semi Dynamic Flip- Flop, proposed by Fabian Klass with 0.25 µm CMOS technology. This design had short

latency, Small clock load with low power consumption. This design was bulky having large number of transistors and required larger area on die. This design was improved by Arnab Ghosh from university of Idaho

with same Semi Dynamic Flip-Flop (SDFF)

by scaling and embedded logic [1], [2]. The

flip-flop on a 1 bit adder consisting carry and

sum functions was implemented and by the

use of scaling and embedded logic timing parameters and area were improved. These improvements were achieved with the penalty of bulk in circuit, large delay, large setup and hold time. This design is considered as a benchmark for this paper [1]. This section will discuss the used structure of Flip-flop i.e. Semi-Dynamic Flip-Flop (SDFF) and the

conventional high speed Flip-Flop i.e. Hybrid-Latch Flip-Flop (HLFF). The circuit diagram of a Semi-Dynamic Flip-Flop (SDFF) is shown in Fig. 1. The circuit is

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Proceedings of the Third International Conference on Digital Information Processing, E-Business and Cloud Computing, Reduit, Mauritius 2015

faster than TSPC but still has some shortcomings. First, internal node X is truly dynamic, i.e. it is not actively driven by any device during most of the evaluation phase. Second, output Q is high impedance when the clock signal is low. The circuit is composed

of a dynamic front-end and a static back-end.

The flop samples input D and produces output QB, which is the logic complement of D. The circuit operates as follows. On the falling edge of clock CLK, the flop enters the precharge phase.

edge of clock CLK, the flop enters the precharge phase. Fig.1. Semi Dynamic Flip-Flop (SDFF) Node

Fig.1. Semi Dynamic Flip-Flop (SDFF)

Node X is precharged high, cutting off node

Q from the input stage. The evaluation phase

begins with the rising edge of clock CLK. If input D is low, node X would remain high.

Node Q would either remain low or will be

discharged through transistors. The circuit diagram of Hybrid Latch Flip-Flop is shown

in Fig.2.

circuit diagram of Hybrid Latch Flip-Flop is shown in Fig.2. Fig.2. Hybrid Latch Flip-Flop (HLFF) The

Fig.2. Hybrid Latch Flip-Flop (HLFF)

The circuit of Hybrid Latch Flip-Flop consists

of two stages: the front end function as pulse

generator and the back end is to capture the pulse as a latch. It has the advantage of

ISBN: 978-1-941968-14-7 ©2015 SDIWC

having negative setup time in generating pulse which gives small D-Q delay. It also has small logic-embedding with small penalty. As mentioned earlier this Flip-flop has the disadvantage of large amount of power dissipation [3-13].

3. PROPOSED FLIP-FLOP

To overcome the disadvantages of Design using Semi Dynamic Flip-Flop and Conventional high speed flip flops we proposed a Pulse Triggered Flip- Flop based on split output TSPC latch. It has a simpler structure composed of five transistors and back to back inverters. It is a positive latch if it is triggered by the rising edge of the clock. Back to back inverters enhance the robustness of its output operation. Proposed flip-flop can reduce the power dissipation, current drawn, transistor count, total transistor width and estimated transistor area. Fig.3 Shows the Circuit diagram of Pulse Triggered Flip-Flop based on split output TSPC latch. In proposed circuit clock is applied to pull up circuit to fulfill the need to have a mirror circuit of pull down to implement the embedded logic. Clock is also applied to NMOS at the middle to trigger the circuit, data is applied to pull down circuit.

trigger the circuit, data is applied to pull down circuit. Fig.3. PTFF based on Split output

Fig.3. PTFF based on Split output TSPC latch

This circuit will also avoid bulk in the design as compared to Semi Dynamic Flip-Flops (SDFF) as it do not consists of any redundant

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Proceedings of the Third International Conference on Digital Information Processing, E-Business and Cloud Computing, Reduit, Mauritius 2015

transistors at internal node. An inverted clock is applied to PMOS connected at X and Y node to remove the potential difference between both the nodes. This gate here behaves like a pass gate. At the back end we have cross coupled inverters which is a basic storing element also, it increases the robustness of the circuit. In this cross coupled inverters, width of feedback inverter should be greater than the width of feed through inverter.

4. EMBEDDING LOGIC FUNCTION

width of feed through inverter. 4. EMBEDDING LOGIC FUNCTION Fig.4. PTFF based on split output TSPC

Fig.4. PTFF based on split output TSPC latch with embedded logic

Embedding logic function is an important technique using which we can easily incorporate most logic functions into flop, such as wide OR functions, multiplexers and complex gates. Fig.4. shows the Pulse Triggered Flip-Flop based on split output TSPC latch with embedded Sum and Carry functions. It will reduce the number of combinational stages and clock cycles, which will provide high throughput of the design.

5. SIMULATION RESULTS

In this experiment we implemented the design of 1-bit registered adder having sum and carry function using Semi Dynamic Flip-flop [1] discussed in this paper and the proposed Pulse Triggered Flip-flop based on split output TSPC latch. We also simulated and analyzed

ISBN: 978-1-941968-14-7 ©2015 SDIWC

both the designs using Cadence analog design environment. We compare the transistor count, total transistor width, estimated transistor area, current drawn, power dissipation, C-Q, C-Q̅̅̅̅ , D-Q. D-Q̅̅, Set up and hold times and transparency pulse width of circuit. The experiment conditions are shown in Table.1. Simulation results are shown in Table.2 to Table.10. In this experiment all the flip-flops have the same data rate and all transistor sizes are optimized to achieve the desired results. The rise time and fall time of the input signal are 100ps. We can see that Transistor count of the proposed flip-flop is 15, with embedded logic it consists of 19 transistors and for 1 bit registered full adder transistor count is 90 in Table.2. In Table.3, we compare the Total Transistor Width which is 116.04µm for 1-bit registered full adder. We also compare Estimated Transistor Area which is 172.203µm 2 for proposed circuit and 250.901µm 2 for benchmark [1] in Table.4. In Table.5 transparency pulse width is given, which is 205ps and 180ps for Semi Dynamic Flip-Flip (SDFF) and Pulse Triggered Flip- Flop Based on split output TSPC latch respectively. In Table.6 we compare the Set up and Hold time of the proposed and benchmark [1]. We can see at the fall edge the C-Q for benchmark circuit is 120.3ps and for the proposed circuit it is 189.3ps, at the rise edge the C-Q for benchmark circuit is 276.5ps and for the proposed circuit it is 215ps given in Table.7. In Table.8 we can see at fall edge the D-Q for benchmark circuit is146ps and for the proposed circuit it is 207.9ps, at the rise edge the D-Q for benchmark circuit is 293.1ps and for the proposed circuit it is 228.3ps. Table.9 shows the comparison between Current drawn of both the designs which is 0.7nA and 0.23nA for benchmark and the proposed circuit respectively. Power dissipation is also compared in Table.10

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Proceedings of the Third International Conference on Digital Information Processing, E-Business and Cloud Computing, Reduit, Mauritius 2015

which is 1.4nW for benchmark circuit and 0.445nW for the proposed circuit.

Table 1. Experiment Conditions

Design

Benchmark

Proposed Work

Specification

Technology

0.25um

0.25um

 

TSMC deep

TSMC deep

MOSFET

Model

submicron

0.25um

submicron

0.25um

Conditions

Nominal

Nominal

Supply Voltage

2V

2V

Temperature

25 degree C

25 degree C

Rise time of input signal

100ps

100ps

Fall time of input signal

100ps

100ps

Clock frequency

100 MHz

100 MHz

Clock duty

50%

50%

cycle

Delay

Between 50%

Between 50%

calculations

points

points

Table 2. Transistor Count

Circuit

Transistor count

Benchmark

Proposed

Flip-Flop

23

15

Flip-Flop

   

with

embedded

27

19

logic

1-bit

   

registered

227

90

full adder

Table 3. Total Transistor Width

   

Proposed

Circuit

Benchmark

design (µm)

design

(µm)

Flip-Flop

25.695

15.9

Flip-Flop

   

with

embedded

35.995

23.82

logic

1-bit

   

registered full

168.39

116.04

adder

ISBN: 978-1-941968-14-7 ©2015 SDIWC

Table 4. Estimated Transistor Area

Circuit

Benchmark design (µm 2 )

Proposed design (µm 2 )

Flip-Flop

38.115

23.607

Flip-Flop

   

with

embedded

53.615

35.480

logic

1-bit

   

registered

250.901

172.203

full adder

Table 5. Transparency Pulse Width of the Circuit

Circuit

Benchmark

Proposed

design (ps)

design (ps)

Flip-Flop

193

180

Flip-Flop

   

with

embedded

205

180

logic

Table 6. Set up and Hold times

Circuit

Benchmark

Proposed

design

design

 

Virtual

Real

Virtual

Real

(ps)

(ps)

(ps)

(ps)

Setup time

Flip-Flop

-55

237

-58.82

210.3

Flip-Flop

       

with

embedded

-30

263

-55.05

223.8

logic

Hold time

Flip-Flop

160.3

-133

179

-90

Flip-Flop

       

with

embedded

160

-133

126

-154

logic

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Proceedings of the Third International Conference on Digital Information Processing, E-Business and Cloud Computing, Reduit, Mauritius 2015

Table 7. Comparison of C-Q

Circuit

Clk Q (ps)

 

Clk

(ps)

 

(LH)

(HL)

 

(LH)

 

(HL)

Benchmark design

 

Flip-Flop

253.5

118

 

190.2

 

305.1

Flip-Flop

       

with

embedded

276.5

120.3

 

190.1

 

330

logic

   

Proposed design

 

Flip-Flop

226.6

147

 

231.5

 

283.1

Flip-Flop

       

with

embedded

215

189.3

 

280

 

272.7

logic

   

Table 8. Comparison of D-Q

 

Circuit

 

D Q (ps)

 

(ps)

 

(LH)

(HL)

(LH)

(HL)

Benchmark design

 

Flip-Flop

250.5

220.9

291.4

299.8

Flip-Flop

       

with

embedded

293.1

146

231.7

344.7

logic

Proposed design

 

Flip-Flop

210.8

207.2

301.6

266.1

Flip-Flop

       

with

embedded

228.5

207.9

299.9

283.6

logic

 

Table 9. Current Drawn

 

Circuit

Benchmark

Proposed

design (nA)

design (nA)

Flip-Flop

 

0.7

0.23

Flip-Flop with

   

embedded

 

0.7

0.23

logic

 

1-bit registered

   

full adder

 

6.1

 

2.1

ISBN: 978-1-941968-14-7 ©2015 SDIWC

Table 10. Power Dissipation

Benchmark

design (nW)

Proposed

design (nW)

Circuit

Flip-Flop

1.4

0.445

Flip-Flop with

embedded

logic

1.4

0.456

1-bit registered

full adder

11.7

4.63

CONCLUSION

A Design using Pulse triggered Flip-Flop based on split output TSPC latch is proposed and simulated in a 0.25µm process. Our simulation results justify our analysis that we reduced power dissipation by 40%, transistor area by 68%, transistor count by 40% and current drawn by 48% without affecting the high performance of the circuit.

ACKNOWLEDGEMENT

The authors thank Guru Nanak Dev Engineering College, Gill Road, Ludhiana, for technical support for implementation and simulation.

REFERENCES

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Proceedings of the Third International Conference on Digital Information Processing, E-Business and Cloud Computing, Reduit, Mauritius 2015

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