Block Diagram

Bridging ARM7 and Cortex-M3

Series Overview

Introduction

LPC1700 Series

MPU
NVIC
WIC
Flash Accelerator
DMA

Industrys FIRST Cortex-M3 implementation running at 100MHz

Low power operation

Tailored for communication with 15 serial interfaces

Unique Implementations:

Smooth migration from ARM7

LPC1700 Series

Tools & ecosystem

Peripheral support

Power management

Key system blocks

Memory support

Benchmarks

Introduction

Contents

LPC2300
Block
Diagram

Series Overview

LPC1700 Block Diagram (Part 1)

Bridging Two GREAT Families- ARM7 &

Cortex-M3

Bit-Band Regions

http://www.arm.com/pdfs/IntroToCortex-M3.pdf

Multilayer AHB Bus Matrix

11

LPC1700 Bit
Band Regions

Block
Diagram
(Part 2)

12

10

Automotive/industrial benchmarks used by NXP for LPC1700

Communications
Networking
Consumer
Office automation
Embedded Java
Network storage-related applications

www.eembc.org

Members including leading semiconductor, intellectual property, and

compiler companies

EEMBC benchmarking represents different workloads/capabilities in:

Designed to help designers select the right processor for their system

Develops and certifies real-world benchmarks and benchmark scores

Embedded Microprocessor Benchmark Consortium

About EEMBC

Revision 2 Cortex core

Full Debug/Trace

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:DNH8S,QWHUUXSW:,&FRQWUROOHU

Embedded Trace Macrocell (ETM)

Memory Protection Unit (MPU)

Fully-compliant USB2.0

Simultaneous Ethernet, USB and CAN operation without bottlenecks

Average 35% Higher Performance than leading competitors (EEMBC)

Flash Accelerator for Zero-Wait Flash at max clock

100 MHz Clock Speed

15

13

Advantages over Cortex M3 competition

Ethernet, USB On-The-Go/Host/Device and CAN simultaneously

LPC1700 operates high-bandwidth comm. peripherals without

bottlenecks

LPC1700 has been certified by EEMBC at 72,100, and 120 MHz

NXPs performance advantage is even greater at higher clock speeds

LPC1700 executes application code on average 35% faster than the

leading Cortex-M3 competitors when running at the same clock speeds

Based on results EEMBC

LPC1700 is the industrys highest performance Cortex-M3 MCU

Summary

Benchmarks

16

14

Memory Support

Max Clock of competitor is 72 MHz (with 2 wait states)

EEMBC Benchmark Results

19

17

18

8 KB ROM
Flash program/erase APIs

On-Chip ROM

Allows CPU and DMA accesses to be spread over 3 separate RAMs

that can be accessed simultaneously.

Two additional 16 KB SRAM separate slave port on the AHB

multilayer matrix.

20

32 KB SRAM accessible by the CPU and DMA controller on a higher

speed bus

Total 64 KB

On-Chip SRAM

Maximum 512 KB
Zero wait-state performance with Flash Accelerator

On-chip Flash

Memory Support Explained

Memory Protection Unit (MPU)

Booting

Flash Accelerator

Internal Memories

Memory Support

A background region

Eight separate memory regions, 0-7

Export of memory attributes to the system

Overlapping regions

Independent attribute settings for each region

Memory Protection Unit (MPU)

100MHz, 80MHz, 60MHz, 40MHz and 20 MHz

Configuring Flash Timing

Just one register configuration- FLASHCFG

Flash Accelerator

23

21

Booting

DMA Support

Nested VIC

Clocking

Key System Blocks

24

22

Clocking Explained

27

25

Clock source for the RTC block, the main PLL, and subsequently the CPU.
1 Hz clock to RTC

RTC oscillator

Clock source for the CPU, with or without using the PLL.
The main oscillator also provides the clock source for the dedicated USB
PLL
Operates at frequencies of 1 MHz to 25 MHz

Main oscillator

Clock source for the WDT, and/or as the clock that drives the PLL and
subsequently the CPU
The nominal IRC frequency is 4 MHz 1% accuracy over the entire temp
and voltage range

Internal RC oscillator

Clock Structure (Inputs)

Clock OUT

Input clock frequency from the main oscillator only (10-25MHz)

Output frequency of 48MHz used only by the USB subsystem
Dedicated to provide clocking for the USB interface to allow added
flexibility for the main PLL settings

USB PLL (PLL1)

Input clock frequency in the range of 32 kHz to 50 MHz.

May run from the main oscillator, the internal RC oscillator, or the
RTC oscillator
Output frequency from 10 MHz up to the max. CPU rate

Main PLL (PLL0)

Clock Structure (PLLs)

28

26

http://www.arm.com/pdfs/IntroToCortex-M3.pdf

Tail-chaining achieves much lower latency by replacing serial stack pop and
push actions that normally take over 30 clock cycles with a simple 6 cycle
instruction fetch

In the case of back-to-back interrupts, traditional systems would repeat the

complete state save and restore cycle twice, resulting in higher latency

NVIC Interrupt Tail Chaining

Priority pre-emption
Tail chaining

Advanced features

Deterministic interrupt latency

An External Non-Maskable Interrupt (NMI)

Grouping of priority values into group priority and sub-priority fields

LPC1700 supports 35 vectored interrupts with

programmable 32 priority levels for each interrupt

LPC1700 NVIC Features

31

29

12

PUSH

ISR

MemManage Fault
Bus Fault
Usage Fault
Reserved
SVCall
Debug Monitor
Reserved
PendSV
SYSTICK
Interrupt#0
-------

4
5
6
7-10
11
12
13
14
15
16
------

Interrupt#239

Hard Fault

256

NMI

Exception Type
Reset

No.
1

Priority

247

----

NA

NA

-1

-2

-3 (Highest)

Type of Priority

settable

settable

settable

settable

settable

NA

settable

settable

NA

settable

settable

settable

fixed

fixed

fixed

Descriptions

External Interrupt #240

---------------------------

External Interrupt #0

System Tick Timer

Pendable request for System Device

Breakpoints, watch points, external debug

System Service Call

Exceptions due to program errors

Fault if AHB interface receives error

MPU violation or access to illegal locations

Default fault if other handler not implemented

Non-Maskable Interrupt

Reset

12

POP

Cortex-M3 Exception Types

Cortex-M3

IRQ

ARM7 does not have deterministic interrupt latency

32

30

Cortex-M3 has an interrupt latency of 12 cycles and 12 cycles to return

from servicing

Deterministic interrupt latency

NVIC Interrupt Latency

Reserved
PendSV
Systick
IRQ0
More IRQs

0x34
0x38
0x3C
0x40
---------

SVCall
Debug Monitor

0x30

Reserved

0x1C 0x28
0x2C

Bus Fault
Usage Fault

0x18

Memory Manage

0x10
0x14

NMI
Hard Fault

0x08
0X0C

Reset

0x00
0X04

Vector
Initial Main SP

Address

5:0

4:1

3:2

2:3

1:4

0:5

PRIGROUP
(3 bits)

0 bit for group, 5 bits for sub-priority

1 bit for group, 4 bits for sub-priority

2 bits for groups, 3 bits for sub-priority

3 bits for groups, 2 bits for sub-priority

4 bits for groups, 1 bit for sub-priority

5 bits for groups, 0 bit for sub-priority

Binary Point
(Group: sub)

Bits

16

32

Levels

Pre-empting Priority
(Group Priority)

Bits

32

16

Levels

Sub-Priority
(Sub-Level)

If PRIGROUP = 2, then 5 bits used to format peripheral interrupt level will be defined
XXXXX where XXXXX groups (can have 32 groups), via software - cannot set subpriority within group.

If PRIGROUP = 5, then 5 bits used to format peripheral interrupt level will be defined
as XX : YYY where XX groups (can have total 4 groups), and YYY sub-priority
within each group (can have total 8 sub-priorities within each group)

If PRIGROUP = 3, then 5 bits used to format peripheral interrupt level will be defined
as XXXX : Y where XXXX groups (can have total16 groups), and Y sub-priority
within each group (can have total 2 sub-priorities within each group)

Interrupt Prioritization

Via the Vector Table Offset (Register

contained in the NVIC)

Vector Table can be relocated to

SRAM

Set up by hardware during Reset

Main stack pointer initial value in

location 0

Vector Table contains addresses

(vectors) of exception handlers and
ISRs

Vector Table starts at location 0

Cortex-M3 Vector Table

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33

PRIGROUP
(3 bits)

0:5

1:4

2:3

3:2

4:1

5:0

0 bit for group, 5 bits for sub-priority

1 bit for group, 4 bits for sub-priority

2 bits for groups, 3 bits for sub-priority

3 bits for groups, 2 bits for sub-priority

4 bits for groups, 1 bit for sub-priority

5 bits for groups, 0 bit for sub-priority

Binary Point
(Group: sub)

Bits

16

32

Levels

Pre-empting Priority
(Group Priority)

Bits

32

16

Levels

Sub-Priority
(Sub-Level)

We can set PRIGROUP to 4. We can have 8 groups total and 4 sub-levels within each group.
We set priority field (bit 23:19) of EINT0 to 2 so it will 00010 which means EINT0 is from
group 0 and has sub-priority of 2 within group 0
We set priority field (bit 15:11) of GPIO Interrupt (EINT3) to 1 so it will be 00001 which means
GPIO Interrupt (EINT3) is from group 0 and has sub-priority of 1 within group 0
So if both interrupts take place at the same time, GPIO Interrupt will be serviced first and then
EINT0 Interrupt (example of Tail-Chaining)

Example: We have two interrupts in our system - EINT0 and GPIO Interrupt and we
want to assign both interrupts under the same group with different sub-priorities where
GPIO Interrupt has a higher sub-priority than EINT0

Interrupt Prioritization

The software programmable PRIGROUP register field of

the NVIC chooses how many of the 5-bits are used for
group-priority and how many are used for sub-priority

Controlled by PRIGROUP field of the Application Interrupt

and Reset Control register in NVIC

On the LPC1700, each interrupt source has an 5-bit

interrupt priority value

Interrupt Prioritization

36

34

1010010110110110

10100101
10110110
01111000
001
00
1 0 0 00
11
01
01

15 Serial Interfaces

Single and burst

requests supported

SSP, I2S, UART, ADC

& DAC. DMA can also
be triggered by a timer
match condition

Eight DMA channels

with a four-word FIFO
per channel

AHB Bus master

DMA Support

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37

8 Frame FIFOs for both Transmit and Receive and multi-protocol

capabilities.
4 to 16 bits frame sizes
DMA support
Maximum possible speed of the SSP 50 Mbits/s (Master Mode), 8 Mbits/s
(Slave Mode)

SSP controller (Synchronous Serial Communication)

Synchronous, Serial, Full Duplex Communication.

SPI master or slave.
8 to 16 bits per transfer
Programmable clock polarity and phase for data transmit/receive
operations
Maximum possible speed of the SPI (master/slave) 12.5 Mbits/sec

SPI controller (Serial Peripheral Interface)

SPI0/ SSP(0 &1)

General Purpose IO

Analog Blocks

Motor Control

Timers

15 Serial Interfaces

Peripheral Support

40

38

UART1 is identical to UART0/2/3, with the addition of a modem

interface and RS-485/EIA-485 modes, no IrDA support

IrDA support for infrared communication

EIA-485/RS-485 and 9-bit mode support

Modem control support

DMA support

Fractional divider for baud rate control, auto-baud capabilities, and

implementation of software or hardware flow control

16 byte Receive and Transmit FIFOs.

UARTs (0, 1, 2 & 3)

43

MCLK

WS

SD

MCLK

WS

SD

CK

Audio Codec

Ethernet Interface
Contains a Ethernet MAC (Media Access Controller) with RMII
interface (reduced Media Independent Interface)
Supports 10 or 100 Mbps PHY devices
Dedicated DMA controller
Fully compliant with 802.3x Full Duplex Flow Control and Half
Duplex back pressure

CAN2.0B controllers (Controller Area Network)

Full implementation of the CAN-Protocol according to the CAN
Specification Version 2.0B
Data rates to 1 Mbit/s on each bus
Built-in Hardware Acceptance Filter recognizes 11- and 29-bit Rx
Identifiers

CAN (1 & 2) & Ethernet

NXP

SCL

41

LPC1700

SDA

CK

The I2S input and output can each operate independently in both master and
slave mode

Supports Fast Mode Plus (I2C0 only)

I2C
Interface

Audio Master Clock input/output (used on many I2S codecs)

Bi-directional data transfer between masters and slaves

DMA support

4-wire combined transmit and receive connections

Supports 3-wire data transmit and receive OR

I2S

Digital Interface

I2C compliant bus interface, and can be configured as Master, Slave, or

Master/Slave.

I2C (0,1 & 2)

Analog Interface

44

42

45

Enabled by software but requires a hardware reset or a Watchdog

reset/interrupt to be disabled
Can be used in Deep Sleep mode
Debug mode (interrupt)

Watchdog Timer

47

Total 8 capture inputs, and 4 external match outputs

Timer as counter or timer mode.
Selected timer events can selectively generate DMA requests. This allows
for timed memory-to-memory transfers.
Match output can toggle, go high, go low or do nothing

General Purpose Timers

Timers (1)

Dedicated DMA controller

Built-in on-chip PHY for Device/Host/OTG functions.

USB 2.0 Full Speed (12 Mbps) Device and On-The-Go/Open Host
Control Interface.

USB

Seven match registers allow up to 6 single edge controlled or 3 double

edge controlled PWM outputs, or a mix of both types. The match registers
also several operations at match
May be used as a standard timer if the PWM mode is not enabled
Two 32 bit capture channels take a snapshot of the timer value when an
input signal transitions. A capture event may also optionally generate an
interrupt
Shadow latch mechanism

PWM timer

An interrupt is generated when the counter value equals the compare

value, after masking
This allows for combinations not possible with a simple compare

Repetitive Interrupt Timer (RIT)

Timers (2)

Systick timer

PWM (Timer operation)

Repetitive interrupt timer

Watchdog timer

Four General Purpose timers

Timers

48

46

Motor Control- An Overview

24-bit timer that counts down to zero and provides 10 millisecond time interval
between interrupts
Can be clocked internally by the CPU clock or by a clock input from a pin
(STCLK)
Default register settings gives a 10ms interrupt if the CPU clock rate is 100 MHz

Systick Timer

Timers (3)

51

49

MCOB0

MCOA1

MCOB1

Channel 1

Operating Modes

MCOA0

CAP

DT

MAT

LIM

TC

Motor Control PWMs

MCOA2

52

50

MCOB2

Channel 2

Select Channel
ADCR (7:0)

V3A VREFP VSSA VREFN

ADC
Inputs

7 6 5 4 3 2 1 0

DMA support

12-bit ADC

Optional conversion on transition on input pin or Timer Match signal

Burst conversion mode for single or multiple inputs

12 bit conversion rate of 200 KHz

ADDR7

ADDR0

Measurement range 0 V to VREFP (typically 3 V; not to exceed VDDA voltage

level)

Analog Blocks- 12-bit ADC

Quadrature Encoder
Interface (QEI)

55

53

10 bit digital to analog converter

Resistor string architecture
Buffered output
Power-down mode
Selectable speed vs. power

Two thresholds- 2.65V & 2.95V

BOD

Power-on-Reset (POR)

10 Bit DAC (Digital to Analog Converter)

Analog Blocks (contd.)

Can combine index and position interrupts to produce an

interrupt for whole and partial revolution displacement

Index counter for revolution counting

Velocity capture

Programmable for 2X or 4X position counting.

Digital filter with programmable delays for encoder input

signals

Tracks encoder position

QEI- Key Features

56

54

57

GPIO registers are accessible by the GP DMA

Mask registers allow treating sets of port bits as a group,

leaving other bits unchanged

59

GPIO registers are located on a peripheral AHB bus for fast

I/O timing

New configuration - open-drain mode (applies to all GPIO

pins)

All pins have configurable pull-ups/pull-downs

70 High Speed GPIOs (LQFP100) and 52 High Speed

GPIOs (LQFP80)

General Purpose I/O (GPIO)

RTC Domain

58

60

Up to 46 edge sensitive interrupt inputs (42 GPIO + 4 EINT) combined with

up to four level sensitive external interrupt inputs (EINT pins) as selectable
pin functions
The external interrupt inputs can optionally be used to wake up the
processor from Power-down mode

External interrupt inputs

GPIO & External Interrupts

RTC will work down as low as 2.1 V

RTC power supply is isolated from the rest of the chip

Dedicated 32 kHz ultra low power oscillator with dedicated battery

power supply pin

20 bytes of Battery-backed storage and RTC operation when power is

removed from the CPU

Uses power from the CPU power supply when it is present

Ultra-low power design to support battery powered systems. Less than

1 uA required for battery operation

Provides seconds, minutes, hours, day of month, month, year, day of week,
and day of year

Measures the passage of time to maintain a calendar and clock

RTC Features

Peripherals continue running

(Similar to Idle Mode on ARM7)

Wakeup >> External reset or any enabled interrupt which occurs

Main oscillator and all internal clocks except the IRC are stopped

Flash memory is in standby, ready for immediate use

Deep-Sleep

CPU execution is suspended

Sleep

Power reduced modes

Wide rage of clock sources to static clocking

Ability to divide down or shut off clocks to individual on-chip peripherals

Active Power options

Power Modes (1)

Wakeup Interrupt Controller

(WIC)

Power down modes

Power Domains

Power Management

63

61

All clocks including IRC are stopped. Internal voltage is turned off
Complete system state is lost, only special registers in the RTC domain
are preserved
Option to run RTC
Wake-up >>> reset or RTC interrupt

Deep power-down

Same as Deep-Sleep mode except Flash and IRC are shut down
State is preserved

Power-down

Power Modes (2)

VDDA
VREFP

12 Bit ADC (2.7 V to 3.6 V)

Power only to the RTC

No Battery RAM
Backup Registers (20 bytes)

VBAT pin (2.1 V to 3.6 V)

VDD(reg)(3V3) on-chip voltage regulator

VDD(3V3) I/O pads

Single 3.3 V power supply (2.4 V to 3.6 V)

Power domains

64

62

NXP has the best Debugging available on any Cortex M3

Support up to eight breakpoints and four watchpoints.

Embedded Trace Macrocell (ETM) interface (5 pins) for real-time trace

Serial wire debug (SWD) (two pins) and Serial wire output (SWO) (one pin)

Standard JTAG debug (5 pin)

Debug and trace functions are integrated into the ARMCortex-M3.

Emulation and debugging

Only available in Release 2 of Cortex-M3

NMI, External Interrupts EINT0 through EINT3, GPIO interrupts,

Ethernet Wake-on-LAN interrupt, Brownout Detect, RTC Alarm,
CAN activity interrupt and USB activity interrupt
In addition, the watchdog timer can wake up the part from Deep
Sleep mode if it is clocked by the IRC oscillator

Interrupts used:

Completely controlled in hardware (no programming

required)

Enables the chip to wake up from Deep Sleep and Power

down mode (without the use of NVIC)

Wakeup Interrupt Controller (WIC)

67

65

Overview of JTAG, SW and Trace Pins

Tools & Ecosystem

68

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Embedded Artists
Hitex LPC17xx-Stick
IAR KSDK-LPC17xx
Keil MCB17xx

ARM/Keil Vision3
CodeRed RedSuite
Hitex HiTOP
IAR Embedded Workbench for ARM

Thank You!

Plus many more tools available!

All debuggers supporting Cortex-M3

JTAG debuggers

IDEs

Evaluation boards

LPC1700 Tools Highlights

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www.nxp.com/lpczone

Complete listing of Tools

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