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http://ohotspot.blogspot.in/2012/09/time-borrowing-and-time-stealing.html
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[http://2.bp.blogspot.com/-OQZjCERGs7g/UETksjYiVGI/AAAAAAAAAAY/p8a-yhUGfzs/s1600/Fig1Zoom.jpg]
The above timing issue is resolved with SAME clock period of 5 ns, using TIME BORROWING principle as
shown in FIG # 2. In FIG # 2, FF1 is replaced with LATCH1 which is POSITIVE LEVEL sensitive. This OPENS the
LATCH1 at the same time as FF1 at 0ns, but closes LATCH1 at 2.5 ns ( at negative edge of CLK1), unlike FF1.
http://ohotspot.blogspot.in/2012/09/time-borrowing-and-time-stealing.html
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[http://2.bp.blogspot.com/-uJa7F20s1mg/UETlOq97eCI/AAAAAAAAAAg/FDp5ts54lVY/s1600/Fig2Zoom.jpg]
So, PATH # 1 has extra 2.5 ns to borrow from next cycle (as LATCH1 closes at 2.5 ns). Time borrowed by PATH#1
= 2 ns ( PATH # 1 delay (7 ns) CLK period (5 ns). PATH#1 can use the entire 2.5 ns, but uses only 2 ns, leaving a
positive slack of 0.5 ns.
Since LATCH1 closes at 2.5 ns, there is NO TIMING VIOLATION, as data from PATH # 1 -> LATCH1 arrived 0.5 ns
before LATCH1 is closed. Output of LATCH1 is immediately available for combinatorial PATH#2. PATH#2 starts right
where PATH #1 left off, as shown in the fig. (this is important to remember, as Prime Time uses this principle for
Time Borrowing, while reporting). PATH#2 adds 1 ns delay from where PATH#1 left off (@ 2 NS ) also referred as
the start point (not the pin G of LATCH1) for FF2.
PATH#2 could have used upto 3 ns (0.5 ns slack from previous stage + 2.5 ns of half-clk-period of current cycle),
but uses only 1 ns. Valid data is available for capture FF2 at 3 ns. Since rising edge of capture FF2 happens at 5 ns,
FF2 has positive slack of 2 ns (5 ns 3 ns).
This should clear the concept of borrowing time from next cycle & using the slack from previous cycle.
http://ohotspot.blogspot.in/2012/09/time-borrowing-and-time-stealing.html
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Timing is met with NO changes to clock, but just by replacing FF1 with LATCH1. Time borrowing stops once you
hit the pipeline with a Flip flop. Ideally, to exploit Time Borrowing principle fully, pipeline should employ only
LATCHES.
http://ohotspot.blogspot.in/2012/09/time-borrowing-and-time-stealing.html
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[http://4.bp.blogspot.com/-7z4Qf81EUEw/UETmHIKgGYI/AAAAAAAAAAo/dfWqdq9PHqY/s1600/Fig2B.jpg]
http://ohotspot.blogspot.in/2012/09/time-borrowing-and-time-stealing.html
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[http://2.bp.blogspot.com/-Y38ntIXSzew/UETmxVB5CBI/AAAAAAAAAAw/-Grkn-O3m_A/s1600/Fig3.jpg]
A] SCENARIO 1:
In SCENARIO 1, PATH # 1 delay = 6 ns; PATH # 2 delay = 1 ns; PATH # 3 delay = 8 ns; PATH # 4 delay = 1 ns.
LATCH#1 is opened at point (1) at CLK1. Data from LATCH#1 through PATH#1 is available 6 ns later from launch
point (1) at CLK1. Implies, valid data is available 1 ns (6 ns 5 ns) after LATCH#2 is opened at point (2) of CLK2.
Since PATH#2 has enough slack, PATH#1 was able to borrow 1 ns from PATH #2.
Similarly, PATH#3 with delay of 8 ns, borrowed 3 ns from succeeding stage. In either case, slack in prior stages
(between pts (2) and (3), pts (4) and (5) ) is NOT used fully, as PATH #2 and PATH # 4 has delays less than half-a-clk
period.
http://ohotspot.blogspot.in/2012/09/time-borrowing-and-time-stealing.html
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B] SCENARIO 2:
In SCENARIO 2, PATH # 1 delay = 6 ns; PATH # 2 delay = 1 ns; PATH # 3 delay = 2 ns; PATH # 4 delay = 1 ns.
In scenario 2, PATH#3 has delay of 2 ns which is less than the half-cycle period of CLK ( 5ns ). Implies, NO
BORROWING required from succeeding stage. This also means, had there been a FF instead of LATCH#4, it
wouldnt have made a difference.
NOTE: FF in place of LATCH#4, stops time borrowing we have seen from LATCH#1 -> LATCH# 3, at launch edge
of FF.
C] SCENARIO 3:
In SCENARIO 2, PATH # 1 delay = 6 ns; PATH # 2 delay = 7 ns; PATH # 3 delay = 5 ns; PATH # 4 delay = 3 ns.
In SCENARIO 3, there is 100% time borrowing its simply a huge combinatorial block between LATCH at start and
the last LATCH, where each stage AUTOMATICALLY borrowing time and rippling through to the final outputs.
LATCHES in between are just transparent delay elements.
In this scenario, if the circuit above had 4 FFs instead of 4 LATCHES, the 4 stage FF based pipeline would have
consumed 28 NS. Using Time Borrowing principle, pipe delay has been reduced to 20 ns.
If the principle of Time Borrowing is understood, its easy to figure out the max permissible BORROW TIME.
http://ohotspot.blogspot.in/2012/09/time-borrowing-and-time-stealing.html
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[http://1.bp.blogspot.com/-EQ_bBwJ7kXk/UETnUb5WWXI/AAAAAAAAAA4/A8BFfKQSCek/s1600/Fig4.jpg]
Posted 3rd September 2012 by Orange - Pit Stop For All your VLSI needs
Labels: Latch Designs, Time Borrowing, Time Stealing, Timing
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