VIGNANS LARA INSTITUTE OF TECHNOLOGY AND SCIENCE

(Affiliated to Jawaharlal Nehru Technological University, Kakinada)

Department of Electronics & Communication Engineering
DIGITAL SYSTEM DESIGN & DIGITAL IC APPLICATIONS

LESSON PLAN
Academic Year: 2015-16
Year/Semester: III/I
Regulation: R13
Branch: ECE
Section: C

Faculty name: Mr. J. Veerayya

Dept: Electronics & Communication Engineering
Periods: 5
Credits: 3

S.No.

Hour No.

Date

Topics to be covered

1
2
3
4
5
6
7
8
9
10
11

Unit-I (11)
1
2
3
4
5
6
7
8
9
10
11

30/6/2015
1/7/2015
2/7/2015
3/7/2015
4/7/2015
7/7/2015
8/7/2015
9/7/2015
10/7/2015
11/7/2015
14/7/2015

Digital Design Using HDL

Introduction
HDL Design Flow, Program structure
History of VHDL
VHDL Requirements, Levels of Abstraction
Elements of VHDL
Concurrent and Sequential statements
Packages
Libraries and Bindings
Object, classes and subprograms
Comparison of VHDL and Verilog
Revision

12
13
14
15
16
17
18
19
20
21
22
23

UNIT-II(12)
12
13
14
15
16
17
18
19
20
21
22
23

15/7/2015
16/7/2015
17/7/2015
21/7/2015
22/7/2015
23/7/2015
24/7/2015
25/7/2015
28/7/2015
29/7/2015
30/7/2015
31/7/2015

VHDL Modeling
Introduction
Simulation, Logic Synthesis
Inside a Logic Synthesizer
Constraints, Technology Libraries
VHDL and Logic Synthesis
Functional Gate-Level verification
Place and Route
Post Layout Timing Simulation
Static Timing
Major Netlist for design representation
VHDL Synthesis-Programming Approach
Revision

Remarks

24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

Unit-III (15)
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

1/8/2015
4/8/2015
5/8/2015
6/8/2015
7/8/2015
8/8/2015
11/8/2015
12/8/2015
13/8/2015
14/8/2015
18/8/2015
19/8/2015
20/8/2015
21/8/2015
22/8/2015

PLDs and Memories

Introduction
Programmable Read Only Memory
Programmable Logic Array
Programmable Array Logic Devices
ROM: Internal structure, 2D-Decoding
Commercial ROM types,
Timing and applications
Static RAM: Internal structure
SRAM timing
standard, synchronous SRAMS
Dynamic RAM: Internal structure
Timing
Synchronous DRAMs.
Design considerations of PLDs with relevant Digital ICs.
Revision

39
40
41
42
43
44
45
46
47
48

Unit-IV(12)
39
40
41,42
43,44
45
46
47
48
49
50

1/9/2015
2/9/2015
3/9/2015
5/9/2015
9/9/2015
10/9/2015
11/9/2015
12/9/2015
15/9/2015
16/9/2015

Digital Logic Families and Interfacing

Introduction to logic families
CMOS logic
CMOS steady state electrical behavior
CMOS dynamic electrical behavior
CMOS logic families.
Bipolar logic, transistor-transistor logic, TTL families
CMOS/TTL interfacing
Low voltage CMOS logic and interfacing
Emitter coupled logic.
Revision

49
50
51
52
53
54
55
56
57
58
59

Unit-V (12)
51
52
53
54
55
56
57
58
59
60
61

18/9/2015
19/9/2015
22/9/2015
23/9/2015
25/9/2015
26/9/2015
29/9/2015
30/9/2015
1/10/2015
3/10/2015
6/10/2015

60

62

7/10/2015

Combinational Logic Design

Adders & Subtractors, Ripple Adder
Look Ahead Carry Generator
Binary Parallel Adder, Binary Adder-Subtractor, ALU
Decoders, encoders
Three state devices
Multiplexers and demultiplexers
Code Converters, parity circuits,
Comparators, Cascading Comparators
Multipliers
Barrel Shifter, Simple Floating-Point Encoder
Dual Priority Encoder, modeling of Circuits by using
VHDL.
Revision

61
62
63
64
65
66
67
68
69
70
71

Unit-VI (11)
63
64
65
66
67
68
69
70
71
72
73

Signature of the Faculty

8/10/2015
9/10/2015
13/10/2015
14/10/2015
15/10/2015
16/10/2015
17/10/2015
21/10/2015
13/10/2015
21/10/2015
23/10/2015

Sequential Logic Design

SSI Latches and Flip-Flops
Counters, Design of Counters using Digital ICs
Ring Counter, Johnson Counter
Modulus N Synchronous Counters
MSI Registers, Shift Registers
Modes of Operation of Shift Registers
Universal Shift Registers
MSI Shift Registers
Design considerations with relevant Digital ICs,
Modeling of circuits by using VHDL.
Revision

Head of the Department