RVCE/F 63-00-07/11/2014

COURSE PLAN
Subject / Code: DIGITAL PRINCIPLES AND SYSTEM DESIGN

/ CS

6201
Course/ Branch:

BE / CSE

Year/Semester: 01 / 02

Course Credit: 3

Course Description:
To provide an in-depth knowledge of the design of digital circuits and the
use of Hardware Description Language in digital system design
Prerequisites:
1. CS 2202 Digital Principles and System Design
2. EC 2203 Digital Electronics
3. EE 2255 Digital Logic Circuits
Objectives of Course:
1.
2.
3.
4.
5.

Learn the various number systems.

Learn Boolean algebra
Understand the various logic gates.
Be familiar with various combinational circuits.
Be familiar with designing synchronous and asynchronous sequential
circuits.
6. Be exposed to designing using PLD
Learning Outcomes:
After completing the course the students will
1. Understand the various number systems and various logic gates
2. Understand the concepts of Boolean algebra
3. Recognize the Importance of designing synchronous and asynchronous
sequential circuits
4. Realize various combinational circuits.
Text Books:
1. Morris Mano M. and Michael D. Ciletti, Digital Design, IV Edition,
Pearson Education, 2008.

RVCE/F 63-00-07/11/2014

References:
1. John F. Wakerly, Digital Design Principles and Practices, Fourth Edition,
Pearson Education, 2007.
2. Charles H. Roth Jr, Fundamentals of Logic Design, Fifth Edition Jaico
Publishing House, Mumbai, 2003.
3. Donald D. Givone, Digital Principles and Design, Tata Mcgraw Hill, 2003.
4. Kharate G. K., Digital Electronics, Oxford University Press, 2010..
Similar Subjects Offered by Other Universities
S.N
o

Subject Name / code

Digital Design Principles

Digital Design

University
SRM
UNIVERSITY
SATHYABAMA
UNIVERSITY

Web Page

www.srmuniv.in
www.sathyabama
university.ac.in

LESSON PLAN
Total

S.
No

Topic

: 45 hours
Referenc
e Book
with
Page
Nos.

L
3

T
0

No. of
Periods

P
0

C
3

Cumulativ
e No. of
Periods

UNIT I: BOOLEAN ALGEBRA AND LOGIC GATES

1
2
3
4

Review of Number Systems

Arithmetic Operations
Binary Codes
Boolean Algebra and Theorems

Boolean Functions

6
7

Simplification of Boolean
Functions using Karnaugh Map
andTabulation Methods
Logic Gates

3 ( 47-51)
2(38-51)
4 (2-11)
1 (6-10)
1 (2-3)
1 (10-15)

1
1
1
1

1
2
3
4

1 (51-59)

1 (73-76)

RVCE/F 63-00-07/11/2014

NAND and NOR

Implementations

1 (117119)
1 (119121)

10

11

12

14

15

16

17

18

UNIT II: COMBINATIONAL LOGIC

1

Combinational Circuits

Analysis and Design Procedures

Circuits for Arithmetic

Operations

Code Conversion

Decoders and Encoders

Multiplexers and
Demultiplexers

Introduction to HDL

HDL Models of Combinational

circuits

1 (73-76)
4 (109111)
3 (187200)
4 (284285)
4 (285289)
4 (289304)
4 (289304)
1 (165178)
1 (181184)
1 (139140)

UNIT III: SYNCHRONOUS SEQUENTIAL LOGIC

1

Sequential Circuits

Latches and Flip Flops

Analysis and Design Procedures

State Reduction
and State Assignment

Shift Registers

Counters

HDL for Sequential Logic

Circuits

3 (253256)
1 (268277)
3 (260264)
1
(257,283)
1 (286291)
4 (392400)
4(398400)

19

20

22

23

24

26

27

RVCE/F 63-00-07/11/2014

UNIT IV: ASYNCHRONOUS SEQUENTIAL LOGIC

Analysis of Asynchronous
Sequential Circuits
Design of Asynchronous
Sequential Circuits
Reduction of State and Flow
Tables

1
2
3
4

Race-free State Assignment

Hazards

4 (138139)
4 (139134)
4 (150161)
1 (334336)
3 (512513)
1 (335336)

29

31

33

34

36

UNIT V: MEMORY AND PROGRAMMABLE LOGIC

1

RAM and ROM

Memory Decoding

Error Detection and Correction

Programmable Logic Array

Programmable Array Logic

Sequential Programmable
Devices
Application Specific Integrated
8
Circuits
CONTENT BEYOND THE SYLLABUS 7

1 (379)
1 (380381)
1 (391399)
4 (400417)
1 (418429)
1 (429433)
1 (418429)

37

38

39

41

43

44

45

WEB RESOURCES
www.notesengine.com

www.rejinpaul.com

www.5starnotes.com

www.vidyarthiplus.com

www.paprix.com

www.technical4u.com

Portions for Sessional Exam

Test No.
I

Topics
BOOLEAN ALGEBRA AND LOGIC GATES &

RVCE/F 63-00-07/11/2014

II
III

Model

COMBINATIONAL LOGIC
SYNCHRONOUS SEQUENTIAL LOGIC &
ASYNCHRONOUS SEQUENTIAL LOGIC
MEMORY AND PROGRAMMABLE LOGIC &
BOOLEAN ALGEBRA AND LOGIC GATES
BOOLEAN ALGEBRA AND LOGIC GATES
COMBINATIONAL LOGIC
SYNCHRONOUS SEQUENTIAL LOGIC
ASYNCHRONOUS SEQUENTIAL LOGIC
MEMORY AND PROGRAMMABLE LOGIC

Assignment Topics
1. Code Conversion. (Unit 02)
2. Latches and Flip Flops. (Unit 03)
3. Hazards. (Unit 05)
Prepared by

Approved by

Signature

Name
Designation
Date

M.SAKTHIMOHAN
ASSISTANT PROFESSOR

Dr.P.KOTTESWARAN
PROFESSOR & HEAD