How Circuit Analysis and Yield Optimization Can Be Used

To Detect Circuit Limitations Before Silicon Results

Carlo Roma Pierluigi Daglio Guido De Sandre Marco Pasotti Marco Poles
STMicroelectronics Agrate Brianza Milan - Italy
E-mail: - carlo.roma@st.com

Abstract
This paper presents a methodology for circuit analysis
and yield optimization, where the most important and
interesting features are the different modules with a
strong focus on circuit analysis and yield improvement of
the designed integrated circuits.
Moreover, the possibility to analyze and size mixedsignal circuit design by a high flexibility and interactive
use of the implemented methods and algorithms has been
successfully used by designers for an exhaustive analysis
of all devices to understand the circuit limitations before
silicon results.
In this case, we mainly focus on the usage of WiCkeD,
deeply integrated in the Cadence Analog Design
Environment.
The proposed approach leverages the integration of
WCDI/WiCkeD Cadence/MunEDA tools inside the Opus
Design Framework: WCDI to read and collect data from
Cadence Analog Design Environment and WiCkeD for
circuit analysis and optimization purposes.
Furthermore, the possibility both to detect all the
structural constraints (i.e. saturation condition, ...) with
feasibility analysis and to separate mismatch parameters
from statistical ones to show to the user which transistor
parameter pairs cause largest performance drop by
mismatch effect, allows to check, step by step, circuit
consistency and the performance behaviour over a
parameter during designing phases.
The possibility of exporting the Analog Design
Environment data towards WiCkeD for the synthesis
setup and, later on, after the yield optimization step, the
ability of annotating design parameters back to the
Cadence Design Framework II allowed us to formalize
and verify a methodology for circuit analysis and yield
improvement, whose functionality has been proven on
Non Volatile Memories (NVM) proprietary technologies.
Two main topics will be addressed in this paper: first we
focus on the different WiCkeD analysis and optimization
modules to show the main advantages of this
methodology, where circuit analysis is no longer a black
box.
Afterwards, we use WiCkeD to optimize a Bandgap
Voltage Reference to improve the yield, addressing
designers to better understand the circuit weakness.

Figure 1. Circuit Analysis & Yield Optimization Flow

1. Introduction
Nowadays, it is more and more important to design ICs
working properly at first silicon to reduce the risk of
missing market windows and to control the growing costs
of manufacturing processes. This is surely possible by
employing several skilled designers, but it can also be
improved by using dedicated state-of-the-art software
tools that can really be useful when the reduced channel
length and the lower power supply voltage become
critical parameters for the circuit reliability.
In such a context, in our opinion, it is valuable to use
commercial tools for analysis, optimization and sizing of
analog and mixed-signal designs when they allow to
deeply analyze different topologies to reach desired
results before silicon.
In our case, it has been possible to check the circuit
behaviour at different design stages, taking advantage of

Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED05)

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the different circuit analysis modules, which provide a

new methodology for an exhaustive analysis of all the
devices and to separate mismatch analysis from the
statistical one to show detailed parameter contribution
over performances and structural constraints.
Figure 1 shows the complete Circuit Analysis & Yield
Optimization Flow using the WiCkeD tool. Two stages
have been mainly taken into account: first a detailed
circuit analysis, then Nominal and Yield optimization are
performed. The proposed top-down methodology has
been qualified on several applications. In this paper, a
Bandgap Voltage Reference in 0.13P used as reference
for internal voltage generation in a flash memory macro
has been examined.

2. Bandgap Voltage Reference: Circuit

Description and Analysis

Table 1. Structural Constraint rules

The Bandgap Voltage Reference topology used to

validate our Analog Sizing and Optimization Flow is
shown in Figure 2. The output voltage reference is given,
according to [1], by:

Vbg (T )

V
V ln N
(1)
Rout be  th
R1 R 2

where: Rout is the output resistance (Fig. 2)

R1 , R2 are the PTAT resistors (Fig. 2)

The main specs to be investigated and verified in the [-50
150] C temperature and [ 1.08, 1.2, 1.32] supply
ranges are the following:
Vbg lower limit for the output voltage > 770mV
Vbg upper limit for the output voltage < 820mV
Vbg diff (max Vbg min Vbg) over the temperature range
(TC) < 8mV
Within the limitations of linear approximation, the
weighted sum of PTAT current and diode current
provides the thermal insensitivity for an ideal behaviour
in the whole temperature range. As the process
parameters can be spread into best, worst and typical,
taking also into account the thermal non-linearity present
in R, Vbe and Vth expressions, the voltage reference
output signal was not sufficiently temperature
independent.
Furthermore, keeping the typical corner process, but
looking at the supply range [1.08, 1.2, 1.32], an irregular
behaviour in the [-50 150] C temperature range was
seen for the lowest value, due to the compressed dynamic
range.

Figure 2. Bandgap Voltage Reference and Biasing

Circuitry
This lack of robustness has been confirmed by silicon
results, as shown in the example displayed in Figure 3. In
this case few chips worked properly as regards the output
voltage nominal value using the optimal trimming
configuration.
The spread in Vbg(T) might be explained by devices
mismatch, mainly caused by devices areas, overdrives
tradeoffs, power supply and temperature extreme values.
In this case, using WiCkeD circuit analysis and yield
improvement modules, it has been possible to check in
details the main reasons of the circuit wrong behaviour.

Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED05)

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The next circuit analysis is the Sensitivity analysis that

has been proven to be really useful to understand how
design parameters should be changed to improve
performances and structural constraints but, above all, to
remove design parameters with low influence on the
performances and structural constraints.

Figure 3. Silicon results for the original design

3. WiCkeD Methodology for Circuit

Analysis and Nominal Optimization
An accurate evaluation of the circuit behaviour has been
done together with the circuit designer, taking advantage
of the software modularity to separate the different kinds
of analyses. The circuit behaviour has been investigated
following the methodology shown in Figure 4.
Before focusing our analysis on each module, it is
important to point out that, consisting WiCkeD of
different modules, designers can rely on different analysis
results at any level of design stage following a consistent
personal flow, depending on the needs and on the features
of any circuit under study.
After the WCDI setup is done, the most basic analysis of
a circuit is a single simulation, which is performed using
the Simulation module.
At this level of analysis, the most important information
is focused on the structural constraint values (e.g.
saturation and inversion equations) to check how many of
them are fulfilled. It lets the designer check performances
and constraint values for the given parameter settings, as
well as the circuit setup correctness.
This shows which could be the main critical part of the
circuit and allows designers to explore the design space
over a parameter (in the pre-defined design parameter
range) to quickly check the circuit topology limits.

Figure 4. WiCkeD Analysis and Optimization Flow

This restricts the design space to the ones with the
highest relative influence, with the consequence both to
speed up the following analyses and to change the values
of the selected design parameters as little as possible from
the nominal point.
Another important analysis, useful before circuit
optimization and yield improvement, is the Monte Carlo
Analysis, which gives the designer insights on how
process variation influences a given design. It gathers
plenty of information such as how both performances and
structural constraints are influenced by statistical
parameters. These analyses showed their effectiveness for
a deeper circuit analysis to have more detailed
information about both circuit robustness, before yield
improvement, and circuit relative influence toward

Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED05)

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specific process parameters. In this way, designers are

able to address the yield improvement either using the
circuit under test or deciding to change topology when it
is needed.
The first circuit analysis allowing to detect circuit
limitations during the design (and not until the
manufacturing process) is the Feasibility analysis that
allows to reduce the design space to the smaller set of
technically useful designs, that is the Feasibility region.
Feasibility analysis interface provides two different fields,
where structural constraints are split in fulfilled and
violated. Furthermore, based on the sensitivity analysis
results, it is possible to enable only those relevant
parameters to find a feasible solution.
The purpose of the feasibility optimization is to change
the design parameter set such as all the given structural
constraints are fulfilled. This analysis demonstrated its
advantages for these three reasons:

i topology limits can be discovered at this level of

analysis

i faster convergence is guaranteed for sizing

algorithms

i all the structural constraints must be fulfilled

before Design Centering
I would like to point out that feasibility optimization is
based on two different algorithms to fulfill the sizing
rules. They are respectively find closest and find
central. The first one completes the optimization as soon
as all the structural constraints are fulfilled, while the
second one tries to overfulfill the structural constraints
before stopping. The big difference is that, using the first
one, the design parameter set will be changed as little as
needed to provide a solution where the design area is
comparable with the original one, when this is the most
important constraint. In our specific analysis, before
feasibility analysis, five structural constraints were out of
specs as displayed in Figure 5.
Taking into account the sensitivity analysis related
influence results, in a short time, we have been able to
fulfill all of them.
The possibility to separate in a well-structured database
the operating point status, together with the designer
experience, demonstrated how can be useful to separate
the most critical circuit parts. This allowed the designer to
correctly setup, during circuit design, all the structural
constraints, relaxing some of them (the most critical to be
fulfilled) to find a feasible solution, not easy to discover
in a short time without this module analysis.
Next step is the Nominal Optimization to size the circuit
such as, under the influence of the operating parameters,
given specifications are fulfilled as much as possible.

Figure 5. Feasibility Optimization

The optimization methodology is based on three different
algorithms:

i Least Square Method & Parameter Distance

i Stochastic is based on a random sequence
The Least Square Method algorithm stops after
performances fulfill the specifications, while the
Parameter Distance algorithm tries to overfulfill all the
performances.
Moreover, the Nominal Optimization interface allows to
select only those design parameters, which are most
relevant on the performances, based on the sensitivity
analysis results. In this way, the parameter design space is
restricted to the ones with the biggest relative influence
on the performances, with the result of speeding up the
optimization phase. Besides, the consideration of
structural sizing rules and constraints during the Nominal
Optimisation guarantees both a higher quality of the
nominal design and, at the same time, a reduced
simulation time needed for the optimization.
This kind of nominal optimization is useful, above all, for
circuits with a negligible sensitivity regarding the process
tolerances.

4. WiCkeD Methodology for Yield

Analysis & Yield Improvement
The circuit analysis and nominal optimization make the
device as much robust as possible, but without taking into
account the random effect impact to be able to estimate
and measure yield losses.

Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED05)

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The goal of Yield Optimization is to maximize the yield

of the circuit with respect to the given performance
specifications. Furthermore, it leads to a feasible solution,
i.e. the design parameter set will fulfill all the structural
constraints as well.
This analysis is driven by Worst Case Analysis (WCA),
which determines the robustness and partial parametric
yields for given specs on circuit performances with
respect to variations in the fabrication process and
changes in the operating parameters. This is shown in
Figure 6, where the WCA has been performed on the
original design and after nominal optimization and design
centering, to show how could the output of this analysis
be exploited to find the circuit weakness before silicon
results.

The last step is the Design Centering that automatically

tries to maximize the smallest worst case distance to
improve the circuit yield. The circuit optimization
provided a yield value equal to 82.2%, which has been
estimated with a Monte Carlo Analysis.

Figure 7. Mismatch Analysis results for two different

circuit circuit versions

5. Silicon Results
Optimization
Figure 6. Worst Case Analysis outputs
Another important feature for a further circuit
investigation is the Mismatch Analysis, which shows to
the user which transistor parameter pairs cause largest
performance drop by mismatch effect. The Bandgap
Voltage Reference mismatch analysis has been really
appreciated by designers because it allowed isolating the
main relevant mismatch pairs over performances and
understanding the influence of mismatch on this topology.
In Figure 7 the Mismatch Analysis results are related to
two different circuit versions, where the benefits achieved
modifying the MOS sizing for the second version,
according to the above-mentioned results, are shown.
This analysis has been useful to demonstrate that the yield
loss for the first topology was due to the mismatch
components, due to the need to generate constant
differences and ratios of currents with transistor pairs.
The yield has been increased reducing the relevant
mismatch pairs after design centering.

After

Yield

The preliminary silicon results shown in fig.3 are the

ones achieved using the first version of this Bandgap,
where the main purposes were to check the consistency
between silicon and WiCkeD results based on our own
statistical models as well as whether information from the
tool was in the right direction.
This topology has been designed in two versions, the
second one designed gathering all the information coming
from the different WiCkeD analysis and executing the
trimming under the constraint Rout/R1=cost to take into
account a second order effect for yield improvement.
Based on the analysis results, the highest yield value has
been 82.2%, so that a new topology has been used
providing an estimated yield value of 93% that will be
compared with silicon results at the end of this year.
Figure 8 shows the silicon results (11 out of 22) that are
in line with WiCkeD ones (48% the best yield value for
the first version).
Based on these results, this methodology demonstrated
that, when the level of accuracy of the statistical models is
fine, it helps to change topology before waiting for the
silicon results.

Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED05)

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the tool (feasibility analysis, sensitivity analysis,

mismatch analysis and worst case analysis), we have been
able to gather a plenty of useful information, needed to
really understand the impact of each effect over
performances and then concentrating our efforts on the
most relevant ones. Another important benefit to the
design quality derives from the circuit analysis done by
means of the extracted netlist from the parasitic extractor
to check the circuit behaviour with respect to the parasitic
components. Finally, all this information can be collected
in a datasheet in html format.

7. Conclusions

Fig 8. Silicon Results

Fig 9. Portion of the TCT9 layout including the

Bandgap Voltage Reference
Figure 9 shows a part of the TCT9 project, where the
Bandgap Voltage Reference is included.

6. WiCkeD Different Modules Benefits

In our mixed-signal design flow context, WiCkeD can
be involved in the top-down methodology to help
designers to deeply understand and evaluate the circuit
weakness and limitations.
The most interesting usage of the WiCkeD modules is
related to circuit analysis. In fact, exploiting at the
maximum the different circuit analysis module interfaces
and, consequentially, the separate databases created by

A circuit analysis and yield improvement methodology

has been presented in this paper to study a voltage
reference circuit with the idea to put in place an approach
to deeply analyse the circuit to find the best feasible
solution. These different analyses have been successfully
used by several designers to choose, among different
solutions, the one with the higher estimated yield. It has
been possible due to the good quality of the WiCkeD
results and the statistical parameters to get a good
agreement between silicon results and estimated yield.
Moreover, interesting results have been achieved,
showing that in this field of electronics, a tool with
powerful algorithms, an easy-to-use environment together
with the designer experience, is able to provide users with
either faster design cycle time when checking the
schematic architecture (rough sizing) or accuracy when
final results are needed (fine optimization).
In this way, designers can rely on a methodology to
increase the quality of critical analog blocks while
reducing the design cycle, so they can achieve first silicon
success on complex chips. The critical topology described
in this paper allowed us to setup a methodology
demonstrating the benefits of using state-of-the-art
software for circuit analysis and yield optimization
purposes.

Reference
[1] WiCkeD User Manual, Version 3.15.1, MunEDA GmbH,
Munich Germany.
[2] F. Schenkel, R. Schwencker, M. Pronath, H. Graeb, S.
Zizala, K. Antreich, Mismatch Analysis and Direct Yield
Optimization by Spec-Wise Linearization and FeasibilityGuided Search.
[3] K.K. Low, W. Stephen, A New Methodology for the
Design Centering of IC Fabrication Processes.
[4] R. Schwencker, F. Schenkel, H. Graeb, K. Antreich, The
Generalized Boundary Curve A Common Method for
Automatic Nominal Design and Design Centering of Analog
Circuits.

Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED05)

0-7695-2301-3/05 $ 20.00 IEEE