HERITAGE INSTITUTE OF TECHNOLOGY
Department of Electronics and Communication Engineering
This is to certify that the project thesis titled INPUT VECTOR DEPENDENT LEAKAGE CURRENT OF VLSI STANDARD CELLS IN 45NM TECHNOLOGY Has been currently undertaken by
Argha Rakshit
(Roll no12600311030)
Avirup Dutta Gupta
(Roll no12600311042)
Ipsita Basu
(Roll no12600311062)
Md. Maroof Khan
(Roll no12600311084)
Prathhana Roy
(Roll no12600311105)
In partial fulfilment for the award of the degree in Bachelor of Technology In Electronics and Communication Engineering West Bengal University of Technology, 2015
Under the supervision of

Prof. Krishanu Datta Project Guide & Associate Professor Department of Electronics and Communication Engineering Heritage Institute of Technology, Kolkata
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Heritage Institute of Technology
Affiliated to
West Bengal University of Technology
Certificate of
Approval*
The foregoing project report is hereby approved as a creditable study of an engineering subject carried out and presented in a manner satisfactory to warrant its acceptance as a prerequisite to the degree for which it has been submitted. It is understood that by this approval the undersigned don’t necessarily endorse or approve any statement made opinion expressed or conclusion drawn therein but approve the project report only for the purpose for which it is submitted.
Signature of the Examiners:
1…………………………………………….
2…………………………………………….
3…………………………………………….
*Only in the case the project report is approved
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Abstract
With rapid scaling of CMOS technology, sub threshold and gate leakage mechanisms have become dominant. With feature size scaling beyond 50nm, gate leakage has become comparable to sub threshold leakage. In such a scenario, gate leakage currents can no longer be ignored in NMOS devices that are switched OFF. In today’s technology reducing stand by power consumption is one of the key design goals for portable devices. In this study input vector dependency on standby leakage current of VLSI standard cells has been explored for a deep submicron technology (45 nm process node). It is observed that gate leakage current for NMOS devices is not negligible with respect to the subthreshold leakage current which dominates stand by current in VLSI standard cells. Maximizing stacking effect is the key to achieve min leakage of VLSI standard cells.
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CHAPTER[1]:INTRODUCTION
There are three major sources of power dissipation in digital CMOS circuits which are summarized in the following equation:
P avg =P switching + P Shortcircuit +P Leakage
= α 0>1 C L .V ^{2} dd .f clk +I sc .V dd +I leakage .V dd
The first term represents the switching component of power, i.e. the Dynamic Power Dissipation, where C _{L} is the load capacitance , f _{C}_{L}_{K} is the clock frequency and α→0 is the node transition activity factor (the average number of times the node makes a power consuming transition in one clock period).The second term ,i.e. ShortCircuit Power Dissipation is due to the direct –path short circuit current ,I _{S}_{C} , which arises when both the NMOS and PMOS transistors are simultaneously active , conducting current directly from supply to ground .Finally, Static (Leakage) Power Dissipation ,where the leakage current, I _{l}_{e}_{a}_{k}_{a}_{g}_{e} , which can arise from substrate injection and subthreshold effects, is primarily determined by fabrication technology considerations. In today’s technology Leakage power is dominating most of the chip has more than 50% leakage power.
[1.1] SOURCES OF LEAKAGE POWER:
There are four main sources of leakage current in a CMOS transistor (see Figure 1):
1. Subthreshold (weak inversion) leakage (I _{S}_{U}_{B} ),
2. Gate directtunnelling leakage (I _{G} ) ,
3. Gate induced drain leakage (I _{G}_{I}_{D}_{L} ), and
4. Reversebiased junction leakage current (I _{R}_{E}_{V} ).
Around 7080% of leakage current is I _{S}_{U}_{B}_{,} 2030% of leakage current is I _{G}_{a}_{t}_{e} (I _{G} +I _{G}_{I}_{D}_{L} ) and rest is
I REV.
Figure 1: Leakage current components in an NMOS transistor.
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[1.1.1]SUBTHRESHOLD LEAKAGE
The subthreshold leakage is the drainsource current of a transistor operating in the weak inversion region. Unlike the strong inversion region in which the drift current dominates, the subthreshold conduction is due to the diffusion current of the minority carriers in the channel for a MOS device. For instance, in the case of an inverter with a low input voltage, the NMOS is turned OFF and the output voltage is high. In this case, although VGS is 0V, there is still a current flowing in the channel of the OFF NMOS transistor due to the VDD potential of the VDS. The magnitude of the subthreshold current is a function of the temperature, supply voltage, device size, and the process parameters out of which the threshold voltage (V _{T}_{H} ) plays a dominant role. In current CMOS technologies, the subthreshold leakage current, I _{S}_{U}_{B} , is much larger than the other leakage current components. This is mainly because of the relatively low V _{T}_{H} in modern CMOS devices. I _{S}_{U}_{B} is calculated by using the following formula:
I _{S}_{U}_{B} = (W/L).μv _{T}_{H} ^{2} C _{S}_{T}_{H} .e ^{(}^{(}^{v} _{G}_{S} ^{} ^{v} _{T} ^{+} ^{η}^{v} _{D}_{S} ^{)}^{/} ^{η}^{v} _{T}_{H} ^{)} .( 1  e ^{(} ^{}^{v} _{D}_{S} ^{/}^{v} _{T}_{H} ^{)} )……….(1)
where W and L denote the transistor width and length of the MOS, µ denotes the carrier mobility, V _{T}_{H} =kT/q is the thermal voltage at temperature T,C _{S}_{T}_{H} =C _{D}_{E}_{P} +C _{I}_{T} ,denotes the summation of the depletion region capacitance and the interface trap capacitance both per unit area of the MOS gate , and η is the drain induced barrier lowering (DIBL) coefficient [2].
η is the slope shape factor and is calculated as:
η= 1 + (C _{S}_{T}_{H} /C _{O}_{X} )……….(2)
where C _{O}_{X} denotes the gate input capacitance per unit area of the MOS gate. When a long channel transistor
with V _{D}_{S} larger than a few V _{T}_{H} is in the OFF state (V _{G}_{S} =0), we have:
I _{S}_{U}_{B} = (W/L).μv _{t}_{h} ^{2} C
.10 ^{(}^{}^{V}^{T}^{/}^{S}^{)} …….(3)
_{s}_{t}_{h}_{.}
where S denotes the subthreshold swing parameter, which is defined as the inverse of the slope of the log10(I _{D}_{S} ) versus V _{G}_{S} characteristic and is equal to nν _{t}_{h} .ln(10). S is equal to the subthreshold voltage decrease required to increase I _{S}_{U}_{B} by a factor of ten.
It is highly desirable to have a subthreshold swing as small as possible since this is the parameter that determines the amount of voltage swing necessary to switch a MOSFET from OFF to ON state (typical values of S for bulk CMOS devices are 70110 mV/decade; the theoretical lower bound is 60 mV/decade corresponding to n=1.) This is especially important for modern MOSFETs with supply voltages reaching subone volt region. To minimize S, the thinnest possible gate oxide (since it increases Cox) and the lowest possible doping concentration in the channel (since it decreases C _{D}_{E}_{P} ) must be used. Higher temperature results in larger S value, and hence, an increase in the OFF leakage current.
In long channel devices, the influence of source and drain on the channel depletion layer is negligible. However, as channel lengths are reduced, overlapping source and drain depletion regions cause the depletion region under the inversion layer to increase. The wider depletion region is accompanied by a larger surface potential, which attracts more electrons to the channel. Therefore, a smaller amount of charge on the gate is needed to reach the onset of strong inversion and the threshold voltage decreases. This effect is worsened when there is a larger bias on the drain since the depletion region becomes even wider. More precisely,
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when a high drain voltage is applied to a shortchannel device, it lowers the barrier for electrons between the source and the channel, resulting in further decrease of the threshold voltage. The source then injects carriers into the channel surface (independent of gate voltage), causing an increase in IOFF. This phenomenon, which can be thought of as a lowering of V _{T}_{H} as V _{D}_{S} increases, is the DIBL effect. There is yet another phenomenon known as the “V _{T}_{H} Rolloff” whereby the VT of a MOSFET decreases as the channel length is reduced. In such a case, the subthreshold swing parameter degrades and the impact of drain bias on V _{T}_{H} increases. Finally, there is the wellknown “Body Effect” ,which causes an increase in V _{T}_{H} as the body of the transistor is reversebiased (i.e., VSB of an NMOS transistor is increased).
Clearly, decreasing the threshold voltage increases the leakage current exponentially. In fact decreasing the threshold voltage by 100mV increases the leakage current by a factor of 10. Decreasing the length of transistors increases the leakage current as well. Therefore, in a chip, transistors that have smaller threshold voltage and/or length due to process variation contribute more to the overall leakage.
Figure 2: I _{S}_{U}_{B} (V _{G}_{S} =0) trend as a function of temperature. Courtesy of Vivek De, Intel.
The subthreshold leakage current increases with temperature. Figure 2 shows the leakage current for several technologies for different temperatures. As one can see, I _{O}_{F}_{F} grows in each generation. Furthermore, in a given technology, the leakage current increases with the temperature. Ioff has a temperature sensitivity of 8 12 x/100oC.
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Figure 3: Power consumption of a die as a function of temperature. Courtesy of Vivek De, Intel.
Figure 3 shows the power consumption of a 15mm die fabricated in a 0.1 µ m technology with a supply voltage of 0.7V. Although the leakage power is only 6% of the total power consumption at 30°C, it becomes 56% of the total power at 110°C. This clearly shows the necessity of using leakage power reduction techniques in current designs. Putting it all together, Let I _{O}_{F}_{F} denote the leakage of an OFF transistor (V _{G}_{S} =0V for an NMOS device).From the above discussion,
we know thatI _{O}_{F}_{F} =I _{R}_{E}_{V} +I _{G}_{I}_{D}_{L} +I _{S}_{U}_{B} ………
Clearly, I _{R}_{E}_{V} and I _{G}_{I}_{D}_{L} are maximized when V _{D}_{B} = V _{D}_{D} . Similarly, for shortchannel devices, I _{S}_{U}_{B} increases with V _{D}_{B} because of the DIBL effect. Note the I _{G} is not a component of the OFF current, since the transistor gate must be at a high potential with respect to the source and substrate for this current to flow. Among the three components of I _{O}_{F}_{F} , I _{S}_{U}_{B} is clearly the dominant component. So the remainder of this paper focuses on I _{S}_{U}_{B} . More precisely, in the next two sections, methods are presented for decreasing the subthreshold leakage currents in circuits that are in STANDBY or ACTIVE state.
STACK EFFECT:
To limit the energy and power increase in future CMOS technology generations, the supply voltage (V _{D}_{D} ) will have to continually scale [9]. The amount of energy reduction depends on the magnitude of V _{D}_{D} scaling[10]. Along with V _{D}_{D} scaling, the threshold voltage (Vt) of MOS devices will have to scale to sustain the traditional 30% gate delay reduction. These V _{D}_{D} and Vt scaling requirements pose several technology and circuit design challenges [11]. One such challenge is the rapid increase in subthreshold leakage power due to V _{t} scaling. Should the present scaling trend continue it is expected that the sub threshold leakage power will become a considerable constituent of the total dissipated power[12]. In such a system it becomes crucial to identify techniques to reduce this leakage power component. It has been shown previously that the stacking of two off devices has significantly reduced sub threshold leakage compared to a single off device[13]. This concept of stack effect is illustrated in Figure 4.
(4)
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Figure 4: Leakage Current Difference between a Single OFF Device and a Stack of Two OFF Devices. As Illustrated by the energy Band Diagram, the Barrier Height is modulated to be higher for the Two Stack due to Smaller Drainto Source Voltage Resulting in Reduced Leakage.
Stack effect factor is defined as the ratio of the leakage current in one off device to the leakage current in a stack of two off devices. One solution to the problem of everincreasing leakage is to force a nonstack device to a stack of two devices without affecting the input load. By ensuring isoinput load, the previous gate’s delay and the switching power will remain unchanged. Logic gates after stack forcing will reduce leakage power, but incur a delay penalty.
[1.1.2].GATE DIRECT TUNNELLING LEAKAGE
The gate leakage flows from the gate thru the “leaky” oxide insulation to the substrate. In oxide layers thicker than 3–4 nm, this kind of current results from the FowlerNordheim tunnelling of electrons into the conduction band of the oxide layer under a high applied electric field across the oxide layer. For lower oxide thicknesses (which are typically found in 0.15µm and lower technology nodes), however, direct tunnelling through the silicon oxide layer is the leading effect. Mechanisms for direct tunnelling include electron tunnelling in the conduction band (ECB), electron tunnelling in the valence band (EVB), and hole tunnelling in the valence band (HVB), among which ECB is the dominant one. The magnitude of the gate direct tunnelling current increases exponentially with the gate oxide thickness T _{o}_{x} and supply voltage V _{D}_{D} . In fact, for relatively thin oxide thicknesses (in the order of 23 nm), at a V _{G}_{S} of 1V, every 0.2nm reduction in T _{o}_{x} causes a tenfold increase in IG [3]. Gate leakage increases with temperature at only about 2x/100oC. Note that the gate leakage for a PMOS device is typically one order of magnitude smaller than that of an NMOS device with identical T _{o}_{x} and V _{D}_{D} when using SiO2 as the gate dielectric. As transistor length and supply voltage are scaled down, gate oxide thickness must also be reduced to maintain effective gate control over the channel region. Unfortunately this results in an exponential increase in the gate leakage due to direct tunnelling of electrons through the gate oxide [4]. An effective approach to
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overcome the gate leakage currents while maintaining excellent gate control is to replace the currentlyused silicon dioxide gate insulator with highK dielectric material such as TiO _{2} and Ta _{2} O _{5} . Use of the highk dielectric will allow a less aggressive gate dielectric thickness reduction while maintaining the required gate overdrive at low supply voltages [5]. According to the 2003 International Technology Roadmap for Semiconductors (ITRS03) [6], highK gate dielectric is required to control the direct tunnelling current for low standby power devices in process technology nodes below 90 nm. HighK gate dielectrics are expected to be introduced in 2006.
[1.1.3]GATEINDUCED DRAIN LEAKAGE
The gate induced drain leakage (GIDL) is caused by high field effect in the drain junction of MOS transistors. For an NMOS transistor with grounded gate and drain potential at V _{D}_{D} , significant band bending in the drain allows electronhole pair generation through avalanche multiplication and bandtoband tunnelling. A deep depletion condition is created since the holes are rapidly swept out to the substrate. At the same time, electrons are collected by the drain, resulting in GIDL current. This leakage mechanism is made worse by high drain to body voltage and high drain to gate voltage. Transistor scaling has led to increasingly steep halo implants, where the substrate doping at the junction interfaces is increased, while the channel doping is low. This is done mainly to control punchthrough and draininduced barrier lowering while having a low impact on the carrier mobility in the channel. The resulting steep doping profile at the drain edge increases band to band tunnelling currents there, particularly as V _{D}_{B} is increased. Thinner oxide and higher supply voltage increase GIDL current. As an example, with a V _{D}_{G} =3V and T _{o}_{x} of 4nm, there is roughly a 10 fold increase in the GIDL current when VDB is increased from 0.8V to 2.2V.
[1.1.4].JUNCTION LEAKAGE The junction leakage occurs from the source or drain to the substrate through the reverse biased diodes when a transistor is OFF. A reversebiased pn junction leakage has two main components: one is minority carrier diffusion/drift near the edge of the depletion region; the other is due to electronhole pair generation in the depletion region of the reversebiased junction [7]. For instance, in the case of an inverter with low input voltage, the NMOS is OFF, the PMOS is ON, and the output voltage is high. Subsequently, the drainto substrate voltage of the OFF NMOS transistor is equal to the supply voltage. This results in a leakage current from the drain to the substrate through the reversebiased diode. The magnitude of the diode’s leakage current depends on the area of the drain diffusion and the leakage current density, which is in turn determined by the doping concentration. If both n and p regions are heavily doped, bandtoband tunnelling (BTBT) dominates the pn junction leakage [8]. Junction leakage has a rather high temperature dependency i.e., as much as 50 – 100 x/100 oC, but it is generally inconsequential except in circuits designed to operate at high temperatures (> 150oC.) Junction reversebias leakage components from both the sourcedrain diodes and the well diodes are generally negligible with respect to the other three leakage components.
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[1.2] DIGITAL GATE TIMING DEFINITION:
• Switching Speed  limited by time taken to charge and discharge, the capacitor C _{L} .
• Rise Time, T _{R} : waveform to rise from 10% to 90% of its steady state value
• Fall Time T _{F} : 90% to 10% of steady state value
• Delay Time, T _{D} : time difference between input transition (50%) and 50% output level
The below expression denotes average delay where τ _{p}_{L}_{H} defines the Response Time of the gate for a Low to
High Output Transition and τ _{p}_{H}_{L} refers to Low to High Transition. The τ _{P} of a gate defines how quickly it responds to a change at its output.
τ _{P} =( τ _{p}_{L}_{H} + τ _{p}_{H}_{L} )/2
(5)
Figure 5: Depiction Of Delay In The Response Time Of The Gate In Accordance With The Input Signal.
Figure 6: CMOS Inverter with a Capacitative Load, C _{L} , to Examine the Average Delay.
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Figure 6, shows the familiar CMOS i nverter with a capacity load C _{L} that represent s the load capacitance (input of next gates, output of this gat e and routing). Of interest is the voltage wav eform Vout(t) when the input is driven by a step waveform, V in(t) as shown in figure 7.
Figure 8 shows the trajectory of the 0V to V _{D}_{D} . Initially, the enddevice is
X1 on the characteristic curve. Appli cation of a step voltage (V _{G}_{S} = V _{D}_{D} ) at the in put of the inverter changes the operating point to X2. From there onwards the trajectory moves on the V _{G}_{S} = V _{D}_{D} characteristic curve towards point X3 at the origin. Thus i t is evident that the fall time consists of two intervals:
ntransistor operating point as the input volta ge, Vin(t), changes from
cutoff and the load capacitor is charged to V _{D}_{D} . This illustrated by
1. T _{F}_{1} =period during which the capa citor voltage, V _{O}_{U}_{T} , drops from 0.9V _{D}_{D} to (V
DD –V TN )
2. T _{F}_{2} =period during which the capa citor voltage, V _{O}_{U}_{T} , drops from (V _{D}_{D} –V _{T}_{N} ) to
0.1V _{D}_{D} .
Figure 7: V _{O}_{U}_{T} (t) when the Input Is Driven By A Step Wavefor m, V _{I}_{N} (t)
With further calculations it is found o ut that the expression for fall time is given b y
T _{F} = kn .C _{L} /V _{D}_{D} .Bn
(6)
From this expression we can see that the delay is directly proportional to the load capacitance. Thus to
achieve high speed circuits one has to
proportion to the supply voltage i.e. a s the supply voltage is raised the delay time i s reduced. Finally, the delay is proportional to the βn of the driving transistor so increasing the width of a transistor decreases the delay.
minimize the load capacitance seen by a gat e. Secondly it is inversely
Thus the fall time is faster than the ri se time primarily due to different carrier mob ility associated with the p
and n devices thus if we want TF=TR
so, width of the pmos must be greater than t hat of nmos.
Figure 8: Trajectory of NTransistor Operating Point
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[1.3]
PVT (Process Voltage Temperature) Variations:
As technology scales down to the deep submicron regime, the effects of semiconductor process variations are an increasingly significant and critical factor in the design of high performance CMOS circuits. Furthermore, as the process steps involved in the manufacture an IC becomes more complex as the overall circuit performance is now more sensitive to the underlying statistical process variations. Hence a precise knowledge of the effects of process variations is emerging as an integral part of the design methodology. This variation negatively impacts on circuit performance, and generates design specifications which are harder to meet, resulting in functional and parametric yield loss. Moreover, with technology scaling, these problems are becoming increasingly critical due to the tighter design requirements.
In semiconductor manufacturing, a process corner is an example of a designofexperiments (DoE) technique that refers to a variation of fabrication parameters used in applying an integrated circuit design to a semiconductor wafer. Process corners represent the extremes of these parameter variations within which a circuit that has been etched onto the wafer must function correctly. A circuit running on devices fabricated at these process corners may run slower or faster than specified and at lower or higher temperatures and voltages, but if the circuit does not function at all at any of these process extremes the design is considered to have inadequate design margin.
In order to verify the robustness of an integrated circuit design, semiconductor manufacturers will fabricate corner lots, which are groups of wafers that have had process parameters adjusted according to these extremes, and will then test the devices made from these special wafers at varying increments of environmental conditions, such as voltage, clock frequency, and temperature, applied in combination (two or sometimes all three together) in a process. Cornerlot analysis is most effective in digital electronics because of the direct effect of process variations on the speed of transistor switching during transitions from one logic state to another.
One naming convention for process corners is to use twoletter designators, where the first letter refers to the Nchannel MOSFET (NMOS) corner, and the second letter refers to the P channel (PMOS) corner. In this naming convention, three corners exist: typical, fast and slow. Fast and slow corners exhibit carrier mobility that is higher and lower than normal, respectively. For example, a corner designated as FS denotes fast NFETs and slow PFETs.
There are therefore five possible corners: typicaltypical (TT) (not really a corner of an n vs. p mobility graph, but called a corner, anyway), fastfast (FF), slowslow (SS), fastslow (FS), and slowfast (SF). The first three corners (TT, FF, SS) are called even corners, because both types of devices are affected evenly, and generally do not adversely affect the logical correctness of the circuit. The resulting devices can function at slower or faster clock frequencies, and are often binned as such. The last two corners (FS, SF) are called "skewed" corners, and are cause for concern. This is because one type of FET will switch much faster than the other, and this form of imbalanced switching can cause one edge of the output to have much less slew than the other edge.
Leakage current is a major drawback in nanoscale CMOS. Because of the continued scaling of technology and supplythreshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing lowpower digital circuits.
In nanometreCMOS circuits, the main leakage components are the subthreshold, gatetunneling and reverse biased junction bandtobandtunnelling (BTBT) leakage currents. As transistor geometries decrease, it is necessary to reduce the supply voltage to avoid electrical breakdown and obtain the required performance.
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However, to retain or improve performance, it is necessary to reduce the threshold voltage (Vth) as well, which results in an exponential increase of subthreshold leakage. To control shortchannel effect and increase the transistor driving strength in deepsubmicron (DSM) circuits, gateoxide thickness also becomes thinner as technology scales down.
The aggressive scaling in the gate oxide results in a tunnelling current through the oxide, which is a strong exponential function of the oxide thickness and the voltage magnitude across the oxide. In scaled devices, the higher substrate doping density and the application of “halo” profiles cause significantly large reverse biased junction BTBT leakage currents through the drain and sourcesubstrate junctions.
We have used two different process corners model. Firstly, Nominal Model, in this model the corner type is TT i.e. Typical Typical, the Voltage is 1.0V and the operating Temperature is 27 °C. The other model is FF i.e. Fast Fast corner based. For this variational model the Voltage is 1.1V. It is used for three different operating Temperatures, which are 0 °C, 27 °C and 110 °C.
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CHAPTER [2] :SIMULATION
Technology used: PTM 45nm Model File.
Tools used: Tanner Tool
[2.1].SIZING OF STANDARD CELLS:
Another important factor for our study is proper sizing of PMOS and NMOS such that the equivalent resistance of the p network and the n network is always same .
The expression for R _{O}_{N} = L/(KW(V _{g}_{s}  V _{t} – V _{d}_{s} ))
(6)
when the MOS is in Linear Region.
Where W is the width of the MOS.
When NMOSes are connected in series then to get resistance of p network and n network to be same (R) that is equivalent to an inverter, resistance of each MOS should be R/n where R is the required equivalent resistance. Now as resistance is inversely proportional to width, so the width of the MOS es in series has to be increased n*times.But when NMOS es are connected in parallel we consider the discharging time topology that is the lesser the value of resistance the faster an RC network would discharge. So each of the parallel networks should have least resistance that is resistance equal to the equivalent inverter resistance that is R. So, each of the MOS in parallel will have same width.
[2.2] Fanout4
This inverter circuit is then used as a block for ease of simulation.
Figure 7: Fanout4 Inverter Circuit
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Data for 45 nm Nominal Model:
Wp 
Wn 
Wp/Wn 
Output Rise 
Output Fall 
Rise Delay 
Fall Delay 
Average Delay 
1.67 
3.33 
0.501502 
11.79 
30.52 
36.35 
11.79 
24.07 
2.5 
2.5 
1 
48.9188 
28.5188 
25.299 
14.8419 
20.07045 
3 
2 
1.5 
42.874 
30.43 
22.543 
16.5935 
19.56825 
3.33 
1.67 
1.994012 
40.692 
33.092 
21.675 
18.225 
19.95 
3.57 
1.43 
2.496503 
40.0456 
36.12 
21.439 
19.905 
20.672 
3.73 
1.27 
2.937008 
40.1486 
38.942 
21.5062 
21.4087 
21.45745 
3.75 
1.25 
3 
40.1972 
39.3532 
21.527 
21.626 
21.5765 
3.89 
1.11 
3.504505 
40.7889 
42.7147 
21.768 
23.3884 
22.5782 
4 
1 
4 
41.618 
46.109 
22.078 
25.1 
23.589 
Plot for Rise & Fall Delay against ratio Wp/Wn for 45 nm Nominal Model
It is observed that Rise Delay and Fall Delay is equal for Wp/Wnas 3:1 for 45nm nominal which forms the basis of our further simulations study.
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[2.3] LOGICAL EFFORT
The method of logical effort is founded on a simple model of the delay through a single MOS logic gate. The model describes delays caused by the capacitive load that the logic gate drives and by the topology of the logic gate. Clearly, as the load increases, the delay increases, but delay also depends on the logic function of the gate. Inverters, the simplest logic gates, drive loads best and are often used as amplifiers to drive large capacitances. Logic gates that compute other functions require more transistors, some of which are connected in series, making them poorer than inverters at driving current. Thus a NAND gate has more delay than an inverter with similar transistor sizes that drives the same load. The method of logical effort quantifies these effects to simplify delay analysis for individual logic gates and multistage logic networks.
The logical effort of a logic gate tells how much worse it is at producing output current than is an inverter, given that each of its inputs may present only the same input capacitance as the inverter. Reduced output current means slower operation, and thus the logical effort number for a logic gate tells how much more slowly it will drive a load than would an inverter. Equivalently, logical effort is how much more input capacitance a gate must present in order to deliver the same output current as an inverter. It is measured as a ratio of capacitance of an input pin for a particular gate to that for an inverter.It is dependent on the width of each transistor.
Some of the standard cells with sizing is given below:
Figure 8: Schematic diagram of 3 input NOR
This is Three Input NOR circuit. All the NMOS in the PullDown network are in parallel to each other, so width of individual NMOS does not change, as already mentioned. In the PullUp network, all the PMOS are in series, so individual resistance of PMOS will get divided by 3 and since width is inversely proportional to the resistance, the width of the PMOS should increases 3 fold, that is PMOS have 9µmwidth and NMOS have 1 µm width.
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Logical effort of pin with voltage source 2 is 2.5, with voltage source 3 is 2.5 , with voltage source 4 is 2.5 since they have same width.
Figure 9: Schematic Diagram of OAI (A+B).C)
In the PullDown network, (A+B) and C are in series so equivalent width of (A+B) and C should be 2µm. And as A and B are in parallel so each should have width 2µm.
For the PullUp network, (A+B) are in parallel with C. So, (A+B) and C should have width 3µm. And as A and B are in series so each has width increased 2 times as two are in series. Hence, Width of PMOS_A and PMOS_B is 6µm. Width of PMOS_C is 3µm
Logical Effort for Pin A and Pin B is 2, whereas, the Logical Effort for Pin C is 1.25 .
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Figure 10: Schematic Diagram of AOI (AB+C)
For the given AOI circuit,
In the PullDown network, A and B are in series with C in parallel with them. So, A, B and C must have same width as they are the part of a parallel network. So their widths are 1µm each of A, B and C.But individually A and B are in series so width increases 2 folds. Hence, Width of NMOS_A and NMOS_B is 2µm. Width of NMOS_C is 1µm
In the PullUp network A and B are in parallel with each other and is in series with C. Similarly A and B have a width of 6 micron such that the equivalent width is 3micron.
Logical Effort for Pin A and Pin B is 2, whereas, the Logical Effort for Pin C is 1.75
In similar way we can find the logical effort for other Standard cells, which are as follows,
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Table for Logical Effort of Various Circuits:
Cell 
Input Pin 
Logical Effort 

A 
1.25 

2 
Input NOR 
B 
1.25 
A 
2.5 

3 
Input NOR 
B 
2.5 
C 
2.5 

A 
1.25 

2 Input NAND 
B 
1.25 

A 
1.5 

3Input NAND 
B 
1.5 

C 
1.5 

A 
2 

AOI 
B 
2 

C 
1.75 

A 
2 

OAI 
B 
2 

C 
1.25 
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[2.4] PROCESS CORNER FOR MAXIMUM LEAKAGE:
[2.4.1] Inverter Circuit:
Figure 11: Schematic Diagram of Inverter
Process 
Voltage 
Temperature 
Input 
Total Leakage Current 
Remarks 

(in V) 
(°C) 
Vector 
I 
LEAKAGE (nA) 

TT 
1.0 
27 
0 
90.39 
 

1 
149.4 

FF 
1.1 
0 
0 
640.5 
Maximum 

1 
1302.0 
Leakage 

FF 
1.1 
27 
0 
600.1 
 

1 
1212.0 

FF 
1.1 
110 
0 
556.3 
 

1 
1067.0 
From the above data, it is observed that for the PVT variation, according to Nominal Model (TT 27 °C), the Leakage current is Minimum, and for FF 0°C, it is the worst condition as Leakage current is Maximum.
Page 21 of 51
[2.4.2]
NAND Circuit:
Figure 12: Schematic Diagram of2 Input NAND Gate
Voltage 
Temperature 
Input Vector 
Total Leakage Current I LEAKAGE (in nA) 

Process 
(in V) 
(°C) 
Remarks 

A 
B 

0 
0 
11.82 

0 
1 
181.3 

TT 
1.0 
27 
1 
0 
57.79 
 
1 
1 
291.8 

0 
0 
26.58 

0 
1 
1279 
Maximum 

FF 
1.1 
0 
1 
0 
290.3 
Leakage 
1 
1 
3416 

0 
0 
2689 

0 
1 
1200 

FF 
1.1 
27 
1 
0 
281.4 
 
1 
1 
3079 
Page 22 of 51
From the above data it is observed that for the PVT variation, according to Nominal Model (TT 27 °C), the Leakage current is Minimum and for FF 0 °C, it is the worst condition as Leakage current is Maximum.
[2.4.3]NOR Circuit
Figure 13: Schematic Diagram of2 Input NOR Gate
Voltage 
Input Vector 
Total Leakage 

Process 
Temperature 
Current 
Remarks 

(in V) 
(°C) 
A 
B 
I 
LEAKAGE (nA) 

0 
0 
1738 

0 
1 
112 

TT 
1.0 
27 
1 
0 
1051.2 
 

1 
1 
4.0 

0 
0 
3564 

0 
1 
502 
Maximum 

FF 
1.1 
0 
1 
0 
39.8 
Leakage 

1 
1 
10.56 
From the above data it is observed that for the PVT variation, according to Nominal Model (TT 27 °C), the Leakage current is Minimum and for FF 0 °C, it is the worst condition as Leakage current is Maximum.
Hence from the above three circuits we can conclude that, for Minimum Leakage the Nominal Model is suitable. So for the all the circuits further to be used in this project, the model file that will be used is the Nominal Model where the Process Corner is TT (Typical Typical), Voltage V _{D}_{D} is 1.0 V and operating Temperature is 27 °C.
Page 23 of 51
[2.5] LEAKAGE ANALYSIS FOR VARIOUS INPUT VECTOR OF SIZED VLSI STANDARD CELLS
[2.5.1] INVERTER
Figure 14: Circuit Diagram for Inverter
Figure 15: Schematic diagram of inverter
Page 24 of 51
Leakage current(nA)
Ammeter
Index
Input Vector
0
1
Type
_{1}
Gate current of PMOS_1
N
N
_{2}
Source current of PMOS_1
90.38
149.4
_{3}
Substrate current of PMOS_1
N
N
_{4}
Drain current of PMOS_1 &
NMOS_1
90.18
149.5
_{5}
Gate current of NMOS_1
3.6
15
_{6}
Substrate current of NMOS_1
N
N
_{7}
Source current of NMOS_1
86.58
165.5
_{8}
Total Leakage
_{9}_{0}_{.}_{3}_{9}
_{1}_{4}_{9}_{.}_{4}
N=NEGLIGIBLE AMOUNT OF CURRENT IN PICO AMPERE.
Using KCL: 

Input Vector 
Drain Current 
Source Current 
Gate Current 
Substrate Current 

(nA) 
(nA) 
(nA) 
(nA) 

PMOS_1 
0 
90.18 
90.38 
N 
N 

NMOS_1 
90.18 
86.58 
3.6 
N 

PMOS_1 
1 
149.5 
149.4 
N 
N 

NMOS_1 
149.5 
165.5 
15 
N 

Analysis: 
N=NEGLIGIBLE AMOUNT OF CURRENT IN PICO AMPERE. 
In order to maintain the ratio Wp:Wn= 3:1, the equivalent resistance of the PullUp Network and PullDown Network must remain the same. To achieve this, the width of PMOS is 3 µm and the width of NMOS is
1µm.
It is observed that the substrate leakage is negligible for both NMOS and PMOS and the gate leakage is negligible for PMOS. So body effect is not playing any crucial role here. So for our further study we are neglecting substrate leakage.
Another interesting conclusion is that the gate current when the NMOS is on is greater than the gate current when the NMOS is off. The first current is called the tunnelling current and the second current of the NMOS which is off is due to gate induced drain leakage. The ratio that we obtained is 4.16 for inverter which is the basic circuit in our study. Very similar ratios are obtained for other standard cells, which has been discussed later.
Page 25 of 51
[2.5.2] 2 INPUT NAND
Figure 16: Circuit Diagram for 2 Input NAND Gate
Figure 17: Schematic diagram of 2 input NAND
Page 26 of 51
Leakage current(nA) 

Ammeter Index 
Type 
Input vector 

0 0 
0 1 
1 0 
1 1 

Gate current of 

1 
PMOS_1 
N 
N 
N 
N 
Source current of 

2 
PMOS_1 
5.907 
N 
N 
149.4 
Drain current of 

3 
PMOS_1 
5.7 
181.1 
N 
149.5 
4 
Total Leakage 
11.81 
181.3 
57.78 
298.8 
Drain current of 

5 
NMOS_1 
11.4 
181.1 
57.58 
299 
Source current of 

6 
NMOS_1 &Drain current of NMOS_2 
4.164 
173.9 
57.62 
311 
Gate current of 

7 
NMOS_2 
N 
31.45 
1.452 
30 
Source current of 

8 
NMOS_2 
4.161 
205.9 
56.24 
363.1 
Source current of 

9 
PMOS_2 
5.907 
N 
57.78 
149.4 
Gate current of 

10 
PMOS_2 
N 
N 
N 
N 
Drain current of 

11 
PMOS_2 
5.7 
N 
57.58 
149.5 
Gate current of 

12 
NMOS_1 
7 
7 
N 
32.66 
N=NEGLIGIBLE AMOUNT OF CURRENT IN PICO AMPERE.
Page 27 of 51
Using KCL
Source 

Input vector 
Drain Current (nA) 
Current (nA) 
Gate Current (nA) 

PMOS_1 
5.7 
5.907 
N 

PMOS_2 
0 
0 
5.7 
5.907 
N 
NMOS_1 
11.4 
4.164 
7 

NMOS_2 
4.164 
4.161 
N 

PMOS_1 
181.1 
181.3 
N 

PMOS_2 
0 
1 
N 
N 
N 
NMOS_1 
181.1 
173.9 
7 

NMOS_2 
173.9 
205.9 
31.45 

PMOS_1 
N 
N 
N 

PMOS_2 
1 
0 
57.58 
57.78 
N 
NMOS_1 
57.58 
57.62 
N 

NMOS_2 
57.62 
56.24 
1.452 

PMOS_1 
149.5 
149.4 
N 

PMOS_2 
1 
1 
149.5 
149.4 
N 
NMOS_1 
299 
311 
12.66 

NMOS_2 
311 
342.1 
30 
Analysis:
N=NEGLIGIBLE AMOUNT OF CURRENT IN PICO AMPERE.
In order to maintain the ratio Wp:Wn= 3:1, the equivalent resistance of the PullUp Network and PullDown Network must remain the same. To achieve this, the width of PMOS is 3 µm and the width of NMOS is 2 µm.
Page 28 of 51
FACTORS AFFECTING LEAKAGE IN 2INPUT NAND GATE:
A 
B 
Total Leakage Current (nA) 
Factor Affecting Leakage Current 

1. 0 
0 
11.81 
best case 
Stack Effect 

2. 0 
1 
181.3 
 

3. 1 
0 
57.78 
 

4. 1 
1 
298.8 
worst case 
PMOS devices leaking in parallel 
∑ From the data, it is observed that the fundamental Network Theory i.e. Kirchhoff’s Law has been obeyed at every node, here, we are considering NMOS and PMOS as nodes.
∑ Due to the stacking effect, leakage through a logic gate depends on the applied input vector.
To
evaluate the effect of input vector selection in controlling leakage, the pulldown network of the two input NAND gate (a twotransistor stack) is considered. With both gates at logic “0”, the intermediate node voltage is positive (V _{m} ), resulting in a negative value of Vgs1. This reduces the
sub threshold current in M1. With all other input vectors, V _{g}_{s} of NMOS_1and NMOS_2 are either positive or zero. Thus, “00” gives the minimum sub threshold current flowing through a stack of two transistors. It has been shown that sub threshold current flowing through a stack of transistor decreases with an increase in the number of the “off” transistors.
∑ Whereas, maximum leakage current is obtained when the input vector is “11”. In this condition, both the NMOS are ON but both the PMOS are OFF. As the PMOS are in Parallel, both the devices will leak and the sum of it results in a higher Leakage current than that of rest cases.
Logical effort at input A&B is 1.25.
Page 29 of 51
[2.5.3] 3 INPUT NAND
Figure 1 8: Circuit Diagram for 3 Input NAND Gate
= (A
.B.C.)
Figure 19: Schematic diagram of 3 input NAND
Page 30 of 51
Leakage Current(nA) 

Ammeter 
Type 

Index 
Input Vector 

0 0 0 
0 0 1 
0 1 0 
0 1 1 
1 0 0 
1 0 1 
1 1 0 
1 1 1 

1 
Total Leakage Current 
14.41 
17.55 
11.33 
272.1 
9.03 
86.7 
74.9 
448.1 
Drain Current of 

2 
PMOS_1 
4.2 
8.77 
5.6 
272.1 
N 
N 
N 
149.4 
Drain Current of 

3 
PMOS_2 
4.8 
8.77 
N 
N 
4.5 
86.7 
N 
149.4 
Drain Current of 

4 
PMOS_3 
4.8 
N 
5.6 
N 
4.5 
N 
74.8 
149.4 
Source Current of 

5 
PMOS_1 
4.49 
8.5 
5.4 
271.9 
N 
N 
N 
149.4 
Source Current of 

6 
PMOS_2 
4.49 
8.5 
N 
N 
4.3 
86.4 
N 
149.4 
Source Current of 

7 
PMOS_3 
4.49 
N 
5.4 
N 
4.3 
N 
74.89 
149.4 
Gate Current of 

8 
PMOS_3 
N 
N 
N 
N 
N 
0 
N 
N 
Gate Current of 

9 
NMOS_1 
10 
10 
10 
10 
N 
N 
88.5 
50 
Drain Current of 

10 
NMOS_1 
13.78 
17.1 
10.9 
271.9 
8.3 
86.4 
N 
448 
Source Current of 

11 
NMOS_1 & Drain Current of NMOS_2 
2.91 
6.2 
N 
261 
8.6 
86.5 
88.75 
498.6 
Gate Current of 

12 
NMOS_2 
N 
N 
12 
50 
2.8 
2 
N 
48 
Source Current of 

13 
NMOS_2 & Drain Current of NMOS_3 
2.903 
6.2 
11 
309.2 
5.6 
84.5 
89.56 
544 
Gate Current of 

14 
NMOS_3 
N 
50 
N 
50 
N 
50 
16 
48 
Source Current of 

15 
NMOS_3 
2.903 
54.4 
10.9 
357.3 
5.6 
132 
73.24 
592.9 
N=NEGLIGIBLE AMOUNT OF CURRENT IN PICO AMPERE.
Page 31 of 51
USING KCL:
Input Vector 
Drain 
Gate Current 
Source 

Current(nA) 
(nA) 
Current(nA) 

PMOS_1 
4.49 
N 
4.2 

PMOS_2 
4.49 
N 
4.8 

PMOS_3 
4.49 
N 
4.8 

NMOS_1 
0 
0 0 
13.78 
10 
2.91 
NMOS_2 
2.91 
N 
2.903 

NMOS_3 
2.903 
N 
2.903 

PMOS_1 
8.5 
N 
8.77 

PMOS_2 
8.5 
N 
8.77 

PMOS_3 
N 
N 
N 

NMOS_1 
0 
0 1 
17.1 
10 
6.2 
NMOS_2 
6.2 
N 
6.2 

NMOS_3 
6.2 
50 
54.4 

PMOS_1 
5.4 
N 
5.6 

PMOS_2 
N 
N 
N 

PMOS_3 
5.4 
N 
5.6 

NMOS_1 
0 
1 0 
10.9 
10 
N 
NMOS_2 
N 
12 
11 

NMOS_3 
11 
N 
10.9 

PMOS_1 
271.9 
N 
272.1 

PMOS_2 
N 
N 
N 

PMOS_3 
N 
N 
N 

NMOS_1 
0 
1 1 
271.9 
10 
261 
NMOS_2 
261 
50 
309.2 

NMOS_3 
309.2 
50 
357.3 
N=NEGLIGIBLE AMOUNT OF CURRENT IN PICO AMPERE.
Page 32 of 51
Drain Current 
Gate Current 
Source 

Input Vector 
(nA) 
(nA) 
Current (nA) 

PMOS_1 
N 
N 
N 

PMOS_2 
4.5 
N 
4.3 

PMOS_3 
4.5 
N 
4.3 

NMOS_1 
1 0 0 
8.3 
N 
8.6 
NMOS_2 
8.6 
2.8 
5.6 

NMOS_3 
5.6 
N 
5.6 

PMOS_1 
N 
N 
N 

PMOS_2 
86.7 
N 
86.4 

PMOS_3 
N 
N 
N 

NMOS_1 
1 0 1 
86.4 
N 
86.5 
NMOS_2 
86.5 
2 
84.5 

NMOS_3 
84.5 
50 
132 

PMOS_1 
N 
N 
N 

PMOS_2 
N 
N 
N 

PMOS_3 
74.8 
N 
74.8 

NMOS_1 
1 1 0 
N 
88.5 
88.75 
NMOS_2 
88.75 
N 
89.56 

NMOS_3 
89.56 
16 
73.24 

PMOS_1 
149.4 
N 
149.4 

PMOS_2 
149.4 
N 
149.4 

PMOS_3 
149.4 
N 
149.4 

NMOS_1 
1 1 1 
448 
50 
498.6 
NMOS_2 
498.6 
48 
544 

NMOS_3 
544 
48 
592.9 
Analysis:
N=NEGLIGIBLE AMOUNT OF CURRENT IN PICO AMPERE.
In order to maintain the ratio Wp:Wn= 3:1, the equivalent resistance of the PullUp Network and PullDown Network must remain the same. To achieve this, the width of PMOS is 3 µm and the width of NMOS is 3 µm.
In our study, we have examined the interdependence between I _{S}_{U}_{B} and I _{G}_{A}_{T}_{E} . However I _{G}_{A}_{T}_{E} in PMOS transistors and reverse I _{G}_{A}_{T}_{E} in OFF transistors was considered negligible. This fact does not hold true for 45nm and 32nm technologies.
Page 33 of 51
I _{G}_{A}_{T}_{E} leakage in the OFF NMOS transistor is comparable to that in the ON NMOS transistor. However, I _{G}_{A}_{T}_{E} in PMOS transistors is relatively less than in NMOS transistors and can be safely ignored. Here Substrate Leakage is also ignored.
FACTORS AFFECTING LEAKAGE IN 3INPUT NAND GATE
A 
B 
C 
Leakage Current (in nA) 
Factor Affecting Leakage Current 
0 
0 
0 
14.41 
 
0 
0 
1 
17.55 

0 
1 
0 
11.33 
 
0 
1 
1 
272.1 
 
1 
0 
0 
9.03 best case 
No I _{G}_{A}_{T}_{E} Drawn; Stack Effect 
1 
0 
1 
86.7 

1 
1 
0 
74.9 
No Stack Effect; I _{S}_{U}_{B}_{T} Dominates 
1 
1 
1 
448.1 worst case 
∑ From the data, it is observed that the fundamental Network Theory i.e. Kirchhoff’s Law has been obeyed at every node, here, we are considering NMOS and PMOS as nodes.
∑ Leakage Current is found to be minimum for vector “100” because “No I _{G}_{A}_{T}_{E} is drawn; Stack effect”. In this combination, NMOS_1 is ON so it doesn’t any gate current from supply voltage. Rests of the two NMOS are OFF and are in series, hence due to Stacking effect lows I _{S}_{U}_{B} flows.
∑ Another Category of input vector is “I _{G}_{A}_{T}_{E} drawn; Stack Effect”. In this combination, NMOS_1 is switched OFF and therefore draws I _{G}_{A}_{T}_{E} from power supply. Because there are two OFF NMOS in this combination, low I _{S}_{U}_{B} flows due to stack effect.
∑ In case of vector “010”, “I _{G}_{A}_{T}_{E} replaces I _{S}_{U}_{B} ”. In such cases where there is a nonconducting transistor above and below a conducting transistor, I _{G}_{A}_{T}_{E} replaces I _{S}_{U}_{B} . A positive potential is developed between the NMOS_1 and NMOS_2 due to I _{S}_{U}_{B} flowing through NMOS_1.Thevoltage developed is sufficiently small for NMOS_2 to exhibit I _{G}_{A}_{T}_{E} from its gate to drain. I _{G}_{A}_{T}_{E} further increases the voltage at the node. This increase in voltage reduces I _{S}_{U}_{B} through NMOS_1 and also reduces I _{G}_{A}_{T}_{E} . But the dependence of I _{S}_{U}_{B} on V _{G}_{S} is stronger than the dependence of I _{G}_{A}_{T}_{E} onV _{G}_{D} . Thus, I _{G}_{A}_{T}_{E} displaces I _{S}_{U}_{B} and remains as the only leakage component in the stack.
∑ The Last category is “No Stack Effect; I _{S}_{U}_{B} Dominates”, as stack effect is not possible in this case I _{s}_{u}_{b} leads to be the dominating factor in leakage. For “111”, it is the Worst case as three PMOS are in parallel, hence ISUB from all the PMOS collectively makes it the maximum leakage combination.
Page 34 of 51
∑ 
It is observed that for 3ip nand gate max leakage occurs when 3pmos es are in series that is for 111 combination and theoretically min leakage should occur for 000 combination. But this is not the case .We have taken readings of v _{g}_{s} and v _{d}_{s} for all 3 nmoses . The nmos with v _{g}_{s} most negative is the limiter of current in the entire circuit for a particular input combination. It is found out that the theoretical and practical values of ratios of channel currents after subtracting the gate leakage current is almost same. The theoretical value is found from the equation of sub threshold current. 

100 
000 

V 
_{d}_{s} (v) 
V 
_{g}_{s} (v) 
V 
_{d}_{s} (v) 
V 
_{g}_{s} (v) 

Nmos 1 
.225 
.225 
.984 
.156 

Nmos 2 
.77 
.105 
.129 
.027 

Nmos 3 
.105 
0 
.027 
0 

∑ 
From the table it is observed for 100 combination Nmos2 is the limiter. 

∑ 
After subtracting gate leakage current, channel current for 100 combination is (9.032.8)nA= 6.23 nA. For 000 combination channel current is 14.41nA. So practically ratio of channel current for 100 to 000 is .432. 

_{∑} 
_{I} sub _{=}_{I} 0 _{e} ((vgsvth)/n.vt) _{e} (vds/vt) 

∑ 
Putting the values from the above table and taking n to be 2 ,v _{t}_{h} =.22v,v _{t} (thermal voltage) =25 mV we get I _{s}_{u}_{b}_{(}_{1}_{0}_{0}_{)} /I _{s}_{u}_{b}_{(}_{0}_{0}_{0}_{)} = 0.013/0.0298= 0.436 
Logical effort at input A, B & C is 1.5
Page 35 of 51
[2.5.4] 2 input NOR
Figure 20: Circuit Diagram for 2 Input NOR Gate
Figure 21: Schematic diagram of 2 Input NOR Gate
Page 36 of 51
Ammeter 
Type 
Leakage current(nA) 

Index 

Input Vector 

0 0 
0 1 
1 0 
1 1 

1 
Total Leakage Current 
181.2 
299.3 
77.11 
3.103 
2 
Drain Current of PMOS_1 &Source Current of PMOS_2 
180.7 
298.9 
77.16 
3.104 
3 
Drain Current of PMOS_2 
180.3 
299.1 
77.16 
3.313 
4 
Drain Current of NMOS_1 
90.17 
N 
77.16 
1.656 
5 
Drain Current of NMOS_2 
90.17 
299.1 
N 
1.656 
6 
Gate Current of NMOS_1 
3.5 
N 
16.34 
15.95 
7 
Gate Current of NMOS_2 
3.5 
15.95 
N 
15.95 
8 
Source Current of NMOS_1 
86.57 
N 
93.11 
17.61 
9 
Source Current of NMOS_2 
86.57 
315 
N 
17.61 
N=NEGLIGIBLE AMOUNT OF CURRENT
Drain Current 
Source Current 
Gate Current 

Input Vector 
(nA) 
(nA) 
(nA) 

PMOS_1 
180.7 
181.2 
N 

PMOS_2 
0 
0 
180.3 
180.7 
N 
NMOS_1 
90.17 
86.57 
3.5 

NMOS_2 
90.17 
86.97 
3.5 

PMOS_1 
298.9 
299.3 
N 

PMOS_2 
0 
1 
299.1 
298.9 
N 
NMOS_1 
N 
N 
N 

NMOS_2 
299.1 
315 
15.95 

PMOS_1 
77.16 
77.11 
N 

PMOS_2 
1 
0 
77.16 
77.16 
N 
NMOS_1 
77.16 
93.11 
16.34 
Page 37 of 51
NMOS_2 
N 
N 
N 

PMOS_1 
3.104 
3.103 
N 

PMOS_2 
1 1 
3.313 
3.104 
N 
NMOS_1 
1.656 
17.61 
15.95 

NMOS_2 
1.656 
17.61 
15.95 
Analysis:
N=NEGLIGIBLE AMOUNT OF CURRENT IN PICO AMPERE.
In order to keep the effective resistance of the pMOS and nMOS equal, the width of the pMOS and n MOS are fixed at 6u and 1u, respectively, thereby maintaining ratio of Wp :Wn at 3:1.
∑ In both the studies we observe that the fundamental law of network theory i.e. Kirchhoff’s Current Law has been obeyed at every node (considering, each mos to be a node).
∑ We also observe that maximum leakage current is obtained when both the sources are set to 0V. This is because both the nMOS are off simultaneously, and so their individual leakage currents are added up.
∑ Minimum leakage current is obtained when both the sources are set to 1V.This is because of the stack effect, resulting in decrease of the leakage current as the pMOS are in series
Logical effort at input A & B is 7/4.
Page 38 of 51
[2.5.5]3 input NOR
Figure 22: Circuit Diagram for 3 Input NOR Gate
Y= (A+B+C)
Figure 23: Schematic diagram of 3 Input NOR Gate
Page 39 of 51
Leakage Current (nA) 

Ammeter 

index 
Type 
Input Vector 

000 
001 
010 
011 
100 
101 
110 
111 

Total leakage 

1 
current 
272.3 
449 
116.3 
5.281 
94.81 
4.704 
4.098 
1.868 
2 
Drain current of PMOS_1 & Source current of 
271.7 
448.4 
115.7 
4.658 
94.87 
4.705 
4.099 
1.868 
PMOS_2 

3 
Drain current of PMOS_2 & Source current of 
271.7 
447.8 
115.8 
4.658 
94.87 
4.36 
4.233 
1.869 
PMOS_3 

Drain current of 

4 
PMOS_3 
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