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CAD for VLSI Design - II

Lecture 6 V. Kamakoti and Shankar Balachandran

Overview of this Lecture

• CMOS Transistor Theory

– Delay Issues (Cont’d)

• Types and effects of Capacitances on delay

Parasitic Capacitance

• Switching speeds of MOS systems strongly depend on the parasitic capacitances associated with MOSFETs and interconnections

• Total C load on the output of a CMOS gate is the sum of:

– Gate capacitance (C g )

– Junction capacitance due to the source and drain regions and their surroundings (C sb and C db )

– Interconnect (or routing) capacitance (C w )

• Gate oxide capacitance per unit area,

C

ox

=

εε

0

ox

t ox

MOSFET Capacitances

x d x d x d
x d
x d
x d

Gate Capacitance

• Gate capacitance, C g = C ox WL

• Total gate capacitance C g can be decomposed in two elements:

1. Overlap capacitance: due to the topological structure of the MOSFET. 2. Gate-to-Channel capacitance: due to the interaction between gate voltage and channel charge.

Gate Overlap Capacitance

• In reality , actual channel length, L eff < drawn length, L (mask length), due to the extension of the source and drain regions somewhat below the oxide by an amount x d , called the lateral diffusion, i.e., Leff = L – 2.x d

x d gives rise to overlap capacitance which is linear and has a fixed value.

C

gso

=

C

gdo

=

C xW

ox

d

=

CW

o

C o is overlap capacitance per unit transistor width (fF/μm)

Gate-to-Channel Capacitance

It has thee components: C gs , C gd and C gb

Gate-to-Channel Capacitance • It has thee components: C g s , C g d and C

Average Gate Capacitance

Average Gate Capacitance Region   C gb   C gs   C gd C g Cutoff

Region

 

C

gb

 

C

gs

 

C

gd

C

g

Cutoff

C

ox WL

eff

 

0

 

0

C

ox WL eff +2C o W

Linear

 

0

C

ox WL eff /2

C

ox WL eff /2

C

ox WL eff +2C o W

Saturation

 

(2/3)C ox WL e

 

0

(2/3)C ox WL eff +2C W

o

 

ff

 

Area and Side-wall Capacitance

• Area Capacitance (C area ) due to the bottom-plate junction formed by the source (drain) region with doping N D and substrate with doping N A (bottom area 5).

C

area

=

C WL

j

s

where C is junction capacitanceperunitarea

,

j

• Side-wall (perimeter) Capacitance (C sw ) formed by junctions 2, 3, and 4. These are surrounded by the p+ channel-stop implant with doping level N A + which is usually larger than that of the substrate larger capacitance per unit area.

C

where , C

length

(

CW

jsw

(

j sw

C

jsw

+⋅ 2

L

s

)

=

sw

is junction side-wall capacitanceperunit

=

Cx

jsw

j

)

MOSFET Capacitance Model

MOSFET Capacitance Model C C C g GS GD = C g b + C GS

C

C

C

g

GS

GD

=

C

g

b

+

C

GS

+

= CC +

gs

gso

= C

g

d

+ C

gdo

C

GD

Wire (Routing) Capacitance

Wire (Routing) Capacitance C w ≈ C + pp C fri nge ≈ ε ε ⋅

C

w

C +

pp

C

fri nge

ε

ε ⋅ wl

o o x

h

+

2 πε o x log ( ) h t
2 πε
o x
log
(
)
h t

Parallel-plate and Fringing Capacitance

Total Cap. t/h= 1 t/h= 0.5 C pp w t h w/t
Total Cap.
t/h= 1
t/h= 0.5
C pp
w
t
h
w/t

Modern Interconnect

Modern Interconnect • Inter-layer capacitance increases with decreasing feature sizes. • Multi-layer capacitive
Modern Interconnect • Inter-layer capacitance increases with decreasing feature sizes. • Multi-layer capacitive

• Inter-layer capacitance increases with decreasing feature sizes.

• Multi-layer capacitive interactions result in unwanted coupling among neighboring signals cross talk

Impact of Inter-layer Capacitance

Impact of Inter-layer Capacitance

Capacitances for a 0.25μm Process

Capacitance

Area Cap (fF/μm 2 )

Perim. Cap (fF/μm)

Poly - substrate

0.088

0.054

Metal1 - substrate

0.041

0.047

Metal2 - substrate

0.015

0.027

n+ diff - substrate

1.660

0.399

p+ diff - substrate

1.832

0.323

n+ overlap cap.

--

0.562

p+ overlap cap.

--

0.630

C

ox

5.951

 

Metal1 - poly

0.017

0.041

Metal2 – metal1

0.038

0.054

0.25μm Interconnect Hierarchy

0.25 μ m Interconnect Hierarchy Global Intermodule Intercell Intracell • Optimize interconnect structure at each

Global

Intermodule

Intercell

Intracell

• Optimize interconnect structure at each layer.

– for local wires, density and low C are important – use dense and thin wiring grid

– for global wires in order to reduce delays, use fat, widely spaced wires.

• Improve wire delays by using better material (Cu) and low-K dielectrics for insulators.

Electrical Wire Models

• Ideal Wire - it is simply a line with no attached parameters or parasitics it has no impact on electrical behavior.

• Lumped Model – simplified model simple and fast computation, e.g., lumped C, lumped RC or lumped RLC

computation, e.g., lumped C , lumped RC or lumped RLC C lumped = l wire .

C lumped = l wire .c wire

• Distributed Model - Parasitics of a wire are distributed along its length and are not lumped into a single position, distributed C, distributed RC, or distributed RLC

Elmore Delay Formula

Elmore Delay Formula • For an n stage RC chain, the first order time constant is

• For an n stage RC chain, the first order time constant is given by,

τ

n

n

i

= ∑ ∑

C

R

ij

i

=

1

j

=

1

=

CR

11

+

C

2

()

R

1

+

R

2

++

C

n

(

R

1

+ R ++

2

R

n

)

• If R i = R j and C i = τ

n

(

)

n

n + 1

C

= RC

j

for all i and j ,

2

(1i, j n) then,

Distributed RC Model for a Wire

Distributed RC Model for a Wire Using Elmore delay formula we can determine the dominant time

Using Elmore delay formula we can determine the dominant time constant of the wire, i.e., it is a first-order approximation.

Questions and Answers

Thank You