Bang-Bang type PLL for balanced three phase

voltages
It is essential that the PLL system should work under distorted utility conditions. Moreover, it also should be able to lock-in as fast as possible and provide
the reference signal without distortion. Since the PLL system is implemented in
a digital manner using a digital signal processor (DSP), a bang-bang type PLL
is proposed which gets locked faster and easier to implement for balanced grid
voltages. From the Figure 1 the grid voltages va , vb and vc in the d-q domain
va
vb
vc

vqe
abc
to
dq

vq
vd

dq
to
de qe

Comp

0 +
vd e

Oscillator
H

ce

se

Figure 1: Bang-Bang type PLL.

are
vq (n + 1) = va (n + 1)

(1)

vd (n + 1) = 0.57735(vc (n + 1) vb (n + 1))

(2)

voltages vd and vq in the de-qe domain are

vqe (n + 1) = vq (n + 1)ce (n) vd (n + 1)se (n)

(3)

vde (n + 1) = vq (n + 1)se (n) + vd (n + 1)ce (n)

(4)

difference equations for the harmonic oscillator can be written as

se (n + 1) = se (n) + e (n + 1).ts .ce (n)

(5)

ce (n + 1) = ce (n) e (n + 1).ts .se (n + 1)

(6)

where ts is the sampling time, equations (5) and (6) can be written in state
space form as




 

se (n + 1)
1 0
se
ce (n)
=
+
u(n + 1)
(7)
ce (n + 1)
0 1
ce
se (n + 1)
where
u(n + 1) = e (n + 1).ts

(8)

Using (4) and (7) it follows

vde (n+1) = vq (n+1)se (n1)+vq (n+1)u(n)ce (n1)+vd (n+1)ce (n1)vd (n+1)u(n)se (n)
(9)

The control which ensures vde = 0, can be found by solving the following equation:
vq (n+1)se (n1)+u(n) (vq (n + 1)ce (n 1) vd (n + 1)se (n))+vd (n+1)ce (n1) = 0.
(10)
It should be noted that the above equation is obtained by setting vde = 0 in
(9). For notational simplicity let us define
Qa

vq (n + 1)ce (n 1) vd (n + 1)se (n)

(n) vq (n + 1)se (n 1) + vd (n + 1)ce (n 1)

(11)
(12)

Using the above definition, (10) can be rewritten as

vde (n + 1) = (n) + Qa u(n)

(13)

from the above equation dead-beat type of control law can be derived as
u(n) = e (n)ts = Q1
a (n)

(14)

Since the above control law is computationally intensive. The objective of forcing vde towards zero can also be achieved by the following discontinuous control
u(n) = M sign(vde )

(15)

where M = Q1
a N and N is chosen so that
| | + N

(16)

where  is a small positive constant. It is straightforward to verify that the

control Eqn. (15) ensures decay of absolute value of vde . From (13) and (15) we
can write vde (n + 1) as
vde (n + 1) = (n) N sign(vde )

(17)

In the figure the block comparator is a switch, which switches between two
reference frequencies. They are upper (H ) and lower (L ) limits of e , and
switch state depends upon the error vde . The output of the comparator drives
the harmonic oscillator to reduce the error and locks to the system frequency.
Figure shows the characteristics of vde by switching (n) with a specific band.
To understand how
vde
approaches zero, consider the follwing two cases:
Case-1 when vde > 0, vde (n+1) = (n)N , for the condition of Eqn. (16)
it follows vde (n + 1) < 0. As shown in Figure 1 the control law ensures
decay of vde at certain minimum rate () and reaches to zero.
Case-2 when vde < 0, vde (n+1) = (n)+N , for the condition of Eqn. (16)
it follows vde (n + 1) > 0. In this case vde moves towards vde = 0 line at
certain minimum rate () of increase.
2

From Eqn. (16) it is clear that the minimum rate at which vde approaches to
vde = 0 is . By considering the minimum decay rate of absolute value of vde
(nf )max

vde (0)


(18)

where nf is the maximum sampling instants at which vde becomes zero. However, it is worth noting that when the value of is smaller, then the decay rate
of vde becomes higher. When = 0, the decay rate is N . By increasing the  the
decay rate of absolute value of vde increases. Whenever vde crosses vde = 0 line
from either side, the control law forces back vde on vde = 0 line. Eventually, this
leads to continuously crossing and recrossing of vde = 0 line. This phenomena is
called chattering [?]. To avoid the chattering a band across vde = 0 line can be
introduced; the switching takes place when vde is out side the band from either
side. This solution reduces the excessive crossing and recorssing of vde = 0 line.
Figure shows the simulation results of PLL for L = 46 Hz and H = 55 Hz.
Initially the grid frequency is set at 50 Hz, to observe the transient response
of the proposed system when t = 80 ms the grid frequency is switched to 45
Hz. Figure shows the tracking performance of PLL and response time of control
output vde . Figure shows the simulation results of PLL for L = 40 Hz and
H = 60 Hz. Initially the grid frequency is set at 50 Hz, when t = 80 ms the
grid frequency is switched to 45 Hz. Figure shows the tracking performance
of PLL for L = 35 Hz, H = 65 Hz. Initially the grid frequency is set at
50 Hz, when t = 80 ms the frequency is switched to 45 Hz. Figure shows the
tracking performance of PLL for L = 35 Hz and H = 65 Hz. Initially the
grid frequency is set at 55 Hz, when t = 80 ms the frequency is switched to 45
Hz. The effects of values of H and L upon the performance of PLL are as
follows:
Initially error is negative, so H is applied as an input to the harmonic oscillator. Due to this, the output frequency increases faster and waveforms
as shown in, gets locked faster. So increasing H will increase the response
time. During this time L is zero. This large difference in H L results
in fast locking.
Lower band (L ) if increased, will affect the response by increasing the
locking time, but the reference frequency should be within H and L .
Otherwise system will not get it locked.
From the experimental results for a given band of switching frequency the PLL
tracks the references in less than half cycle. The tasks carried out by the DSP
(TMS320VC33) for implementation of PLL takes 1.16 s in total for a time step
of 20 s. Where transformations conversion time is 660 ns and PLL algorithm
execution time is 500 ns. These results are well justified in terms of transient
response and code optimization.