ECE697BB Analog Handouts PDF

Analog Integrated Circuits
ANALOG INTEGRATED
CIRCUITS DESIGN
University of Massachusetts
Electrical and Computer Engineering Department
Omid Oliaei
Why Analog?
Real-world signals are Analog.
Signals generated by sensors are analog
Digital signal processing of signals requires Analog-to-Digital Conversion.
Analog signal needs to be amplified and filtered before A/D.
Amplifiers and Filters are Analog Circuits.
A/D is a Mixed-Signal Circuit.
Chapter 1
University of Massachusetts Amherst
ECE697BB/Oliaei
Digital signals in a digital communication system behave as analog signals

at certain stages of transmission, receive and processing.
Ex 1. Lossy Cable
Ex 2. Disc Drive
Ex 3. Wireless Receiver
Ex 3. Optical Receiver
Signal Attenuation, Noise and Distortion incurred in the propagation

channel require that the received signal be Amplified, Filtered and
Equalized using Analog circuits.
ECE697BB/Oliaei
Chapter 1
Why Integrated?
Larger integration larger complexity
Lower parasitics Higher speed
Lower cost
Moores Law: Number of transistors doubles every 18 months:
1960: 25 m Gate length
Today: 90 nm and 65 nm in production
45 nm and 32 nm are in lab. 22nm and 16nm on roadmap.
Why CMOS?
Digital (Main Driver)
Low Power, Simplicity, Scaling, Low cost
Analog
Integration with digital
Improved speed over years
Chapter 1
ECE697BB/Oliaei
What is Analog Design?

Per
fo
Dont Forget
Variations
rm a
nce
S ch
Analog
Design
s
C on
n
trai
atic
em
Layout
T es
t
ts
Levels of Abstraction
System Level
Circuit Level
Component Level
ECE697BB/Oliaei
Chapter 1
CAD TOOLS FOR CIRCUIT DESIGN

Two Dominant Suppliers:
Cadence
80% market share
Mentor Graphics 20% market share
Simulation:
System Level:
High-Level (Behavioral):
Low-Level (Electrical):
Matlab, SPW
Verilog, Verilog_A, Verilog AMS
SPICE, SPECTRE, ADS, Proprietary Tools
Cadence and Mentor Graphics Include tools for

Schematic Capture
Simulation
Layout
Chapter 1
ECE697BB/Oliaei
Customer
Specifications
Design House
Foundry
Schematic Capture
Netlist
Technology
Device Model
Electrical/Behavioral Simulations
Layout: Automatic/Manual
Masks
Design Rules Check (DRC)

Layout Versus Schematic (LVS)
Fabrication
Parasitic Extraction
Production
Chapter 1
Test
ECE697BB/Oliaei
Analog Design Space

Tradeoffs
Cost ?
Analog Design is a Multi-Dimensional Optimization Problem.

Improving one parameter always results in degradation of some others.
Chapter 1
ECE697BB/Oliaei
Basic MOS Device Physics

Understanding Device Physics is Essential to Analog Design.
MOS device is symmetric.
Side Diffusion
(Sio2)
Contact
(Metal)
NMOS
Bulk
Leff = Ldrawn 2 LD
Chapter 2
Ldrawn
Tox
0.25 m
5 nm
0.18 m
3.5 nm
0.13 m
2.2 nm
ECE697BB/Oliaei
NMOS
PMOS
MOS is a four-terminal device.

Substrate (bulk) of an NMOS is connected to the lowest potential.
Substrate (bulk) of a PMOS is connected to the highest potential.
All p-n junctions are reverse biased.
Conduction takes place beneath gate, between source and drain.
Chapter 2
ECE697BB/Oliaei
10
Complementary MOS Process (CMOS):

PMOS
NMOS
Chapter 2
PMOS
ECE697BB/Oliaei
11
MOS CHANNEL FORMATION
Cut Off
VG
GND
VG
Depletion
GND
VG
VTH
Inversion
GND
Chapter 2
ECE697BB/Oliaei
12
Device turn-on is a gradual phenomenon.

There exists several definitions for VTH.
One definition: when VG=VTH :
density of electrons on the interfaced equals density of holes in the substrate
VTH increases with increasing the substrate doping.
Adjusting VTH by ion implantation:
P+ layer increases VTH

ECE697BB/Oliaei
Chapter 2
13
PMOS IN INVERSION STATE
PMOS: Holes flow from Source to Drain.

NMOS: Electrons flow from Source to Drain.
Electrons have a higher Mobility. NMOS is faster than PMOS (~ 3 times).
Chapter 2
ECE697BB/Oliaei
14
MOS Symbols
Arrow indicates current flow from positive voltage to negative voltage polarity.
Chapter 2
ECE697BB/Oliaei
15
I-V CHARACTERISTICS
NMOS
Uniform Charge
Distribution
Larger VDS Larger Longitudinal Field

More Current
Larger VGS More Charge Carriers
Chapter 2
ECE697BB/Oliaei
16
I/V Characteristics (cont.)
ID = WCox[VGS VTH V ( x)]v

Given v = E and E(x) =
dV (x)
dx
ID = WCox[VGS VTH V ( x)]n

L
dV ( x)
dx
VDS
I dx = WC
D
x =0
[VGS VTH V ( x)]dV
ox n
V =0
1 2
W
ID = nCox L [(VGS V TH)VDS VDS ]
2
ECE697BB/Oliaei
17
I-V CHARACTERISTICS: Triode Region
Triode Region:
Almost Linear
ID nCox WL (VGS VTH )VDS
VDS < VGS VTH
1
W
2
2
cm 2 Electrons Mobility
V .s
W
L
[m]
[m]
Cox =
si
tox
[pF / cm ]
2
Oxide Capacitance
Device Width
si = 0.35 [ pF / cm]
Oxide Permittivity
Device Length
tox
Oxide Thickness
Chapter 2
ECE697BB/Oliaei
18
I-V CHARACTERISTICS: Saturation Region
'
DS
= V GS VTH
(Pinch off )
VDS > VGS VTH

ID =
nCox W
2
(VGS VTH ) 2
L
L L
ECE697BB/Oliaei
Chapter 2
19
MOS OPERATION REGIMES

Both PMOS and NMOS:
Triode Region
VDS < VGS VTH
Pinch-Off
VDS = VGS VTH
Saturation Region
VDS > VGS VTH
In saturation, MOS behaves as a current source.

Chapter 2
ECE697BB/Oliaei
20
Transconductance in Saturation Region
ID =
gm =
nCox W
2
(VGS VTH ) 2
ID
VGS VDS constant
gm = 2 nCox WL ID
= n Cox WL (VGS V TH)
2ID
VGS V TH
ECE697BB/Oliaei
Chapter 2
21
DRAIN-SOURCE RESISTANCE IN TRIODE REGION
1
W
2
2
ID = nCox WL (V GS VTH )VDS, V DS << 2(V GS VTH )

RON =
1
VDS
=
W
I DS nCox L (VGS VTH )
Voltage-Controlled Resistance
Chapter 2
ECE697BB/Oliaei
22
THRESHOLD VOLTAGE AND BODY EFFECT
VB < 0 attracts holes and widens depletion region

Larger VG > 0 to put opposite charge on gate
Larger VG > 0 to create inversion
Higher VTH
VTH = VTH 0 +
0. 3 < < 0. 4
F
2F + VSB 2F
Body effect coefficient

Source-Bulk voltage
Fermi level
ECE697BB/Oliaei
Chapter 2
23
CHANNEL LENGTH MODULATION: SATURATION REGION
L' = L L
1
1
(1 + L / L) = (1 + VDS )
L
L
nCox W
(VGS VTH ) 2 (1 + VDS )
ID =
2 L
1 / L' =
g DS =
1
I DS
nCox W
=
(VGS VTH ) 2 I DS ,
VDS
2 L
L
Chapter 2
ECE697BB/Oliaei
g DS
I DS
L
24
ECE697BB/Oliaei
25
SUBTHRESHOLD CONDUCTION
VGS
ID = I 0 exp
VT
For VGS<VTH, there exists a weak inversion layer causing a small diffusion current.
This leakage current causes increased power dissipation in digital circuits.
To operate in weak inversion, transistor must be wide low speed.
Application: Ultra Low-Power design.
Chapter 2
ECE697BB/Oliaei
26
MOS LAYOUT
Gate
Contacts (Poly)
(Metal)
Gate
Shared
Gate Contact
ECE697BB/Oliaei
Chapter 2
27
PARASITIC CAPACITANCES
Overlap
Bottom-plate
cap
Side-wall
cap
Junction capacitance increases non-linearly with reverse bias.

Chapter 2
ECE697BB/Oliaei
28
GAT-SOURCE AND GATE DRAIN CAPCITANCES
Qch WCox[VGS VTH V ( x)]

2
Cgs is maximum in the saturation region CGS 3 WLCox
1
Device is symmetric in the triode region CGS = CGD WLCox
2
ECE697BB/Oliaei
Chapter 2
29
LOW-FREQUENCY MOS SMALL-SIGNAL MODEL
VSB = 0
ro =
ID
g mb =
VSB 0
: Drain-source resistance
ID
= gm
VBS
2 2 F + VSB
: Bulk transconductance
saturation
Chapter 2
ECE697BB/Oliaei
30
HIGH-FREQUENCY SMALL-SIGNAL MODEL

Saturation
Triode
Chapter 2
Cut Off
ECE697BB/Oliaei
31
ECE697BB/Oliaei
32
ECE697BB/Oliaei
33
GATE ACCESS RESISTANCE

Two fingers
Reduce resistance
Gate resistance effect is significant at RF.

Chapter 2
ECE697BB/Oliaei
34
COMMON-SOURCE with RESISTIVE LOAD
Off
Sat.
Triode
Saturation
Av = gm RD
Deep triode
Chapter 3
ECE697BB/Oliaei
35
COMMON-SOURCE with RESISTIVE LOAD: Model
Av = gm ro || RD
RD
Av = g m ro
Chapter 3
ECE697BB/Oliaei
36
DIODE-CONNECTED MOS
Vx
= Ix
ro
Vx
1
1
=
|| r o
Ix gm + gmb
gm + gmb
(gm + gmb)V x +
ECE697BB/Oliaei
Chapter 3
37
COMMON-SOURCE STAGE with DIODE-CONNECTED LOAD
Av = gm1
Av =
1
gm1 1
=
gm2 + gmb2
gm2 1 +
(W / L)1 1
(W / L)2 1 +
Gain independent of bias current

Good gain accuracy: good matching
PMOS Diode-Connected Load
Av =
un (W / L)1
up (W / L)2
Gain independent of bias current

Gain set by two different types of transistor
Chapter 3
ECE697BB/Oliaei
38
COMMON-SOURCE with CURRENT SOURCE LOAD

Saturation
Large Output Voltage Compared with Resistive Load

All Transistors Need to be in Saturation for High Gain
M1 sets the Minimum Output Voltage
M2 Sets the Maximum Output Voltage
Av = gm ro1 || ro2
High-Resistance Node
Triode
Av = gm RON2
RON 2 =
Chapter 3
nC
W
ox
L 2
(VDD Vb | VTHP |)
ECE697BB/Oliaei
39
COMMON-SOURCE WITH SOURCE DEGENERATIONS

Gm =
gm
1 + gm RS
Av = Gm RD
Av =
gm RD
1+ gm RS
Including Second-Order Effects
Gm =
gm ro
RS + [1+ (gm + gmb )RS ]ro
Av = Gm RD || ROUT
Chapter 3
ECE697BB/Oliaei
40
COMMON-SOURCE OUTPUT RESISTANCE
ROUT = [1 + (gm + gmb )ro ]RS + ro
ROUT = ro ' ro [1+ (gm + gmb )RS ]

Av = Gm RD || ro '
Simplified Model
Av =
gm RD
RD
=
1+ gm RS
1/ gm + RS
ECE697BB/Oliaei
Chapter 3
41
SOURCE FOLLOWER
Small-Signal Model
Av =
gm RS
RS
RS
=
+
g
g
1+ (gm + gmb )RS 1/ g + ( m
mb
)RS 1/ gm + RS
m
gm
Output Resistance
Rout =
1
1
1
||
=
g m g mb g m + g mb
Source Follower Exhibits a high input resistance

and a low output resistance.
Chapter 3
ECE697BB/Oliaei
42
SOURCE FOLLOWER WITH FIXED BIAS CURRENT

Id1, thus, Vgs1- Vth1, are independent of Vin.
Load Effect on Gain
1
|| r || r || RL
gmb o1 o2
Av = 1
1
|| ro1 || ro2 || RL +
gm
gmb
Application: Buffering a High-Gain Stage
ECE697BB/Oliaei
Chapter 3
43
COMMON-GATE
DC coupling
Gain
Av =
AC coupling
Small-Signal Model
( g m + g mb )ro + 1
RD ( g m + g mb ) RD
ro + ( g m + g mb )ro RS + RS + RD
Output Resistance
Rout = {[1 + (gm + gmb )ro ]RS + ro }|| RD

Input Resistance
Chapter 3
Rin = ro ||
1
1
||
gm gmb
ECE697BB/Oliaei
44
CASCODE AMPLIFIER
AV gm1{[ro1 ro2 (gm 2 + gmb2 )] || RD ]}
Rout = {[1 + ( g m 2 + g mb 2 )ro 2 ]ro1 + ro 2 } || RD
[ro1ro 2 ( g m 2 + g mb 2 )] || RD
Shielding Effect of Cascode
AV gm1 [(ro1ro2 gm2 ) || (ro3ro4 gm3 )]
ECE697BB/Oliaei
Chapter 3
45
DIFFERENTIAL VERSUS SINGLE-ENDED
Single-Ended Source
Differential Sources
Advantage: Reduced Sensitivity to Supply Noise
Supply Noise
Clock Noise
ECE697BB/Oliaei
46
PSEUDO-DIFFERENTIAL AMPLIFIER
Disadvantage: Sensitive to Input Common-Mode Voltage
ECE697BB/Oliaei
Chapter 4
47
DIFFERENTIAL AMPLIFIER
Tail current: Rejects input common mode
4 I SS
V 2
I D nCox W nCoxW / L in
Gm =
=
2 L
Vin
4 I SS
V 2
nCoxW / L in
Vout1 Vout 2
= g m RD
Vin1 Vin 2
Differential-Mode Gain
Adiff =
Common-Mode Gain
Ac = 0
Chapter 4
ECE697BB/Oliaei
48
SMALL-SIGNAL ANALYSIS
Differential-Mode
Ad = g m RD
Virtual ground
Common-Mode
Ac =
ECE697BB/Oliaei
Chapter 4
RD / 2
1 /( 2 g m ) + RSS
49
COMMON-MODE RESPONSE
Load Resistor Mismatch
VX VY
g m RD
=
Vin ,CM
1 + 2 g m RSS
Transistor Mismatch
(g m1 g m 2 )RD
VX VY
=
Vin,CM
( g m1 + g m 2 ) RSS + 1
Chapter 4
ECE697BB/Oliaei
50
DIFF. AMP WITH ACTIVE LOAD
1
Ad = g mN ( g mP
|| roN || roP )
g mN
g mP
Ad = g mN (roN || roP )
Ad g m1[( g m 3 ro 3 ro1 ) || ( g m 5 ro 5 ro 7 )]
ECE697BB/Oliaei
Chapter 4
51
CURRENT MIRRORS
Reference Current
I OUT
n Cox W
2
R2
(
VDD VTH ) 2
L R2 + R1
Sensitive to VDD , Vth , W, L
Chapter 5
ECE697BB/Oliaei
52
CURRENT-BIASED DIFFERENTIAL AMPLIFIER
ECE697BB/Oliaei
Chapter 5
53
CASCODE CURRENT MIRROR
Low-Voltage Cascode
Chapter 5
ECE697BB/Oliaei
54
DIFFERENTIAL AMPLIFIER WITH

ACTIVE CURRENT MIRROR
Large-Signal Operation
Chapter 5
ECE697BB/Oliaei
55
DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD

Small-Signal Analysis
ID1 = I D3 = ID 4 = gm1,2 Vin / 2
I D2 = gm1,2 Vin / 2
Iout = I D2 I D4 = gm1,2 Vin , Gm = gm1, 2

Rout ro2 || ro4 , (2ro1,2 >> [1/ gm 3 ] || ro3 )
Chapter 5
ECE697BB/Oliaei
Av G m Rout
56
COMMON-MODE ANALYSIS
VF = Vx
Common-Mode Gain
ACM
g m1, 2
1
1 + 2 g m1, 2 RSS g m 3, 4
Common-Mode Rejection Ratio
CMRR =
ADM
= g m 3, 4 (ro1, 2 || ro 3, 4 )(1 + 2 g m1, 2 RSS )
ACM
ECE697BB/Oliaei
Chapter 5
57
FREQUENCY RESPONSE OF AMPLIFIERS

Single-Pole Passive RC
vi
Vo ( s )
1 / sC
1
1
=
=
=
Vi ( s ) R + 1 / sC 1 + RCS 1 + s / p
s = j
vo
p = 1 / 2RC
: pole frequency
Vo ( )
1
=
Vi ( ) 1 + jRC
Vo ( )
1
=
2
Vi ( )
1 + (RC )
VY
VX
Z2 =
Millers Theorem
Av
Av =
Chapter 6
Z1 =
Z
(1 Av )
ECE697BB/Oliaei
Z
(1 A 1v )
58
AMPLIFIER FREQUENCY RESPONSE ANALYSIS

Capacitance Multiplication
C1 = CF (1 Av )
C2 = CF (1 A
1
v
) CF
Association of Poles and Nodes
Vout ( s )
A1
A2
1
=
Vin ( s ) 1 + Rs Cin 1 + R1C N 1 + R2C p
Chapter 6
ECE697BB/Oliaei
59
COMMON-SOURCE FREQUENCY RESPONSE

Approximate Analysis (Miller)
f p,in =
1
2RS [CGS + (1+ gm RD )CGD ]
f p,out =
1
2 [(CGD + CDB )RD ]
Exact Analysis
z =
+ gm
CGD
Vo
( sCGD g m ) RD
=
Vi s 2 RS RD (CGS CGD + CGS C SB + CGD C DB ) + s RS (1 + g m RD )CGD + RS CGS + RD (CGD + C DB ) + 1
Chapter 6
ECE697BB/Oliaei
60
SOURCE FOLLOWER OR COMMON DRAIN
vo
gm + sCGS
= 2
vi s RS (CGSCL + CGSCGD + CGD CL ) + s(gm RSCGD + CGD + CGS ) + gm
f p1
gm
, assuming f p2 >> f p1
2 (gm RS CGD + CL + CGS )
=
C + CGS
2 RS CGD + L
gm
ECE697BB/Oliaei
Chapter 6
61
SOURCE FOLLOWER INPUT IMPEDANCE
Z in
g
1
+ 1 + m
sCGS sCGS
g mb + sC L
At low frequencies, gmb >>| sC L |

1
Zin
(1+ gm / gmb ) + 1/ gmb
sCGS
Cin = CGS gmb /(gm + gmb ) + CGD (same as Miller)
At high frequencies, gmb << | sCL |
1
1
g
Zin
+
+ 2 m
sCGS sCL s CGS C L
Chapter 6
ECE697BB/Oliaei
62
SOURCE FOLLOWER OUTPUT IMPEDANCE

ZOUT = VX / IX
=
sRS CGS + 1
gm + sCGS
1/gm , at low frequencies

RS , at high frequencies
R2 = 1 / g m , R1 = RS 1 / g m , L =
CGS
(RS 1 / g m )
gm
Output ringing due to CL and inductive

component of output impedance.
Chapter 6
ECE697BB/Oliaei
63
CASCODE STAGE
f pA =
Chapter 6
gm1
2 RS CGS1 + CGD11+
gm 2 + gmb 2
f pX =
gm 2 + gmb 2
2 (CGD1 + CDB1 + CSB 2 + CGS2 )
f pY =
1
2 RD (CDB 2 + CL + CGD 2 )
ECE697BB/Oliaei
64
DIFFERENTIAL PAIR
f p1
1
2 (roN || roP )CL
f p2 =
fZ = 2 f p 2 =
gmP
2CE
2gmP
2CE
ECE697BB/Oliaei
Chapter 6
65
FEEDBACK PRINCIPLES
Y(s) = H (s)[X(s) G(s)Y (s)]
H (s)
Y(s)
=
X(s) 1+ G(s)H (s)
Gain Desensitization
ACL =
Example
Chapter 8
Y
A
1 A
1
=
=
X 1 + A 1 + A
A
1 + A
1 R1 + R2
=
R2
ACL =
ECE697BB/Oliaei
ACL 1 +
R2
R1
66
FEEDBACK EFFECT ON BANDWIDTH
Acl =
A0
f
1 + j f
p
ACL =
A0
(1 + A0 )1 + j f f (1 + A )
p
0
ECE697BB/Oliaei
Chapter 8
67
FEEDBACK EFFECT ON OUTPUT IMPEDANCE

Output Impedance
IX =
VX VM VX ( A0VX )
=
Rout
Rout
VX
Rout
= Rout,CL =
IX
1+ A0
Input Impedance
VX
= Rin,CL = Rin (1+ A0 )
IX
Chapter 8
ECE697BB/Oliaei
68
AMPLIFIER TYPES
ECE697BB/Oliaei
Chapter 8
69
OP-AMP
Single-Ended Output
+
-
Differential Output
+-+
Ideal Op-Amp
Av
Rin
Rout = 0
Chapter 9
ECE697BB/Oliaei
70
SINGLE-STAGE OP-AMP
OP-AMP as a voltage buffer
ECE697BB/Oliaei
Chapter 9
71
CASCODE OP-AMP: SINGLE-STAGE

Telescopic Cascode
+ Higher Gain
- Reduced Output Swing
- Output swing dependent on input swing
Chapter 9
ECE697BB/Oliaei
72
IMPROVED SINGLE-ENDED CASCODE OP-AMP
Low-Voltage Cascode Current Mirror
Chapter 9
ECE697BB/Oliaei
73
TRIPLE CASCODE
Av app. (gmro)3/2
Severely Limited Output Swing
Complex biasing
Chapter 9
ECE697BB/Oliaei
74
FOLDED-CASCODE AMPLIFIER
PMOS Input
NMOS Input
+ High Gain
+ Output Swing Decoupled from Input Swing
- Reduced Speed
ECE697BB/Oliaei
Chapter 9
75
FOLDED-CASCODE OP-AMP
| Av | g m1 [( g m 3 + g mb3 )ro3 ]ro1

1442443
Cascode Gain
Chapter 9
ECE697BB/Oliaei
76
FOLDED-CASCODE OP-AMP
| Av | gm1 {[(gm 3 + gmb3 )ro3 (ro1 || ro5 )]|| [(gm 7 + gmb 7 )ro7 ro9 ]}
ECE697BB/Oliaei
Chapter 9
77
TELESCOPIC VERSUS FOLDED CASCODE

Non-dominant Pole
Non-dominant Pole
Chapter 9
ECE697BB/Oliaei
78
FOLDED-CASCODE OP-AMP IMPLEMENTATION

Current-Mirror
signal
Current-Mirror
Devices in Signal Path
Current-Mirror
ECE697BB/Oliaei
Chapter 9
79
SINGLE-ENDED TWO-STAGE OP-AMPS

+ Large Voltage Swing
- Reduced Speed
Single-Ended Output Two-Stage Op Amp
Active Current Mirror

Chapter 9
ECE697BB/Oliaei
80
FULLY-DIFFERENTIAL TWO-STAGE OP-AMPS

+ Larger Voltage Swing
+ Better Noise Performance
Ex.2
Ex.1
ECE697BB/Oliaei
Chapter 9
81
OUTPUT IMPEDANCE ENHANCEMENT USING FEEDBACK
Rout = A1gm 2 ro2 ro1
Regulated Cascode
Disadvantage: Low swing or Large Supply Voltage

Chapter 9
ECE697BB/Oliaei
82
DIFFERENTIAL GAIN BOOSTING
Low-Supply
High-Supply
Chapter 9
ECE697BB/Oliaei
83
OP-AMP USING DIFFERENTIAL GAIN BOOSTING
Enhanced Telescopic Cascode
Chapter 9
Enhanced Folded Cascode
ECE697BB/Oliaei
84
COMPARISON
Performance Comparison of OP-AMP Topologies
ECE697BB/Oliaei
Chapter 9
85
COMMON-MODE FEEDBACK
Low-Gain Amplifier
High-Gain Amplifier
+-+
Output common-mode voltage in a low-gain diff-pair is well-defined.

Output common-mode voltage in a low-gain diff-pair is ill-defined.
Chapter 9
ECE697BB/Oliaei
86
COMMON-MODE FEEDBACK PRINCIPLE
Auxiliary amplifier sets the output common-mode.
Vo1 + Vo 2
= Vref = VCM
2
VCM = Vref
ECE697BB/Oliaei
87
COMMON-MODE SENSING METHODS
Resistive
Buffered-Resistive
ECE697BB/Oliaei
88
FOLDED-CASCODE WITH COMMON-MODE CONTROL

(a)
(b)
ECE697BB/Oliaei
89
SIMPLIFIED CMFB
M7 and M8 in Triode.
Advantages:
Simple, low power
Disadvantages:
Low Accuracy
Reduced Output Swing due to M7 and M8
Increased Output Parasitic Capacitance
CMFB with improved output swing:
ECE697BB/Oliaei
90
IMPROVED CMFB
Complete Implementation
Through Symmetry:
Vref = VCM
ECE697BB/Oliaei
91
TRANSIENT LARGE-SIGNAL: SLEWING
Slew rate:
SR =
ECE697BB/Oliaei
dVout (t ) I SS
=
dt
CL
92
SLEWING IN TELESCOPIC OP-AMP
Fully-Differential:
SR =
dVout (t ) 2 I SS
=
dt
CL
ECE697BB/Oliaei
93
FOLDED-CASCODE SLEWING
Fully-Differential:
SR =
ECE697BB/Oliaei
dVout (t ) 2 I SS
=
dt
CL
94

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Analog Integrated Circuits

University of Massachusetts Amherst

Analog Integrated Circuits

Digital signals in a digital communication system behave as analog signals

Signal Attenuation, Noise and Distortion incurred in the propagation

University of Massachusetts Amherst

Analog Integrated Circuits

What is Analog Design?

CAD TOOLS FOR CIRCUIT DESIGN

Cadence and Mentor Graphics Include tools for

University of Massachusetts Amherst

Analog Integrated Circuits

Design Rules Check (DRC)

Analog Design Space

Analog Design is a Multi-Dimensional Optimization Problem.

University of Massachusetts Amherst

Analog Integrated Circuits

Basic MOS Device Physics

MOS is a four-terminal device.

University of Massachusetts Amherst

Analog Integrated Circuits

Complementary MOS Process (CMOS):

MOS CHANNEL FORMATION

University of Massachusetts Amherst

Analog Integrated Circuits

Device turn-on is a gradual phenomenon.

P+ layer increases VTH

PMOS IN INVERSION STATE

PMOS: Holes flow from Source to Drain.

University of Massachusetts Amherst

Analog Integrated Circuits

Larger VDS Larger Longitudinal Field

University of Massachusetts Amherst

Analog Integrated Circuits

I/V Characteristics (cont.)

ID = WCox[VGS VTH V ( x)]v

ID = WCox[VGS VTH V ( x)]n

[VGS VTH V ( x)]dV

I-V CHARACTERISTICS: Triode Region

ID nCox WL (VGS VTH )VDS

VDS < VGS VTH

University of Massachusetts Amherst

Analog Integrated Circuits

I-V CHARACTERISTICS: Saturation Region

VDS > VGS VTH

MOS OPERATION REGIMES

VDS < VGS VTH

VDS = VGS VTH

VDS > VGS VTH

In saturation, MOS behaves as a current source.

University of Massachusetts Amherst

Analog Integrated Circuits

Transconductance in Saturation Region

= n Cox WL (VGS V TH)

DRAIN-SOURCE RESISTANCE IN TRIODE REGION

ID = nCox WL (V GS VTH )VDS, V DS << 2(V GS VTH )

University of Massachusetts Amherst

Analog Integrated Circuits

THRESHOLD VOLTAGE AND BODY EFFECT

VB < 0 attracts holes and widens depletion region

Body effect coefficient

CHANNEL LENGTH MODULATION: SATURATION REGION