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Analog Integrated Circuits

ANALOG INTEGRATED
CIRCUITS DESIGN
University of Massachusetts
Electrical and Computer Engineering Department
Omid Oliaei

Why Analog?
Real-world signals are Analog.
Signals generated by sensors are analog
Digital signal processing of signals requires Analog-to-Digital Conversion.
Analog signal needs to be amplified and filtered before A/D.
Amplifiers and Filters are Analog Circuits.
A/D is a Mixed-Signal Circuit.

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Analog Integrated Circuits

Digital signals in a digital communication system behave as analog signals


at certain stages of transmission, receive and processing.
Ex 1. Lossy Cable

Ex 2. Disc Drive

Ex 3. Wireless Receiver

Ex 3. Optical Receiver

Signal Attenuation, Noise and Distortion incurred in the propagation


channel require that the received signal be Amplified, Filtered and
Equalized using Analog circuits.
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Chapter 1

Why Integrated?
Larger integration  larger complexity
Lower parasitics  Higher speed
Lower cost
Moores Law: Number of transistors doubles every 18 months:
1960: 25 m Gate length
Today: 90 nm and 65 nm in production
45 nm and 32 nm are in lab. 22nm and 16nm on roadmap.
Why CMOS?
Digital (Main Driver)
Low Power, Simplicity, Scaling, Low cost
Analog
Integration with digital
Improved speed over years
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Analog Integrated Circuits

What is Analog Design?


Per
fo

Dont Forget
Variations

rm a

nce

S ch

Analog
Design
s
C on

n
trai

atic
em

Layout
T es
t

ts

Levels of Abstraction
System Level

Circuit Level

Component Level
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Chapter 1

CAD TOOLS FOR CIRCUIT DESIGN


Two Dominant Suppliers:
Cadence
80% market share
Mentor Graphics 20% market share

Simulation:
System Level:
High-Level (Behavioral):
Low-Level (Electrical):

Matlab, SPW
Verilog, Verilog_A, Verilog AMS
SPICE, SPECTRE, ADS, Proprietary Tools

Cadence and Mentor Graphics Include tools for


Schematic Capture
Simulation
Layout

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Analog Integrated Circuits

Customer
Specifications

Design House

Foundry

Schematic Capture
Netlist

Technology
Device Model

Electrical/Behavioral Simulations
Layout: Automatic/Manual

Masks

Design Rules Check (DRC)


Layout Versus Schematic (LVS)

Fabrication

Parasitic Extraction
Production
Chapter 1

Test
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Analog Design Space


Tradeoffs

Cost ?

Analog Design is a Multi-Dimensional Optimization Problem.


Improving one parameter always results in degradation of some others.

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Analog Integrated Circuits

Basic MOS Device Physics


Understanding Device Physics is Essential to Analog Design.
MOS device is symmetric.
Side Diffusion
(Sio2)

Contact
(Metal)

NMOS
Bulk

Leff = Ldrawn 2 LD

Chapter 2

Ldrawn

Tox

0.25 m

5 nm

0.18 m

3.5 nm

0.13 m

2.2 nm

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NMOS

PMOS

MOS is a four-terminal device.


Substrate (bulk) of an NMOS is connected to the lowest potential.
Substrate (bulk) of a PMOS is connected to the highest potential.
All p-n junctions are reverse biased.
Conduction takes place beneath gate, between source and drain.
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Analog Integrated Circuits

Complementary MOS Process (CMOS):


PMOS

NMOS

Chapter 2

PMOS

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MOS CHANNEL FORMATION

Cut Off
VG
GND

VG

Depletion

GND

VG
VTH

Inversion

GND
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Analog Integrated Circuits

Device turn-on is a gradual phenomenon.


There exists several definitions for VTH.
One definition: when VG=VTH :
density of electrons on the interfaced equals density of holes in the substrate
VTH increases with increasing the substrate doping.
Adjusting VTH by ion implantation:

P+ layer increases VTH


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Chapter 2

13

PMOS IN INVERSION STATE

PMOS: Holes flow from Source to Drain.


NMOS: Electrons flow from Source to Drain.
Electrons have a higher Mobility.  NMOS is faster than PMOS (~ 3 times).

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Analog Integrated Circuits

MOS Symbols

Arrow indicates current flow from positive voltage to negative voltage polarity.

Chapter 2

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I-V CHARACTERISTICS

NMOS

Uniform Charge
Distribution

Larger VDS  Larger Longitudinal Field


More Current
Larger VGS  More Charge Carriers
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Analog Integrated Circuits

I/V Characteristics (cont.)

ID = WCox[VGS VTH V ( x)]v


Given v = E and E(x) =

dV (x)
dx

ID = WCox[VGS VTH V ( x)]n


L

dV ( x)
dx

VDS

I dx = WC
D

x =0

[VGS VTH V ( x)]dV

ox n

V =0

1 2
W
ID = nCox L [(VGS V TH)VDS VDS ]
2
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I-V CHARACTERISTICS: Triode Region

Triode Region:

Almost Linear

ID nCox WL (VGS VTH )VDS

VDS < VGS VTH

1
W
2
ID = nCox L [(VGS V TH)VDS VDS ]
2

cm 2 Electrons Mobility

V .s

W
L

[m]
[m]

Cox =

si
tox

[pF / cm ]
2

Oxide Capacitance

Device Width

si = 0.35 [ pF / cm]

Oxide Permittivity

Device Length

tox

Oxide Thickness

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Analog Integrated Circuits

I-V CHARACTERISTICS: Saturation Region

'

DS

= V GS VTH

(Pinch off )

VDS > VGS VTH


ID =

nCox W
2

(VGS VTH ) 2
L
L L

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19

MOS OPERATION REGIMES


Both PMOS and NMOS:
Triode Region

VDS < VGS VTH

Pinch-Off

VDS = VGS VTH

Saturation Region

VDS > VGS VTH

In saturation, MOS behaves as a current source.


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Analog Integrated Circuits

Transconductance in Saturation Region

ID =

gm =

nCox W
2

(VGS VTH ) 2

ID
VGS VDS constant

gm = 2 nCox WL ID

= n Cox WL (VGS V TH)

2ID
VGS V TH

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DRAIN-SOURCE RESISTANCE IN TRIODE REGION

1
W
2
ID = nCox L [(VGS V TH)VDS VDS ]
2

ID = nCox WL (V GS VTH )VDS, V DS << 2(V GS VTH )


RON =

1
VDS
=
W
I DS nCox L (VGS VTH )

Voltage-Controlled Resistance
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Analog Integrated Circuits

THRESHOLD VOLTAGE AND BODY EFFECT

VB < 0 attracts holes and widens depletion region


 Larger VG > 0 to put opposite charge on gate
 Larger VG > 0 to create inversion
 Higher VTH

VTH = VTH 0 +
0. 3 < < 0. 4
F

2F + VSB 2F

Body effect coefficient


Source-Bulk voltage

Fermi level
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23

CHANNEL LENGTH MODULATION: SATURATION REGION

L' = L L
1
1
(1 + L / L) = (1 + VDS )
L
L
nCox W
(VGS VTH ) 2 (1 + VDS )
ID =
2 L
1 / L' =

g DS =

1
I DS
nCox W
=
(VGS VTH ) 2 I DS ,
VDS
2 L
L

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g DS

I DS
L
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Analog Integrated Circuits

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SUBTHRESHOLD CONDUCTION

VGS
ID = I 0 exp
VT

For VGS<VTH, there exists a weak inversion layer causing a small diffusion current.
This leakage current causes increased power dissipation in digital circuits.
To operate in weak inversion, transistor must be wide  low speed.
Application: Ultra Low-Power design.
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Analog Integrated Circuits

MOS LAYOUT
Gate
Contacts (Poly)
(Metal)

Gate

Shared
Gate Contact
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Chapter 2

27

PARASITIC CAPACITANCES

Overlap

Bottom-plate
cap

Side-wall
cap

Junction capacitance increases non-linearly with reverse bias.


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Analog Integrated Circuits

GAT-SOURCE AND GATE DRAIN CAPCITANCES

Qch WCox[VGS VTH V ( x)]


2
Cgs is maximum in the saturation region CGS 3 WLCox

1
Device is symmetric in the triode region CGS = CGD WLCox
2
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Chapter 2

29

LOW-FREQUENCY MOS SMALL-SIGNAL MODEL

VSB = 0
ro =

ID

g mb =

VSB 0
: Drain-source resistance

ID

= gm
VBS
2 2 F + VSB

: Bulk transconductance
saturation

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Analog Integrated Circuits

HIGH-FREQUENCY SMALL-SIGNAL MODEL


Saturation

Triode

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Cut Off

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Analog Integrated Circuits

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GATE ACCESS RESISTANCE


Two fingers

Reduce resistance

Gate resistance effect is significant at RF.


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Analog Integrated Circuits

COMMON-SOURCE with RESISTIVE LOAD

Off
Sat.
Triode

Saturation

Av = gm RD
Deep triode

Chapter 3

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COMMON-SOURCE with RESISTIVE LOAD: Model

Av = gm ro || RD

RD
Av = g m ro

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Analog Integrated Circuits

DIODE-CONNECTED MOS

Vx
= Ix
ro
Vx
1
1
=
|| r o
Ix gm + gmb
gm + gmb
(gm + gmb)V x +

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37

COMMON-SOURCE STAGE with DIODE-CONNECTED LOAD

Av = gm1
Av =

1
gm1 1
=
gm2 + gmb2
gm2 1 +
(W / L)1 1
(W / L)2 1 +

Gain independent of bias current


Good gain accuracy: good matching
PMOS Diode-Connected Load

Av =

un (W / L)1
up (W / L)2

Gain independent of bias current


Gain set by two different types of transistor
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Analog Integrated Circuits

COMMON-SOURCE with CURRENT SOURCE LOAD


Saturation

Large Output Voltage Compared with Resistive Load


All Transistors Need to be in Saturation for High Gain
M1 sets the Minimum Output Voltage
M2 Sets the Maximum Output Voltage

Av = gm ro1 || ro2
High-Resistance Node
Triode

Av = gm RON2
RON 2 =

Chapter 3

nC

W
ox
L 2

(VDD Vb | VTHP |)

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COMMON-SOURCE WITH SOURCE DEGENERATIONS


Gm =

gm
1 + gm RS

Av = Gm RD
Av =

gm RD
1+ gm RS

Including Second-Order Effects

Gm =

gm ro
RS + [1+ (gm + gmb )RS ]ro

Av = Gm RD || ROUT
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Analog Integrated Circuits

COMMON-SOURCE OUTPUT RESISTANCE

ROUT = [1 + (gm + gmb )ro ]RS + ro

ROUT = ro ' ro [1+ (gm + gmb )RS ]


Av = Gm RD || ro '
Simplified Model

Av =

gm RD
RD
=
1+ gm RS
1/ gm + RS

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41

SOURCE FOLLOWER

Small-Signal Model

Av =

gm RS
RS
RS
=

+
g
g
1+ (gm + gmb )RS 1/ g + ( m
mb
)RS 1/ gm + RS
m
gm

Output Resistance

Rout =

1
1
1
||
=
g m g mb g m + g mb

Source Follower Exhibits a high input resistance


and a low output resistance.
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Analog Integrated Circuits

SOURCE FOLLOWER WITH FIXED BIAS CURRENT


Id1, thus, Vgs1- Vth1, are independent of Vin.

Load Effect on Gain

1
|| r || r || RL
gmb o1 o2

Av = 1
1
|| ro1 || ro2 || RL +
gm
gmb
Application: Buffering a High-Gain Stage

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Chapter 3

43

COMMON-GATE

DC coupling

Gain

Av =

AC coupling

Small-Signal Model

( g m + g mb )ro + 1
RD ( g m + g mb ) RD
ro + ( g m + g mb )ro RS + RS + RD

Output Resistance

Rout = {[1 + (gm + gmb )ro ]RS + ro }|| RD


Input Resistance

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Rin = ro ||

1
1
||
gm gmb

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Analog Integrated Circuits

CASCODE AMPLIFIER
AV gm1{[ro1 ro2 (gm 2 + gmb2 )] || RD ]}
Rout = {[1 + ( g m 2 + g mb 2 )ro 2 ]ro1 + ro 2 } || RD
[ro1ro 2 ( g m 2 + g mb 2 )] || RD

Shielding Effect of Cascode

AV gm1 [(ro1ro2 gm2 ) || (ro3ro4 gm3 )]

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45

DIFFERENTIAL VERSUS SINGLE-ENDED

Single-Ended Source

Differential Sources

Advantage: Reduced Sensitivity to Supply Noise

Supply Noise
Clock Noise

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Analog Integrated Circuits

PSEUDO-DIFFERENTIAL AMPLIFIER
Disadvantage: Sensitive to Input Common-Mode Voltage

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Chapter 4

47

DIFFERENTIAL AMPLIFIER

Tail current: Rejects input common mode

4 I SS

V 2

I D nCox W nCoxW / L in
Gm =
=
2 L
Vin
4 I SS
V 2
nCoxW / L in
Vout1 Vout 2
= g m RD
Vin1 Vin 2

Differential-Mode Gain

Adiff =

Common-Mode Gain

Ac = 0

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Analog Integrated Circuits

SMALL-SIGNAL ANALYSIS
Differential-Mode

Ad = g m RD
Virtual ground

Common-Mode

Ac =
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Chapter 4

RD / 2
1 /( 2 g m ) + RSS
49

COMMON-MODE RESPONSE
Load Resistor Mismatch

VX VY
g m RD
=
Vin ,CM
1 + 2 g m RSS

Transistor Mismatch

(g m1 g m 2 )RD
VX VY
=
Vin,CM
( g m1 + g m 2 ) RSS + 1
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Analog Integrated Circuits

DIFF. AMP WITH ACTIVE LOAD

1
Ad = g mN ( g mP
|| roN || roP )

g mN
g mP

Ad = g mN (roN || roP )

Ad g m1[( g m 3 ro 3 ro1 ) || ( g m 5 ro 5 ro 7 )]

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51

CURRENT MIRRORS
Reference Current

I OUT

n Cox W
2

R2
(
VDD VTH ) 2
L R2 + R1

Sensitive to VDD , Vth , W, L

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Analog Integrated Circuits

CURRENT-BIASED DIFFERENTIAL AMPLIFIER

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Chapter 5

53

CASCODE CURRENT MIRROR

Low-Voltage Cascode

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Analog Integrated Circuits

DIFFERENTIAL AMPLIFIER WITH


ACTIVE CURRENT MIRROR

Large-Signal Operation

Chapter 5

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DIFFERENTIAL AMPLIFIER WITH ACTIVE LOAD


Small-Signal Analysis

ID1 = I D3 = ID 4 = gm1,2 Vin / 2

I D2 = gm1,2 Vin / 2

Iout = I D2 I D4 = gm1,2 Vin , Gm = gm1, 2


Rout ro2 || ro4 , (2ro1,2 >> [1/ gm 3 ] || ro3 )
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Av G m Rout

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Analog Integrated Circuits

COMMON-MODE ANALYSIS

VF = Vx
Common-Mode Gain

ACM

g m1, 2
1
1 + 2 g m1, 2 RSS g m 3, 4

Common-Mode Rejection Ratio

CMRR =

ADM
= g m 3, 4 (ro1, 2 || ro 3, 4 )(1 + 2 g m1, 2 RSS )
ACM
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Chapter 5

57

FREQUENCY RESPONSE OF AMPLIFIERS


Single-Pole Passive RC

vi

Vo ( s )
1 / sC
1
1
=
=
=
Vi ( s ) R + 1 / sC 1 + RCS 1 + s / p

s = j

vo

p = 1 / 2RC

: pole frequency

Vo ( )
1
=
Vi ( ) 1 + jRC

Vo ( )
1
=
2
Vi ( )
1 + (RC )

VY
VX

Z2 =

Millers Theorem

Av
Av =
Chapter 6

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Z1 =

Z
(1 Av )

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Z
(1 A 1v )
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Analog Integrated Circuits

AMPLIFIER FREQUENCY RESPONSE ANALYSIS


Capacitance Multiplication

C1 = CF (1 Av )

C2 = CF (1 A

1
v

) CF

Association of Poles and Nodes

Vout ( s )
A1
A2
1
=
Vin ( s ) 1 + Rs Cin 1 + R1C N 1 + R2C p
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COMMON-SOURCE FREQUENCY RESPONSE


Approximate Analysis (Miller)

f p,in =

1
2RS [CGS + (1+ gm RD )CGD ]

f p,out =

1
2 [(CGD + CDB )RD ]

Exact Analysis
z =

+ gm
CGD

Vo
( sCGD g m ) RD
=
Vi s 2 RS RD (CGS CGD + CGS C SB + CGD C DB ) + s RS (1 + g m RD )CGD + RS CGS + RD (CGD + C DB ) + 1

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Analog Integrated Circuits

SOURCE FOLLOWER OR COMMON DRAIN

vo
gm + sCGS
= 2
vi s RS (CGSCL + CGSCGD + CGD CL ) + s(gm RSCGD + CGD + CGS ) + gm
f p1

gm
, assuming f p2 >> f p1
2 (gm RS CGD + CL + CGS )
=

C + CGS

2 RS CGD + L
gm

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61

SOURCE FOLLOWER INPUT IMPEDANCE

Z in

g
1
+ 1 + m
sCGS sCGS

g mb + sC L

At low frequencies, gmb >>| sC L |


1
Zin
(1+ gm / gmb ) + 1/ gmb
sCGS
Cin = CGS gmb /(gm + gmb ) + CGD (same as Miller)
At high frequencies, gmb << | sCL |
1
1
g
Zin
+
+ 2 m
sCGS sCL s CGS C L
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Analog Integrated Circuits

SOURCE FOLLOWER OUTPUT IMPEDANCE


ZOUT = VX / IX
=

sRS CGS + 1
gm + sCGS

1/gm , at low frequencies


RS , at high frequencies

R2 = 1 / g m , R1 = RS 1 / g m , L =

CGS
(RS 1 / g m )
gm

Output ringing due to CL and inductive


component of output impedance.
Chapter 6

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CASCODE STAGE
f pA =

Chapter 6

University of Massachusetts Amherst

gm1

2 RS CGS1 + CGD11+

gm 2 + gmb 2

f pX =

gm 2 + gmb 2
2 (CGD1 + CDB1 + CSB 2 + CGS2 )

f pY =

1
2 RD (CDB 2 + CL + CGD 2 )

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Analog Integrated Circuits

DIFFERENTIAL PAIR

f p1

1
2 (roN || roP )CL

f p2 =

fZ = 2 f p 2 =

gmP
2CE

2gmP
2CE

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Chapter 6

65

FEEDBACK PRINCIPLES
Y(s) = H (s)[X(s) G(s)Y (s)]
H (s)
Y(s)
=
X(s) 1+ G(s)H (s)
Gain Desensitization

ACL =
Example

Chapter 8

University of Massachusetts Amherst

Y
A
1 A
1
=
=

X 1 + A 1 + A

A
1 + A
1 R1 + R2
=

R2

ACL =

ECE697BB/Oliaei

ACL 1 +

R2
R1

66

Analog Integrated Circuits

FEEDBACK EFFECT ON BANDWIDTH

Acl =

A0

f
1 + j f
p

ACL =

A0

(1 + A0 )1 + j f f (1 + A )
p
0

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67

FEEDBACK EFFECT ON OUTPUT IMPEDANCE


Output Impedance

IX =

VX VM VX ( A0VX )
=
Rout
Rout

VX
Rout
= Rout,CL =
IX
1+ A0
Input Impedance

VX
= Rin,CL = Rin (1+ A0 )
IX

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Analog Integrated Circuits

AMPLIFIER TYPES

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Chapter 8

69

OP-AMP
Single-Ended Output
+
-

Differential Output
+-+

Ideal Op-Amp

Av
Rin
Rout = 0

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Analog Integrated Circuits

SINGLE-STAGE OP-AMP

OP-AMP as a voltage buffer

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Chapter 9

71

CASCODE OP-AMP: SINGLE-STAGE


Telescopic Cascode

+ Higher Gain
- Reduced Output Swing
- Output swing dependent on input swing
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Analog Integrated Circuits

IMPROVED SINGLE-ENDED CASCODE OP-AMP

Low-Voltage Cascode Current Mirror

Chapter 9

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TRIPLE CASCODE

Av app. (gmro)3/2
Severely Limited Output Swing
Complex biasing

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Analog Integrated Circuits

FOLDED-CASCODE AMPLIFIER
PMOS Input

NMOS Input

+ High Gain
+ Output Swing Decoupled from Input Swing
- Reduced Speed
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75

FOLDED-CASCODE OP-AMP

| Av | g m1 [( g m 3 + g mb3 )ro3 ]ro1


1442443
Cascode Gain

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Analog Integrated Circuits

FOLDED-CASCODE OP-AMP

| Av | gm1 {[(gm 3 + gmb3 )ro3 (ro1 || ro5 )]|| [(gm 7 + gmb 7 )ro7 ro9 ]}
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77

TELESCOPIC VERSUS FOLDED CASCODE


Non-dominant Pole
Non-dominant Pole

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Analog Integrated Circuits

FOLDED-CASCODE OP-AMP IMPLEMENTATION


Current-Mirror
signal

Current-Mirror
Devices in Signal Path

Current-Mirror

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79

SINGLE-ENDED TWO-STAGE OP-AMPS


+ Large Voltage Swing
- Reduced Speed

Single-Ended Output Two-Stage Op Amp

Active Current Mirror


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Analog Integrated Circuits

FULLY-DIFFERENTIAL TWO-STAGE OP-AMPS


+ Larger Voltage Swing
+ Better Noise Performance

Ex.2

Ex.1

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81

OUTPUT IMPEDANCE ENHANCEMENT USING FEEDBACK

Rout = A1gm 2 ro2 ro1

Regulated Cascode

Disadvantage: Low swing or Large Supply Voltage


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Analog Integrated Circuits

DIFFERENTIAL GAIN BOOSTING

Low-Supply

High-Supply
Chapter 9

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83

OP-AMP USING DIFFERENTIAL GAIN BOOSTING

Enhanced Telescopic Cascode

Chapter 9

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Enhanced Folded Cascode

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Analog Integrated Circuits

COMPARISON

Performance Comparison of OP-AMP Topologies

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Chapter 9

85

COMMON-MODE FEEDBACK
Low-Gain Amplifier

High-Gain Amplifier
+-+

Output common-mode voltage in a low-gain diff-pair is well-defined.


Output common-mode voltage in a low-gain diff-pair is ill-defined.

Chapter 9

University of Massachusetts Amherst

ECE697BB/Oliaei

86

Analog Integrated Circuits

COMMON-MODE FEEDBACK PRINCIPLE

Auxiliary amplifier sets the output common-mode.

Vo1 + Vo 2
= Vref = VCM
2

VCM = Vref

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COMMON-MODE SENSING METHODS

Resistive

Buffered-Resistive

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University of Massachusetts Amherst

88

Analog Integrated Circuits

FOLDED-CASCODE WITH COMMON-MODE CONTROL


(a)

(b)

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89

SIMPLIFIED CMFB
M7 and M8 in Triode.
Advantages:
Simple, low power
Disadvantages:
Low Accuracy
Reduced Output Swing due to M7 and M8
Increased Output Parasitic Capacitance

CMFB with improved output swing:

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University of Massachusetts Amherst

90

Analog Integrated Circuits

IMPROVED CMFB

Complete Implementation

Through Symmetry:

Vref = VCM

ECE697BB/Oliaei

91

TRANSIENT LARGE-SIGNAL: SLEWING

Slew rate:
SR =

ECE697BB/Oliaei

University of Massachusetts Amherst

dVout (t ) I SS
=
dt
CL

92

Analog Integrated Circuits

SLEWING IN TELESCOPIC OP-AMP

Fully-Differential:

SR =

dVout (t ) 2 I SS
=
dt
CL

ECE697BB/Oliaei

93

FOLDED-CASCODE SLEWING

Fully-Differential:

SR =

ECE697BB/Oliaei

University of Massachusetts Amherst

dVout (t ) 2 I SS
=
dt
CL

94