Epri TR1002159

Development of a New Multilevel
Converter-Based Intelligent Universal

Transformer: Design Analysis
SED
R I
A L
LICE
M AT E
WARNING:
Please read the License Agreement
on the back cover before removing
the Wrapping Material.
Effective December 6, 2006, this report has been made publicly available in
accordance with Section 734.3(b)(3) and published in accordance with
Section 734.7 of the U.S. Export Administration Regulations. As a result of
this publication, this report is subject to only copyright protection and does
not require any license agreement from EPRI. This notice supersedes the
export control restrictions and any proprietary licensed material notices
embedded in the document prior to publication.
Technical Report
Development of a New Multilevel

Converter-Based Intelligent
Universal Transformer:
Design Analysis
1002159
Final Report, March 2004
EPRI Project Manager

F. Goodman
EPRI 3412 Hillview Avenue, Palo Alto, California 94304 PO Box 10412, Palo Alto, California 94303 USA
800.313.3774 650.855.2121 askepri@epri.com www.epri.com
DISCLAIMER OF WARRANTIES AND LIMITATION OF LIABILITIES

THIS DOCUMENT WAS PREPARED BY THE ORGANIZATION(S) NAMED BELOW AS AN
ACCOUNT OF WORK SPONSORED OR COSPONSORED BY THE ELECTRIC POWER RESEARCH
INSTITUTE, INC. (EPRI). NEITHER EPRI, ANY MEMBER OF EPRI, ANY COSPONSOR, THE
ORGANIZATION(S) BELOW, NOR ANY PERSON ACTING ON BEHALF OF ANY OF THEM:
(A) MAKES ANY WARRANTY OR REPRESENTATION WHATSOEVER, EXPRESS OR IMPLIED, (I)
WITH RESPECT TO THE USE OF ANY INFORMATION, APPARATUS, METHOD, PROCESS, OR
SIMILAR ITEM DISCLOSED IN THIS DOCUMENT, INCLUDING MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE, OR (II) THAT SUCH USE DOES NOT INFRINGE ON OR
INTERFERE WITH PRIVATELY OWNED RIGHTS, INCLUDING ANY PARTY'S INTELLECTUAL
PROPERTY, OR (III) THAT THIS DOCUMENT IS SUITABLE TO ANY PARTICULAR USER'S
CIRCUMSTANCE; OR
(B) ASSUMES RESPONSIBILITY FOR ANY DAMAGES OR OTHER LIABILITY WHATSOEVER
(INCLUDING ANY CONSEQUENTIAL DAMAGES, EVEN IF EPRI OR ANY EPRI REPRESENTATIVE
HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES) RESULTING FROM YOUR
SELECTION OR USE OF THIS DOCUMENT OR ANY INFORMATION, APPARATUS, METHOD,
PROCESS, OR SIMILAR ITEM DISCLOSED IN THIS DOCUMENT.
ORGANIZATION THAT PREPARED THIS DOCUMENT
EPRI PEAC Corporation
Enertronics, Inc
ORDERING INFORMATION
Requests for copies of this report should be directed to EPRI Orders and Conferences, 1355 Willow
Way, Suite 278, Concord, CA 94520, (800) 313-3774, press 2 or internally x5379, (925) 609-9169,
(925) 609-1310 (fax).
Electric Power Research Institute and EPRI are registered service marks of the Electric Power
Research Institute, Inc. EPRI. ELECTRIFY THE WORLD is a service mark of the Electric Power
Research Institute, Inc.
Copyright 2004 Electric Power Research Institute, Inc. All rights reserved.
CITATIONS
This report was prepared by
EPRI PEAC Corporation
942 Corridor Park Blvd.
Knoxville, TN 37932
Principal Investigators
A. Maitra
A. Mansoor
B. Vairamohan
Enertronics, Inc
2204 Hardwick Street
Blacksburg, VA 24060
Principal Investigator
J. Lai
This report describes research sponsored by EPRI.
The report is a corporate document that should be cited in the literature in the following manner:
Development of a New Multilevel Converter-Based Intelligent Universal Transformer: Design
Analysis, EPRI, Palo Alto, CA: 2004. 1002159.
iii
REPORT SUMMARY
This report provides a comprehensive design analysis of a high-voltage multilevel converterbased intelligent universal transformer (IUT). The proposed IUT design includes back-to-back,
interconnected, multi-level converters coupled to a switched inverter circuit via a high-frequency
transformer. The input of the universal transformer can be coupled to a high-voltage distribution
system such as 4.16-kV with the use of existing high-voltage silicon insulated-gate-bipolar
transistor (IGBT) devices, and the output of the universal transformer can be coupled to lowvoltage applications such as 240/120 V.
Background
A significant opportunity exists to replace conventional transformers with a more sophisticated
multi-functional device, the intelligent universal transformer. This approach would radically alter
the way electric utilities serve their respective customers and expand the capabilities of a
distribution transformer from primarily a voltage-transformation device to an integrated
electrical customer interface. The IUT could broaden traditional service offerings, provide key
operational benefits, satisfy a myriad of customer requirements for power quality, and at the
same time provide functionalities for advanced distribution automation.
Objectives
To provide a comprehensive design analysis to verify the functionality of a high-voltage
multilevel converter-based IUT design that uses high voltage power electronics
To estimate the efficiency, cost, and reliability of the proposed design
To refine the long-term roadmap for the development of the universal transformer with better
cost estimates and schedule for development work in 20042007.
Approach
The design analysis work presented in this report is a part of a multi-year effort to develop a
high-voltage, multilevel converter-based IUT based on an all-solid-state approach. The project
team built on the work done in 2002 to assess the feasibility of replacing current distribution
transformers with the IUT. The team selected circuit topology and active and passive
components for the power stage and used simulations to evaluate the ability of the power stage
design to provide the desired functionalities. The team estimated the cost of the proposed system
based on existing component costs and estimated component cost for different degrees of market
penetration and estimated system reliability using industry standard reliability methods. They
developed cost estimates and a schedule for development work in 20042007 and identified the
key functionalities and criteria that an IUT must meet to gain market acceptance.
Results
While there are inherent risks in the development of the IUT, its potential is enormous. As
compared to the conventional copper-and-iron based transformer, the high-voltage multilevel
solid-state transformer will reduce transformer size and eliminate oil, aid in implementing
standardized transformer designs, enhance power quality, and increase functionality. Enhanced
functionality and flexibility easily justify its greater cost. The IUTs power electronics can be
designed with modularity and expandability; and, since the cost of power semiconductor and
associated controls has exponentially decreased over the past few decades, the IUTs economics
can be expected to improve with time and maturation.
The thorough design and performance analysis of the IUT design provided in this report shows
which of the functional specifications can be achieved and what will be the tradeoffs in cost,
efficiency, and reliability to achieve additional functionalities. The report details the power
electronics circuits and associated open-loop and closed-loop controller designs that are
required in an IUT to enhance transformer functionality. The report presents the IUT power stage
design in detail, an AutoCAD drawing, specifications based on a designated KVA and
input/output voltage range, an IUT reliability assessment, modeling and simulation results for
IUT functionality verification, and performance verification of both power stage and controller
designs.
The report provides a detailed functional specification, written in a technology-neutral manner so
as to provide designers with maximum flexibility in achieving desired functionalities. At a
minimum, the functionality of the proposed design should meet the basic functionality of a
conventional distribution transformer in terms of its capability for voltage transformation and
provide operational benefits in terms of standardization of distribution transformers with respect
to input/output voltage and kVA rating. This report describes in detail the possible phases for
design and development of the proposed IUT technology along with schedules, important
milestones, and budgets estimates for development work in 20042007. The economic viability
of the IUT is also evaluated in this report.
EPRI Perspective
Pressures are increasing on distribution system operators to provide a higher-quality and more
reliable product on demand when customers need it and at an acceptable price point. To respond
to these needs, EPRI has a body of work under way to advance distribution automation. The IUT
is a cornerstone device of advanced distribution automation. By integrating a smart device into
the transformer, the main delivery point for most customers, a distribution utility can broaden its
traditional service offerings, realize key operational benefits, and satisfy a myriad of customer
requirements for improved power quality.
Keywords
Distribution transformer
Intelligent universal transformer
Power quality
Power electronics
High voltage multi-level converter
Solid-state designs
Semiconductor devices
vi
EPRI Licensed Material
EXECUTIVE SUMMARY
Project Overview
This report describes the findings of the research performed to assess the requirements for a
high-voltage multilevel converter-based intelligent universal transformer (IUT). A high-voltage
multilevel converter-based IUT was proposed for the next-generation distribution transformer
(see Figure 1).
6.6kV
8 kVrms
11.3 kVpk
Lf i
a
Sa1
Sb1
Low-voltage IGBT based inverter
Sc1
C1
Sa2
Lo
Sb2
Sc2
Lac
vin
Sa3
Sb3
Sa4
Sb4
Co
Cac
Sc3
C2
Sc4
6.6kV
A 3-Level Scheme
6.6 kV
Sr11
Sr21
Si1
Sr12
Sr22
Si2
Sr13
Sr23
Si3
Lf Sr14
Sr24
Si4
120V
400 Hz
8 kV
16.6 kVA
120/240 V
60 Hz
Sr11
Sr21
Si1
Sr12
Sr22
Si2
Sr13
Sr23
Si3
Sr14
Sr24
1r
5
3
Si4
-6.6 kV
Isolated
DC/DC
converter
+
48 Vdc
_
1i
A 5-Level Scheme
Figure 1
Proposed Multi-Converter-Based Intelligent Universal System
vii
The design analysis work presented in this report is a part of a multi-year effort to develop the
IUT based on the all-solid-state approaches. It builds on the work done in 2002 to assess the
feasibility of replacing current distribution transformers with a more sophisticated device, the
IUT. The scope of last years activity was to assess the requirements for a next-generation
universal transformer, identify the application areas, and evaluate the economic and technical
considerations for different technologies and design options for a universal transformer. Also, it
was identified that use of high-voltage (HV) power electronics in designing the primary side of
an all-solid-state transformer offers significant advantage in reliability and cost over low-voltage
(LV) designs.
As compared to the conventional copper-and-iron based transformer, the HV multilevel solidstate transformer will not only reduce transformer size and eliminate oil but also will enhance the
power quality performance and increase the functionality. Conceptually, the following functions
that do not exist in the conventional transformer can be obtained with the proposed IUT circuit:
Identifying Opportunities to Add Value Using All-Solid-State Transformer

Designs
While the risk involved in an all-solid-state approach could be much higher, the potentials are
also enormous. Motivations for possible market transformation using all-solid-state transformer
designs include:
Ability to Provide a Wide Range of Services
The new approaches based on innovative, multi-functional, and modular transformer designs can
be used to expand the capabilities of a conventional distribution transformer from primarily a
voltage-transformation device to an integrated electrical customer interface that has the
capability to meet the customers requirement and is therefore a viable market opportunity. This
pioneering approach has tremendous market advantages for the industry in that utilities can
provide not only the traditional ac service and cater to power quality and reliability needs for
specific customers, but also can create new service opportunities by providing whatever service
the customer desires (dc power, high-frequency ac power, sag protection, harmonic filtering,
ability to convert single-phase service to three-phase for powering certain types of equipment,
and so on).
1. Opportunity to provide new service opportunities The development of a universal
transformer will provide an opportunity to offer dc service, high-frequency ac service, ability
to convert single-phase service to three-phase for powering certain types of equipment, and
premium power services with enhanced power quality and reliability tailored to individual
customer requirement. Opportunities for premium-quality service will be mainly targeted
towards industrial and high-end commercial customers. Options for dc requirement currently
exist primarily in the Internet and telecommunication sector, with potential widespread
application of dc because of the proliferation of digital loads.
2. Opportunity to meet customers power quality and reliability requirements A universal
transformer is proposed to use modern power electronics technology to serve as the energy
buffer in between the source and load to avoid direct impact from either load-to-source or
viii
source-to-load. In addition, with the flexibility of power electronics switching, it also has the
potential to meet enhanced power quality and reliability tailored to individual customer
requirement such as voltage sag compensation, instantaneous voltage regulation, harmonic
compensation, outage compensation, capacitor switching protection, single-phase protection,
and options for energy storage.
Ability to Provide Improved Operational Benefits
Utilities need to make long-term capital investments in all-solid-state-based transformer
technologies that will completely change distribution transformer design to achieve additional
operational benefits such as:
1. Opportunity to implement standardized transformer design There are fixed and variable
costs in maintaining an inventory of distribution transformers. One of the primary functional
specifications for the universal transformer is standardization of product classes compared to
the existing practice based on multiple kVA size, primary voltage, and secondary voltage.
Realization of this primary functional specification through the development of a solid-state
distribution transformer should result in significant reduction in inventory cost. It is possible
to significantly reduce inventory costs by introducing standardized transformer designs.
2. Opportunity to considerably reduce the size and weight of magnetic components As
compared to the conventional copper-and-iron-based transformer, the disclosed, multi-level,
solid-state transformer contains only high-frequency AC components. The resulting core size
is small as compared to that which is designed for 60-Hz operations.
3. Opportunity to dramatically reduce environmental concerns by introducing designs that do
not use mineral oil or other liquid dielectrics Handling and disposal of transformer oil is
definitely costly to utilities. Moreover, leak and spill cleanup (in terms of cost) is another
additional large-ticket item. The universal transformer design will eliminate the need for oil,
which is one of primary environmental issues related to oil-immersed transformer design.
The use of oil-free universal transformers will portray a positive image in the community and
also significantly reduce environmental risk and regulatory exposure.
4. Opportunity to provide reactive support The universal transformer designs will have the
ability to dynamically compensate for reactive power requirements of the load in order to
minimize the effect of flicker from rapidly fluctuating loads such as arc furnaces, rolling
mills, and so forth. In addition, the design should have the capability to correct power factor
when applied in the power-factor-correction mode.
5. Opportunity to provide other advanced distribution automation functions and thereby reduce
operations and maintenance costs The operations-and-maintenance (O&M) cost reduction
are potentially achievable with a universal transformer through improved communication
capabilities by adopting the UCATM communication architecture for the universal
transformer. Advanced distribution automation provides opportunities to develop new
applications for condition monitoring and asset management purposes. One potential area is
monitoring of distribution transformers in order to minimize unnecessary maintenance and
replacements and thus enhance network operation efficiency. The intelligent universal
transformer could have the ability to act as a sensor of voltage, current, and power factor; an
ix
aid in real-time voltage regulation; and a provider of advanced distribution automation

functions. Approximately 13% of the total distribution resource usage is for feeder and line
maintenance (see [12]). Assuming a 2% reduction in the total O&M cost, universal
transformer technology can potentially save $1.3 million for a utility with total annual
distribution cost of $500 million.
However, all new products face barriers to entry, particularly when competing with
entrenched, mature technologies. The disadvantages of the IUT technology include:
Need suitable high-voltage, low-power IGBT or alternate device to be competitive with

conventional transformers cost
LV-IGBTs are mature products. Using LV-IGBTs, a significant reduction in price as a result
of mass product would not be possible.
Will need five to 10 years for product development and field application.
Lower efficiency than the conventional transformer.
Need more device and components for design. Risky in terms of reliability.
Requires power electronics on the high-voltage side.
Higher EMI than conventional transformer.
Lack of customer acceptance and willingness to try new untested technologies
Project Objectives
It is quite clear that, even with the higher risk involved in all-solid-state designs, the preferred
research path should aim for the quantum leap in distribution transformer technology that is
possible with the all-solid-state approach rather than an incremental improvement achieved
through combination of existing technologies. The overall objective of this years activity was to
leverage previous years research and provide a comprehensive design analysis to verify the
functionality that can be achieved with the conceptual high-voltage multilevel converter-based
IUT design and estimation of efficiency, cost, and reliability of such a proposed design.
Conceptually, the solid-state power-conversion-based distribution transformer will be much
more expensive than the conventional one. However, the electronics can be designed with
modularity and expandability. When considering the enhanced functionality and the flexibility,
the added cost can be easily justified. In fact, the cost of power semiconductor and associated
controls has exponentially decreased over the past few decades. Whether or not the IUT can be
economically viable is also evaluated in this report.
This preliminary research is the first step before embarking on the development of the hardware
and associated controls for a prototype universal transformer. This is the most critical stage
because the commitment to a certain design topology will ultimately lead to hardware and
controller development and lab prototype. Critical issues that are addressed in this report,
include:
Selection of the circuit topology for the power stage
Selection of active devices and passive components and calculation for semiconductor device
voltage and current ratings and inductor and capacitor values based on certain assumptions or
requirements on ripple, ride-through, or control response
Simulation of the performance of the power stage using industry-accepted design packages
for power electronics design analysis
Verification of basic functions, such as voltage balancing for a multiple-level stack, with
hardware experiments
Estimation of the cost of the proposed system based on existing component costs and
estimated component cost for different degrees of market penetration
Estimation of the system reliability using industry standard reliability calculation methods
such as MIL-HDBK-217F Reliability Prediction of Electronic Equipment
Determination of design packaging and thermal management systems
Evaluation of the design with respect to its ability to meet the different desired functionalities
Development of a more refined EPRI long-term roadmap (see Figure 2 through Figure
5) for the development of the intelligent universal transformer with better cost estimates
and schedule for the development work in 20042007
Identification of the key functionalities and criteria that need to be met in order for this
technology to gain market acceptance
xi
Figure 2
Projections of Possible Phases and Individual Tasks for Design and Development (2004
2007) of the Proposed HV Multi-Level-Converter-Based IUT Design
xii
BENCH MODEL
Development Schedule
FIELD PROTOTYPE
FIELD Deployment Schedule
10/06 - 05/07
13.8kV, 5 IUT Beta Models
Field Prototype
- Completed
05/07 - 11/07
IUT Field Installation &
Commissioning
Field Data Collection
- Start
1/06 - 12/ 06
13.8kV IUT Alpha Model
Field Prototype
- Completed
4/04 - 6/05
4.16kV IUT Bench Model
- Completed
1/04 - 4/ 04
Initiate forum to select
potential vendors
1/06
13.8kV IUT
Field Prototype
- Start
Jan 2005
11/07 - 08/08
IUT Field Data Collection
& Analysis
1/07 - 05/07
Site Selection & Investigation
Field Demonstration
- Start
Jan 2006
Jan 2007
Jan 2008
Jan 2004
Sep 2008
Figure 3
EPRIs Long-Term Roadmap for the Proposed HV Intelligent Universal Transformer
Development Schedules and Important Milestones
Total Cost of Design

Cost estimate for the 3-level 4.16-kV IUT
Cost estimate for the 5-level 15-kV IUT
Total
$7,084
$4,614
Heat sink and packing

Auxiliary power supply
DSPs
HF transformer
400-Hz inverter + 48 V dc/dc converter
60-Hz inverter
Sensor conditioning
Gate drive interface
HV-gate drive
$7,500
$7,000
$6,500
$6,000
$5,500
$5,000
$4,500
$4,000
$3,500
$3,000
$2,500
$2,000
$1,500
$1,000
$500
$0
3-level power circuit
(Cost Estimates)
Figure 4
Overall Cost Estimate in the 3-Level 4.16kV and 5-Level 15kV IUT
xiii
Figure 5
Detailed Budget Estimate for Development Work in 20042007
xiv
ACKNOWLEDGMENTS
The authors wish to acknowledge the support of Dr. Siriroj Sirisukprasert of Virginia Tech for
his contributions and assistance throughout this project. In particular, we would like to thank Dr.
Allen R. Hefner and Dr. Ranbir Singh of National Institute of Standards and Technology (NIST)
for their insightful thoughts and comments on the development of high-voltage semiconductor
devices.
xv
CONTENTS
1 INTRODUCTION ....................................................................................................................1-1
Project Scope ........................................................................................................................1-1
The Good Old Distribution Transformer..............................................................................1-3
Why Look at Anything Else? .................................................................................................1-5
Can the Opportunity to Offer a Wide Range of Services Be Realized Through
Incremental Improvements in Conventional Transformers?..................................................1-8
Short-Range Market Driver Improved Power Quality and Reliability .............................1-9
Short-Range Market Driver Powering Three-Phase Loads From a Single-Phase
Service............................................................................................................................1-12
Woodworking Workshops ..........................................................................................1-12
Metalworking Workshops...........................................................................................1-12
Vehicle Servicing .......................................................................................................1-12
Farming......................................................................................................................1-12
Mid-Range Market Driver DC Distribution ...................................................................1-12
Long-Range Market Driver High-Frequency AC Power ..............................................1-14
Expanding Traditional Service Offering Through a Sophisticated Device ......................1-14
Can the Opportunity to Offer Improved Operational Benefits Be Realized Through
Incremental Improvements in Conventional Transformers?................................................1-16
Operational Benefits Reduced Inventory Through Standardization ............................1-17
Operational Benefits Advanced Distribution Automation.............................................1-19
Operational Benefits Environmental ............................................................................1-20
Operational Benefits Reactive Compensation.............................................................1-20
Emerging Power Electronic-Based Transformer Designs ...................................................1-20
Window of Opportunity for All-Solid-State Transformer Designs Using HV, LowCurrent Power Electronic Switches ................................................................................1-24
Organization of the Report ..................................................................................................1-25
xvii
2 DESIGN OF THE POWER STAGE ........................................................................................2-1

2.1 Basic Principle of Diode-Clamp Multilevel Converter ......................................................2-1
2.2 Design Calculation for the Front-End AC/DC Multilevel Converter .................................2-5
A. Selection of DC Bus Capacitor Voltage Level..............................................................2-6
B. Size of DC Bus Capacitor ............................................................................................2-7
C. Size of Boost Inductor..................................................................................................2-7
2.3 Design Calculation for the DC/DC Multilevel Half-Bridge Converter ...............................2-8
A. Transformer Design .....................................................................................................2-8
B. Output Filter Capacitor Design.....................................................................................2-9
C. Output Filter Inductor Design .....................................................................................2-10
2.3 Design Calculation for the DC/AC Inverter Output Filters .............................................2-12
A. Determine Inverter Output Filter Inductor...................................................................2-16
B. Determine Inverter Output Filter Capacitor ................................................................2-17
2.4 Design Calculation for the 400-Hz Inverter Output Filters.............................................2-17
A. Determine Inverter Output Filter Inductor...................................................................2-17
B. Determine Inverter Output Filter Capacitor ................................................................2-18
2.5 Power Stage Design for Three-Level 4.16-kV System Active Front-End Converter .....2-19
A. Selection of the DC Bus Capacitor Voltage Level......................................................2-19
B. Size of DC Bus Capacitor ..........................................................................................2-19
C. Size of Boost Inductor................................................................................................2-20
2.6 Physical Layout of the IUT ............................................................................................2-20
A. Power Stage Layout...................................................................................................2-20
B HV-IGBT Gate Drive and Interface Layout..................................................................2-21
C. Physical Layout of the Complete IUT System............................................................2-22
3 MODELING AND SIMULATION FOR PERFORMANCE VERIFICATION ............................3-1
Active Front-End Control Design...........................................................................................3-1
A. Open-Loop Transfer Functions of AFE ........................................................................3-2
B. Feedback Control Design for AFE ...............................................................................3-4
C. Current Loop Compensator Design .............................................................................3-4
D. Voltage Loop Compensator Designs ...........................................................................3-7
E. PWM Generator and DC Link Voltage Balancing Techniques ...................................3-10
F. Simulation Results for the Three-Level Active Front End Converter ..........................3-14
3.2 Modeling and Simulation of the 60-Hz DC/AC Inverter .................................................3-15
xviii
A. Behavior Circuit Modeling ..........................................................................................3-16

B. Inverter Controller Design With a Simple Voltage Loop.............................................3-17
C. Inverter Control Design With Feed-Forward Voltage Loop ........................................3-18
3.3 Performance Verification for the Entire IUT System......................................................3-20
A. Voltage-Sag Compensation .......................................................................................3-21
B. Outage Compensation ...............................................................................................3-25
C. Instantaneous Voltage Regulation Under Load Transients .......................................3-27
D. Effects of Unbalanced Load, Overload, and Lagging Power Factor ..........................3-28
E. Effects of Nonlinear Loads .........................................................................................3-30
F. Performance Verification for the 400-Hz Inverter .......................................................3-32
3.4 Modularization for Three-Phase IUT Design .................................................................3-33
4 RELIABILITY ASSESSMENT OF THE PROPOSED IUT SYSTEM ......................................4-1
Background of Reliability Assessment ..................................................................................4-1
Quantifying Reliability............................................................................................................4-2
Various Reliability Standards ................................................................................................4-5
MIL 217.............................................................................................................................4-5
Bellcore.............................................................................................................................4-5
NSWC (Naval Surface Warfare Center) ...........................................................................4-5
RDF 2000 .........................................................................................................................4-5
PRISM ..............................................................................................................................4-5
Comparison of Different Standards .......................................................................................4-6
Reasons for Choosing MIL 217.............................................................................................4-7
Demerits of MIL 217 ..............................................................................................................4-8
Application of MIL 217 in Various Stages of IUT...................................................................4-8
Design Stage ....................................................................................................................4-8
Lab Prototype Stage.........................................................................................................4-9
Final Production Stage .....................................................................................................4-9
MIL 217 Analysis Methods ....................................................................................................4-9
Parts Count Analysis ........................................................................................................4-9
Part Stress Analysis .......................................................................................................4-10
Reliability Analysis of the Proposed IUT Design Using Item Toolkit ...................................4-11
An Introduction to Item Toolkit........................................................................................4-13
Parameter Values Used in the Reliability Analysis.........................................................4-18
Results of Reliability Analysis..............................................................................................4-21
xix
ABB Power Electronics-Based Distributed Transformer .....................................................4-23

Comparison of Results of Both Designs..............................................................................4-26
5 CIRCUIT DESIGN AND OVERALL COST ESTIMATION......................................................5-1
Active-Front-End Power Circuit .............................................................................................5-2
HV Gate Drive Circuit ............................................................................................................5-3
Gate Drive Interface ..............................................................................................................5-5
Sensor Conditioning Circuit...................................................................................................5-6
Inverter Circuit .......................................................................................................................5-7
Cost Estimate for the 400-Hz Inverter and DC/DC Converter.............................................5-10
Cost Estimate for the Entire IUT..........................................................................................5-10
6 UNIVERSAL TRANSFORMER ROADMAP PLANNING .......................................................6-1
Opening New Frontiers for Next-Generation Transformers ..................................................6-1
Overall Roadmap Technology Characteristics How to Realize the Vision in the
Future ....................................................................................................................................6-6
Following the General Trends to Support the Vision Direction.........................................6-6
Long-Term Research Timeline for Any All-Solid-State Design ......................................6-8
Long-Term Research Timeline for any HV Multi-Converter-Based Intelligent Universal
Transformer Design...............................................................................................................6-9
Solid-State Designs Using HV Power Electronic Switches and Diodes A Key for
Success ..........................................................................................................................6-10
The Unique Requirement of High-Voltage Low-Current Power Electronics for
Distribution Transformer Application ..............................................................................6-13
Silicon-Based HV-Insulated Gate Bipolar Transistors (IGBTs)..................................6-15
Basic Structure......................................................................................................6-15
High-Voltage Insulated Gate Bipolar Transistors ..................................................6-16
Cost Projection for Commercially Available Silicon-Based Insulated Gate
Bipolar Transistor ..................................................................................................6-17
Moving Beyond HV IGBT Why Wide-Band-Gap Semiconductor Materials and
Why Not .....................................................................................................................6-20
What are Wide Band Gap Materials?....................................................................6-20
Band Gap and Operating Temperature.................................................................6-22
Power Device Figure of Merit................................................................................6-22
SiC Device Figure of Merit ....................................................................................6-23
Cost Projection for SiC Devices.................................................................................6-25
IUT Development with Wide-Band Gap Material ..................................................6-26
xx
Critical Technology Areas...............................................................................................6-27

EPRIs Long-Term Roadmap for the Proposed HV Multilevel Converter-Based
Intelligent Universal Transformer ........................................................................................6-28
Phase I: Intelligent Universal Transformer Prototype Development, Testing, and
Functionality Verification.................................................................................................6-31
Major Deliverables for the Phase I.............................................................................6-37
Phase II: Intelligent Universal Transformer Field Prototype Development, Testing,
and Functionality Verification..........................................................................................6-38
Phase III: Intelligent Universal Transformer Field Deployment, Field Unit Data
Collection, and Functionality Verification........................................................................6-40
Phase IV: Intelligent Universal Transformer Technology Commercialization (20082010) ..............................................................................................................................6-42
Development of Comprehensive Functional Specifications for the Proposed HV
Multilevel Converter-Based Intelligent Universal Transformer ............................................6-42
Design Guideline for Proposed IUT Based on Conventional Dry-Type Distribution
Transformer Standards...................................................................................................6-42
Usual Service Condition.............................................................................................6-43
Overload Requirement for IUT...................................................................................6-43
Generic Specification......................................................................................................6-44
Standardization ..........................................................................................................6-44
Power Quality and Reliability .....................................................................................6-44
Reactive Compensation.............................................................................................6-45
Communications ........................................................................................................6-45
Efficiency ...................................................................................................................6-45
Reliability ...................................................................................................................6-45
Environment...............................................................................................................6-46
Cost ...........................................................................................................................6-46
Technical Specifications .................................................................................................6-46
Voltage and Current Waveforms Under Transient Conditions...................................6-49
A. Load Step .........................................................................................................6-49
B. Voltage Sag ......................................................................................................6-50
C. Outage..............................................................................................................6-51
D. Nonlinear Load .................................................................................................6-52
7 REFERENCES .......................................................................................................................7-1
xxi
LIST OF FIGURES
Figure 1-1 Distribution Transformer ...........................................................................................1-4
Figure 1-2 Efficiency Trends Over Several Years for 75-kVA, Three-Phase Distribution
Transformers......................................................................................................................1-6
Figure 1-3 Options for Power Quality Mitigation at Different Levels ........................................1-10
Figure 1-4 Cost of Power Quality Solution Versus Knowledge of Equipment Sensitivity.........1-11
Figure 1-5 Typical Powering Configuration for Telecommunication Equipment ......................1-13
Figure 1-6 Standard Delivery for Various Requirements Today ..............................................1-15
Figure 1-7 New Expanded Service Opportunity.......................................................................1-16
Figure 1-8 Importance of Standardization................................................................................1-17
Figure 1-9 Variations in Distribution Resource Usage .............................................................1-18
Figure 1-10 Realizing the High-Frequency AC Link Stage in a Design ...................................1-20
Figure 1-11 Simplified Schematic for Power Electronics-Based Transformer Design .............1-22
Figure 1-12 Closing the Device Design Loop A Key for Building Optimal ApplicationSpecific Power Devices....................................................................................................1-25
Figure 2-1 Multilevel Diode-Clamped Converters: (a) Three-Level and (b) Five-Level..............2-2
Figure 2-2 Complete Circuit Diagram of a Three-Level IUT.......................................................2-3
Figure 2-3 Half-Bridge-Based Three-Level IUT .........................................................................2-4
Figure 2-4 Combination With Full-bridge 3/5-Level Converter and Half-Bridge 3/5-Level
Inverter That Allows the Use of Semiconductor Devices With a Lower Voltage
Blocking Level ....................................................................................................................2-5
Figure 2-5 Simulated DC Bus Capacitor Voltage and Boost Inductor Current in Three
Line Cycles.........................................................................................................................2-8
Figure 2-6 Zoomed-in Simulated Line Current to Show the Inductor Ripple Content ................2-8
Figure 2-7 Physical Size of the Transformer Cores ...................................................................2-9
Figure 2-8 Rectifier Output Inductor Current Ripple ................................................................2-10
Figure 2-9 Simulation Diagram of the Three-Level DC/DC Converter .....................................2-10
Figure 2-10 Switch Control Signals for the Three-Level DC/DC Converter .............................2-11
Figure 2-11 Transformer Primary Voltage and Secondary Output Voltage Before and
After the Filter Inductor.....................................................................................................2-11
Figure 2-12 Output Filter Capacitor Voltage and Inductor Current Waveforms .......................2-12
Figure 2-13 The DC/AC Inverter With Split Outputs ................................................................2-12
Figure 2-14 Sinusoidal PWM Method ......................................................................................2-13
Figure 2-15 Inverter Output Voltage Before and After Filtering ...............................................2-13
xxiii
Figure 2-16 Harmonic Contents of the Inverter Output Voltage Before Filtering .....................2-14
Figure 2-17 Dual Modulation Method With Two Sets of Duty Cycles da and db .......................2-14
Figure 2-18 Inverter Output Voltage With Dual Modulation Method ........................................2-15
Figure 2-19 Harmonic Contents of the Dual Modulated Inverter Output Voltage Before
Filtering ............................................................................................................................2-15
Figure 2-20 Simulated Inductor Current and Resistive Load Current ......................................2-16
Figure 2-21 Inverter Output Voltage Waveforms After Filtering ...............................................2-17
Figure 2-22 Simulated Inductor Current and Resistive Load Current ......................................2-18
Figure 2-23 Inverter Output Voltage Waveforms After Filtering ...............................................2-18
Figure 2-24 Verification of Capacitor Ripple Voltage ...............................................................2-19
Figure 2-25 Verification of Inductor Current Ripple..................................................................2-20
Figure 2-26 Three-Dimensional View of the Five-Level Half-Bridge Converter Power
Stage................................................................................................................................2-21
Figure 2-27 Gate Drive Interface Board...................................................................................2-22
Figure 2-28 Physical Layout of the Complete Five-Level Half-Bridge Converter.....................2-23
Figure 3-1 Schematic of the Active Front End of IUT ................................................................3-1
Figure 3-2 Closed-Loop Control Block Diagram for AFE ...........................................................3-4
Figure 3-3 Bode Plot of the Open-Loop Transfer Function........................................................3-5
Figure 3-4 Phase Plot of the Open-Loop Control-to-Current Transfer Function
Associated With Digital Delay ............................................................................................3-6
Figure 3-5 Bode Plots of Current Loop Gain..............................................................................3-7
Figure 3-6 Bode Plots of the Voltages Loop Transfer Function With Current Loop Closed.......3-8
Figure 3-7 Bode Plot of Voltages Loop Gain .............................................................................3-9
Figure 3-8 Three-Level Diode-Clamped Converter as an Active Front End Using SinglePole, Triple-Throw Switches to Represent the Phase Legs .............................................3-10
Figure 3-9 State Machine of the Proposed PWM Technique...................................................3-11
Figure 3-10 PWM Generator Block Diagram ...........................................................................3-12
Figure 3-11 Flowchart of PWM Generator ...............................................................................3-13
Figure 3-12 Pulse Width Modulation as Function of Duty Cycle ..............................................3-14
Figure 3-13 Unity Power Factor Is Maintained Regardless of Load Conditions.......................3-14
Figure 3-14 Regulated DC Link Voltage ..................................................................................3-15
Figure 3-15(a) Full-Bridge DC/AC Inverter Circuit ...................................................................3-16
Figure 3-16(b) Behavior Circuit Model of a Full-Bridge Inverter Circuit ...................................3-16
Figure 3-17 Control System of a Full-Bridge DC/AC Inverter With a Simple Voltage Loop .....3-17
Figure 3-18 Transient Response With Simple Voltage Control Loop.......................................3-18
Figure 3-19 The Full-Bridge Inverter Control System With Feed-Forward Control ..................3-19
Figure 3-20 Transient Response With Feed-Forward Voltage Loop Control ...........................3-20
Figure 3-21 Complete IUT for System Simulation ...................................................................3-21
Figure 3-22 AFE Converter Simulation Diagram Showing Step Functions for VoltageSag Simulation .................................................................................................................3-22
xxiv
Figure 3-23 Inverter Simulation Diagram Showing Fixed Load Under Voltage-Sag
Operation .........................................................................................................................3-22
Figure 3-24 Voltage-Sag Simulation Results ...........................................................................3-24
Figure 3-25 Responses of DC Bus Voltages and Input Current After Voltage Sag .................3-25
Figure 3-26 Outage Compensation Simulation Results...........................................................3-26
Figure 3-27 Responses of DC Bus Voltages and Input Current After Outage .........................3-27
Figure 3-28 Simulation for Instantaneous Voltage Regulation Under Load Transients ...........3-28
Figure 3-29 Simulation Under Unbalanced Load Condition.....................................................3-29
Figure 3-30 Simulation Results Under 100% Overload ...........................................................3-29
Figure 3-31 Harmonic Compensation ......................................................................................3-30
Figure 3-32 Time-Domain Voltage and Current Waveforms of a Nonlinear Load ...................3-31
Figure 3-33 Harmonic Contents of the Nonlinear Load ...........................................................3-31
Figure 3-34 Inverter With Open-Loop Control..........................................................................3-32
Figure 3-35 Inverter With Closed-Loop Control .......................................................................3-32
Figure 3-36 Transient Response for the 400-Hz Output ..........................................................3-33
Figure 3-37 Modular IUT Design for Three-Phase Connection................................................3-33
Figure 3-38 Simulated Three-Phase IUT Input Voltage and Current Under Load-Step
Condition ..........................................................................................................................3-34
Figure 4-1 Typical Reliability Bathtub Curve.............................................................................4-2
Figure 4-2 Cumulative Distribution Failure Function F(t) for the Two Transformers ..................4-4
Figure 4-3 Schematic of Intelligent Universal Transformer Circuit Model ................................4-12
Figure 4-4 Block Diagram Representation of Intelligent Universal Transformer (IUT)
Design ..............................................................................................................................4-12
Figure 4-5 Snapshot Showing Different Regions in the Item Toolkit .......................................4-14
Figure 4-6 Section of IUT Schematics Showing Block 1r ......................................................4-16
Figure 4-7 Dialog Window of Item Toolkit Showing the General View (Left) and Physical
View (Right) Section.........................................................................................................4-16
Figure 4-8 Dialog Window of Item Toolkit Showing the Application View Section ...................4-17
Figure 4-9 Grid View of Item Toolkit Showing the Blocks and Their Failure Rate ...................4-17
Figure 4-10 Failure Rate of Different Blocks of IUT .................................................................4-22
Figure 4-11 Contributions of Each Block of IUT Towards Total Failure Rate of the
System .............................................................................................................................4-23
Figure 4-12 Schematics of ABBs Power Electronics-Based Distributed Transformer ............4-24
Figure 4-13 Schematics of Intelligent Universal Transformer Divided Into Three Distinct
Sections ...........................................................................................................................4-26
Figure 4-14 Cumulative Distribution Function of Failure Function F(t) for the IUT, ABB,
and Traditional Transformer .............................................................................................4-28
Figure 4-15 Comparison Showing the Failure Rate (Failures per Million Hours) of IUT
Design and ABB Design...................................................................................................4-29
Figure 5-1 Partition of Circuit Boards and Major Circuit Components .......................................5-1
xxv
Figure 5-2 Associated Cost of Individual Factors in the Two Design Options .........................5-12
Figure 6-1 Proposed Multi-Converter-Based Intelligent Universal System ................................6-4
Figure 6-2 A Stage-Gate Approach for New Product Development ..........................................6-7
Figure 6-3 A Generic Technology Roadmap for All-Solid-State Based Distribution
Transformers......................................................................................................................6-9
Figure 6-4 Available HV Semiconductor Devices and Their Applications................................6-11
Figure 6-5 DARPAs R&D Development Plan for HV Device...................................................6-12
Figure 6-6 HV Device Roadmap and Development Projection Based on DARPAs R&D
Program ...........................................................................................................................6-12
Figure 6-7 Requirements for the Next Generation HV Semiconductor Switches and
Diodes ..............................................................................................................................6-13
Figure 6-8 Are Present HV Semiconductor Devices Suitable for IUT Application? .................6-14
Figure 6-9 Cost Comparison for Off-the-Shelf Insulated Gate Bipolar Transistors (IGBTs)
A Direct Vendor Quote ..................................................................................................6-15
Figure 6-10 Insulated Gate Bipolar Transistor (IGBT) Structure and Symbol: (a) Basic
IGBT Structure, (b) IGBT Equivalent Circuit and Symbol.................................................6-16
Figure 6-11 Ilustrations of Insulated Gate Bipolar Transistors (IGBTs): (a) Discrete TO247 Package Rated Up to 1.2 kV and 50 A and (b) HV-IGBT Module Rated Up to
6.5 kV and 600 A..............................................................................................................6-16
Figure 6-12 Voltage and Current Waveforms of a High-Voltage Insulated Gate Bipolar
Transistor (HV-IGBT) Switching at 2-kV and 700-A Conditions .......................................6-17
Figure 6-13 Cost Trend for Silicon-Based Insulated Gate Bipolar Transistor ..........................6-19
Figure 6-14 Cost Trend and Projection for Silicon-Based Insulated Gate Bipolar
Transistor + Diode............................................................................................................6-19
Figure 6-15 Decrease in System Volume Through Utilization of SiC.......................................6-21
Figure 6-16 Projections of Possible Phases and Individual Tasks for Design and
Development (20042007) of the Proposed HV Multilevel Converter-Based IUT
Design ..............................................................................................................................6-30
Figure 6-17 EPRIs Long-Term Roadmap for the Proposed HV Intelligent Universal
Transformer Development Schedules and Important Milestones .................................6-30
Figure 6-18 EPRIs Long-Term Roadmap for the Proposed HV Intelligent Universal
Transformer Detailed Budget Estimate for Development Work in 20042007..............6-31
Figure 6-19 Schematic of the Proposed IUT Design ...............................................................6-47
Figure 6-20 Output Voltage Shows Glitches Under Load Transient, but the Magnitude
Remains Constant............................................................................................................6-50
Figure 6-21 Input Current Increases by Three Times During 50% Voltage Sag, but the
Output Voltage Is Not Affected.........................................................................................6-51
Figure 6-22 Input Current Increases by Five Times, and the Output Voltage Sees 2% Dip
After a 2-Cycle Outage.....................................................................................................6-52
Figure 6-23 Inverter Output Voltage Under Nonlinear Load Conditions ..................................6-53
xxvi
LIST OF TABLES
Table 1-1 Characteristics of Distribution Transformers Typically Used in United States ...........1-5
Table 1-2 Typical Costs Data for Three-Phase, Pad-Mounted Transformer..............................1-6
Table 3-1 Power Stage Parameters for the Active Front End ....................................................3-2
Table 3-2 Possible Switching States of Three-Level Diode-Clamped AFE Converter.............3-11
Table 4-1 Reliability of Components Versus Number of Years of Operation of the
Components.......................................................................................................................4-4
Table 4-2 Comparison of Various Reliability Models .................................................................4-6
Table 4-3 Components Used in the IUT Design ......................................................................4-13
Table 4-4 Parameter Values Required by the Component Diode............................................4-18
Table 4-5 Parameter Values Required by the Component IGBT.............................................4-19
Table 4-6 Parameter Values Required by the Component Capacitor......................................4-20
Table 4-7 Parameter Values Required by the Component Transformer .................................4-20
Table 4-8 Parameter Values Required by the Component Inductor ........................................4-21
Table 4-9 Results of the Reliability Prediction of IUT Design Using Item Toolkit.....................4-22
Table 4-10 Component List of ABB Design .............................................................................4-24
Table 4-11 Results of the Reliability Prediction of ABB Design Using Item Toolkit .................4-26
Table 4-12 Comparison of Total Components Used in ABB and IUT Design..........................4-27
Table 4-13 Comparison of the Failure Rates of ABB and IUT Design, Block-Wise .................4-27
Table 5-1 Bill of Materials for Three-Level 4.16-kV Power Circuit Board...................................5-3
Table 5-2 Bill of Materials for the Five-Level 8-kV Power Board ...............................................5-3
Table 5-3 Bill of Materials for the Gate Driver............................................................................5-4
Table 5-4 Bill of Materials for the Gate Drive Interface ..............................................................5-6
Table 5-5 Bill of Materials for the Sensor Conditioning Circuit...................................................5-7
Table 5-6 Bill of Materials for the Inverter Board .......................................................................5-8
Table 5-7 Cost Estimate for the Three-Level 4.16-kV IUT.......................................................5-11
Table 5-8 Cost Estimate for the Five-Level 15-kV IUT ............................................................5-11
Table 6-1 Operational Benefits An Overall Comparison .........................................................6-5
Table 6-2 Power Quality and Reliability Benefits An Overall Comparison ..............................6-5
Table 6-3 Options for Expanding Services Opportunities An Overall Comparison .................6-6
Table 6-4 Comparison of Price for Silicon Insulated Gate Bipolar Transistor Over the
Last Five Years From Different Vendors ..........................................................................6-18
Table 6-5 Key Properties of Wide-Band Gap Semiconductor Materials ..................................6-21
xxvii
Table 6-6 Basic Material Properties of Si and SiC...................................................................6-24

Table 6-7 Figure of Merit Comparing Si and SiC Devices .......................................................6-24
Table 6-8 SiC Device Cost and Performance Comparison......................................................6-26
Table 6-9 IUT 4.16-kV Projected Bench Model Development Schedule (Assumes
Funding Availability) .........................................................................................................6-32
Table 6-10 IUT 15-kV Projected Bench Model Development Schedule (Assumes
Funding Availability) .........................................................................................................6-33
Table 6-11 Budget Estimate Summary for 4.16-kV Bench Model Development .....................6-35
Table 6-12 Budget Estimate Summary for 15-kV Bench Model Development ........................6-35
Table 6-13 Budget Estimate by Task and Labor Category for 4.16-kV Bench Model
Development ....................................................................................................................6-36
Table 6-14 Budget Estimate by Task and Labor Category for 15-kV Bench Model
Development ....................................................................................................................6-37
Table 6-15 Projected IUT 15-kV Field Prototype Model Development Schedule ....................6-39
Table 6-16 Budget Estimate Summary for 15-kV Field Prototype Development .....................6-40
Table 6-17 Projected IUT Development Schedule During Field Deployment, Field Unit
Data Collection, and Functionality Verification .................................................................6-41
Table 6-18 Budget Estimate Summary During Field Deployment, Field Unit Data
Collection, and Functionality Verification .........................................................................6-41
xxviii
1
INTRODUCTION
Project Scope
The design analysis work presented in this report is part of a multi-year effort to develop the IUT
based on the all-solid-state approaches. It builds on the work done in 2002 to assess the
feasibility of replacing current distribution transformers with a more sophisticated device, the
IUT. The 2002 report [11] determined the technical and economic feasibility, clarified optional
technology/design paths, estimated the development cost, and identified early market entry
opportunities. Also, it was identified that use of HV power electronics in designing the primary
side of an all-solid-state transformer offers significant advantage in reliability and cost over lowvoltage (LV) designs.
It is quite clear that, even with the higher risk involved in all-solid-state designs, the preferred
research path should aim for the quantum leap in distribution transformer technology that is
possible with the all-solid-state approach rather than an incremental improvement achieved
through combination of existing technologies. As compared to the conventional copper-and-iron
based transformer, the HV multilevel solid-state transformer will not only reduce transformer
size and eliminate oil but will also enhance the power quality performance and increase the
functionality. Conceptually, the following functions that do not exist in the conventional
transformer can be obtained with the proposed IUT circuit:
1. Voltage sag compensation. When the input source voltage drops for a short period, the
universal transformer can compensate for the deficit and maintain constant output voltage.
The total period of compensation, as a function of the amount of energy storage, can be
adapted to the specific need of the customer.
3. Instantaneous voltage regulation. If the input source voltage fluctuates due to power system
transient or other load effects, the universal transformer will maintain constant output voltage
because it has the energy buffer.
4. Outage compensation. Similar to voltage sag compensation, the universal transformer can
provide full voltage compensation for the period needed by the built-in energy storage.
5. Capacitor switching protection. In general, a power-factor-correction capacitor switching
produces voltage transient on the nearby utility line. With the universal transformer, the
voltage transient will not propagate to the secondary (load) side.
6. Harmonic compensation. Nonlinear loads produce harmonic-distorted current that tends to
propagate back to the primary side of the transformer. The universal transformer will
maintain a clean input current with unity power factor.
1-1

Introduction
7. Single-phasing protection. If the input power source has a missing phase or running under
single-phase condition, the universal transformer will have a detection circuit and shut the
output to prevent the system from running under an abnormal source condition.
8. DC output. The universal transformer has a dc/ac three phase-leg inverter circuit that can be
configured to become an interleaved three-leg dc/dc converter, thus providing dc output if
necessary.
9. 400-Hz output. The output of the universal transformer is a dc/ac inverter that can be
configured for 400-Hz output rather than conventional 60-Hz or 50-Hz output.
10. Variable-frequency output. Similar to the 400-Hz output function, the frequency of the
universal transformer output could be a variable that is set by the user.
With the above listed functionalities, it is clear that the next generation distribution transformer
requires substantial power electronics and control elements. In this report, a high-voltage
multilevel converter-based IUT is proposed for the next generation distribution transformer. The
proposed IUT design includes back-to-back, interconnected, multi-level converters coupled to a
switched inverter circuit via a high-frequency transformer. The input of the universal transformer
can be coupled to a high-voltage distribution system, with the use of existing high-voltage silicon
IGBT devices, and the output of the universal transformer can be coupled to low-voltage
applications.
The scope of this years activity was to conduct a comprehensive design analysis of a multilevel
converter-based IUT, using HV power electronics on the input side. Details of the power
electronics circuits and the associated open-loop and closed-loop controller designs that are
required in an IUT to enhance the transformer functionality are provided. The detailed IUT
power stage design, its specification based on a certain KVA and input/output voltage range (1phase 15kVA), AutoCAD drawing, reliability assessment, modeling and simulation results for
IUT functionality verification, and performance verification of both power stage and controller
designs are also presented in this report. This design analysis will then serve as a blueprint for
the development of the IUT and form the basis for competitive bidding (in 2004) for product
development in 20042007. A more refined EPRI long-term roadmap for the development of the
universal transformer with better cost estimates and schedule for the development work in 2004
2007 is also outlined in this report.
Conceptually, the solid-state power-conversion-based distribution transformer will be much
more expensive than the conventional one. However, the electronics can be designed with
modularity and expandability. When considering the enhanced functionality and the flexibility,
the added cost can be easily justified. In fact, the cost of power semiconductor and associated
controls has exponentially decreased over the past few decades. Whether or not the IUT can be
economically viable is also evaluated in this report. Also, this report identifies the key
functionalities and criteria that need to be met in order for this technology to gain market
acceptance.
Critical issues that are addressed in this report, therefore, include:
1-2

Introduction
Determination of design packaging and thermal management systems
Development of a more refined EPRI long-term roadmap for the development of the
intelligent universal transformer with better cost estimates and schedule for the development
work in 20042007
Subsequent sections provide a brief overview of present-day distribution transformers based on

type and design characterization, ongoing technology improvements in transformer designs, and
possible market drivers for the universal transformer, a device that is expected to provide a range
of functionalities beyond those available with conventional transformers.
The Good Old Distribution Transformer

In the early 1900s, as an alternative to Thomas Edisons DC power system, Westinghouse
introduced an AC power system based on a transformer technology that can easily step up or step
down AC voltage levels as required for power transmission, distribution, and retail consumption.
Today, these good old distribution transformers (see Figure 1-1) are still used at virtually every
site where utility power is delivered for use. Distribution transformers, whether mounted
overhead on a power pole or mounted on the ground, reduce the voltage to a more usable level,
typically 480/277 V (for three-phase application) or 208/120 V or 240/120 V (for single-phase
application).
1-3

Introduction
DISTRIBUTION TRANSFORMER
POLE-MOUNTED TRANSFORMERS
PAD MOUNTED TRANSFORMERS
Figure 1-1
Distribution Transformer
Table 1-1 lists the characteristics of distribution transformers typically used in the United States.
Utilities and commercial and industrial users purchase more than 1 million new distribution
transformers annually. The vast majority of distribution transformers on the utility-owned
distribution system are liquid-immersed (purchased using total-owning cost criteria, accounting
for cost-of-energy losses), while those used in commercial and industrial applications are
predominantly dry-type. Liquid-immersed transformers are the predominant type of transformer
and represent the oldest technology with the most established performance record. In contrast to
the dry-type units, which use the natural convection of air for cooling, liquid-filled transformers
rely on oil or other liquid dielectric medium circulating across their coils for cooling.
1-4

Introduction
Table 1-1
Characteristics of Distribution Transformers Typically Used in United States
Transformer
Type
Phase
Primary Voltage
(kV)
Secondary
Voltage (V)
Capacities
(kVA)
Liquid-immersed
34.5 and below
600 and below
1500
Liquid-immersed
34.5 and below
600 and below
32500
Dry-type
34.5 and below
600 and below
15833
Dry-type
34.5 and below
600 and below
152500
Dry-type
1and 3
34.5 and below
600 and below
0.2515
For purposes of this report, distribution transformers are defined as all transformers that
perform the final transformation from electric utility power distribution line voltages (4 to
34.5k V) to final lower secondary utilization voltages (120 to 480 V) suitable for customer
equipment. These transformers typically range in size starting from 10 kVA, single-phase to
3000 kVA, three-phase. High-voltage (that is, 69- to765-kV) transformers are considered power
transformers, not distribution transformers, and thus are not included here.
Why Look at Anything Else?

Given the growing environmental, economic, and governmental concerns for building new
power-generation facilities, utilities continue to look for cost-effective ways to defer new power
generation while meeting their customers growing demand for electricity. Even a true visionary
like Thomas A. Edison could not have imagined the level of sophistication that would be
required of equipment used for the transmission and distribution of electric power a little more
than a hundred years after its invention. Nor could he have anticipated all of the complex issues
facing the electrical industry as it moves into the 21st Century. As the distribution transformer
enters its second century of service, it is not easy to predict whether this device is here to stay or
how its evolution will proceed.
The positive attributes of conventional distribution transformers, well documented for years,
include low cost, high reliability, and high efficiency. They are among the most reliable of
components in power-conversion systems, with an ability to handle 500 times the power and 15
times the voltage of their turn-of-the-20th Century ancestors. Their weight per unit of power has
dropped by a factor of 10, efficiency typically exceeds 99%, and they have an average lifetime of
30 years or more. Figure 1-2 shows efficiency trends for distribution transformers over the past
several years. Standard costs for three-phase, pad-mounted transformers range from $40 to
$100/kVA for sizes ranging between 50 and 150 kVA (see Table 1-2).
1-5

Introduction
Efficiency @ Maximum Load (Liquid Type)
Efficiency @ 15% Load

(Liquid Type)
Efficiency @ Max.
Load (Dry Type)
Efficiency @ 15% Load

(Dry Type)
SOURCE:
Barnes, P., Van Dyke, J., McConnell, B., and S. Das, Determination Analysis Of Energy Conservation Standards For Distribution
Transformers, ORNL 6847, Oak Ridge, TN, July 1996
Van Dyke, J., Barnes, P., McConnell, B., and S. Das, Supplement T o The Determination Analysis Of Energy Conservation
Standards For Distribution Transformers, ORNL 6925, Oak Ridge, TN, Sept. 1997
Figure 1-2
Efficiency Trends Over Several Years for 75-kVA, Three-Phase Distribution Transformers
Table 1-2
Typical Costs Data for Three-Phase, Pad-Mounted Transformer
Cost ($)
Size (kVA)
12.5 kV
34.5 kV
75
7,749
10,584
150
9,450
11,605
300
11,718
15,574
500
13,608
20,034
750
21,357
21,377
1000
25,515
28,350
NOTE: Above costs include necessary cable terminations, pads, miscellaneous material and transformer, but no
primary or secondary cables.
Transformer purchasing decision impact overall efficiencies for transformers in use today. There
are five different types of purchasing practices used by various market players in the distribution
1-6

Introduction
transformer market. These practices are first cost, total life-cycle owning cost (TOC), band of
equivalence (BOE), over-sizing, and choice of winding materials. The last two practices are the
only ones not based on economics, but they play an important role in transformer-purchase
decision making for some end users.
Transformer purchases are treated as capital expenditures for equipment with an expected life of
30-40 years; however, lack of capital causes most small and mid-sized end-users to favor the
short-term purchasing criteria (that is, the first cost) with short payback periods (that is, 1-3
years). Purchases of transformers are often based on the first cost (without any consideration of
long-term economics) when transformer evaluation and purchase decisions are not made, by the
end-user. This is particularly true where purchase decisions are made on the basis of temperature
rise and low first cost for commercial and industrial end-users buying dry-type, pad-mounted
transformers. In addition, these users are not always aware of, and in some cases are uncertain
about, the costs and benefits of using energy-efficient transformers.
In recent years the increases in capital and operating costs for power plants, difficulties in citing
new facilities, and concerns for the environment have forced utilities to evaluate energy
efficiency. These concerns for energy efficiency have been translated by utilities into loss
evaluations for their transformer and equipment purchases, expressed as dollars per kilowatthour saved. Higher the loss evaluation translates to more premiums to minimize energy losses.
The loss evaluation rates (rates that a utility is willing to pay per watt reduction in rated core
and conductor losses) needed to calculate TOC, are currently supplied by most electric utility
purchasers by evaluating the specific application situation (for example, duty cycle, cost of
capital, expected life). Most pole- and pad-mounted transformers are currently loss-evaluated,
while almost no dry-type transformers are evaluated. In some cases, utilities also offer rebates to
customers for undertaking loss evaluations and then monetary assistance to buy down a more
expensive, more energy-efficient transformer where it meets utility savings criteria. For example,
Bonneville Power Administration offers a one-time incentive of up to $0.15/kWh saved in the
first year of operation to its utility and industrial customers. Unfortunately, these programs rarely
extend to the smaller distribution transformers that are common in C&I facilities. Thus, most
commercial, institutional, and light-duty industrial end users, for whom a transformer purchase
decision is more peripheral to their business than it is for a utility, do not use loss evaluations
such as TOC, which require extensive analysis and the input of many variables. Because of
tightening in the availability of capital budgets these days, there is a growing trend even among
utilities to use either some form of TOC or first-cost criteria for making liquid-filled transformer
purchase decisions. The move away from the TOC purchasing criterion results in the selection of
a less efficient transformer and hence reduces the energy conservation potential. Details of other
criteria are provided in the 2002 report Feasibility Assessment for Intelligent Universal
Transformer (EPRI, Palo Alto, CA: 2002. 1001698) and also documented in Determination
Analysis Of Energy Conservation Standards For Distribution Transformers, Barnes, P., Van
Dyke, J., McConnell, B., and S. Das, ORNL 6847, Oak Ridge, TN, July 1996.
Were it not for these stationary, almost totally silent, highly reliable devices, the distance
separating generators from customers would have been significantly greater, many households
and industries would require their own substations, and electricity would have been a much less
practical form of energy. Unfortunately, like other devices in modern electrical distribution
systems, the conventional transformer also has some drawbacks. These drawbacks include
voltage drop under load, inability to mitigate flicker, sensitivity to harmonics, environmental
1-7

Introduction
impacts when leaks of mineral oil occur, limited performance under DC-offset load unbalances,
inability to convert single-phase service to three-phase for powering certain types of equipment,
and no energy-storage capacity. One consequence of not having energy-storage capacity is that
the output can be easily interrupted because of a disturbance at the input. Also, when the output
load current generates harmonics and reactive power, the conventional transformer reflects them
back to the input side.
Owing to their bulky iron cores and heavy copper windings, conventional transformers are by far
one of the heaviest parts in an electrical distribution system. The size and weight of the
transformer is primarily a function of the saturation flux density of the core material and
maximum allowable core and winding temperature rise [1]. The saturation flux density is
inversely proportional to frequency, and hence increasing the frequency allows higher utilization
of the steel magnetic core and reduction in transformer size. However, because the operating
frequency of commercial power is ordinarily fixed (60 Hz in the United States), the volume and
the weight of the distribution transformer cannot be reduced below its definite values. Whats
more, they do experience continuous no-load or core losses that arise from being constantly
energized and ready to serve a load.
As pressure increases on electric service providers to provide a higher-quality and more reliable
product on demand and at a price point that is acceptable to customers, there is desire to increase
utilization of conventional transformers. It has been shown in prior studies [2, 3, 4] on
distribution transformer performance, efficiency, and loss evaluations that even small changes in
efficiencies can add up to a large net gain in energy savings. On the basis of these energy savings
study results, many researchers are exploring the potential for high-energy-efficiency
transformers over conventional copper and iron core transformers. While some major
improvements have occurred in transformer technology from time to time (such as the
introduction of grain-oriented core steel), other developments in the areas of core, winding,
insulation, and dielectric liquids have provided only incremental improvements in transformer
technology. The question, then, is this: Will present and emerging incremental improvements to
conventional transformers provide a solution for the future? Or, is there a need for a technology
replacement?
Can the Opportunity to Offer a Wide Range of Services Be Realized

Through Incremental Improvements in Conventional Transformers?
While more than 1 million new distribution transformers are purchased annually, utility
distribution transformers account for an estimated 61 billion kilowatt-hours (kWh) of the annual
energy lost in the generation and delivery of electricity. Additional transformer losses in nonutility applications are estimated to be 79 billion kWh [2-3]. As mentioned in the preceding
sections, the U.S. Department of energy (DOE) and many other institutions are focusing a great
deal of time and money in research on the economic benefits of increased efficiency in
distribution transformers.
If increasing reliability and efficiency and lowering initial costs are the primary goals, then
incremental improvements in conventional transformer technology may well be the desired
approach. However, this economic gain will more than likely not be realized directly by many
end users, because utility metering is typically located at the secondary of the transformer. End
1-8

Introduction
users could see some indirect savings because reducing losses in utility transformers should
reduce the overall cost of electricity. However, there are other factors in todays market
environment to consider, including increased sensitivities of customer equipment and process,
increased need for DC power created by the next-generation DC loads, higher energy costs,
increasingly stringent environmental regulations, and diminishing energy reserves.
A conventional transformer lacks energy-storage capability, and thus the output can be easily
interrupted due to the disturbance at the input. When the output load current generates harmonics
and reactive power, the conventional transformer also reflects them back to the input side. To
overcome these problems, modern power electronics technology can be used to serve as the
energy buffer between the source and load to avoid direct impact from either load-to-source or
source-to-load. With the flexibility of power electronics switching, it is also possible to provide
universal voltage outputsuch as DC voltage or variable-frequency AC voltageto the load.
The next sections identify possible market drivers for a sophisticated transformer, a device that is
expected to provide a range of functionalities beyond those available with conventional
transformers.
Short-Range Market Driver Improved Power Quality and Reliability
In todays environment, power producers need to mix and match their electrical service offerings
to meet the customers changing requirements. The need for a sophisticated transformer that can
employ modern power electronics to improve transformer functionality has increased because of
the emerging digital economy, which requires a high degree of power quality and reliability.
Matching the voltage requirement within a certain range was once and remains now the primary
functional requirement for a transformer. However, the proliferation of sensitive loads in
residential, commercial, and industrial customer segments has led to the need for a power supply
that not only meets the steady-state voltage criteria but also can buffer the load from line-side
transients such as voltage sags.
Solutions can be implemented at different levels of the system for an end user that has equipment
or processes that are sensitive to electrical disturbances. Figure 1-3 illustrates a solution that
could be provided at four different levels. Traditionally, equipment-level solutions for power
quality are usually the most cost-effective method. However, equipment-level solutions require
detailed knowledge about the specific equipment to be protected. In many cases, without
cooperation from the equipment vendor, it is not practical to implement equipment control-level
solutions. On the other hand, a facility-level or bus-level solution will require a larger power
quality mitigation device, and the cost is typically more than equipment-level solutions. Both of
these options need to be carefully evaluated before deciding which will be the optimal solution.
1-9

Introduction
INCREASING COST OF POWERCONDITIONING
4 - Utility Solutions
Utility
Source
3 - Overall
Protection
Inside Plant
Feeder or
Group of
Machines
2 - Controls
Protection
1 - Equipment
Specifications
1
2
CONTROLS
MOTORS
OTHER LOADS
Sensitive Process Machine
INCREASING KNOWLEDGE ON EQUIPMENT SENSITIVITY
Figure 1-3
Options for Power Quality Mitigation at Different Levels
As illustrated by Figure 1-4, the more knowledge that is available concerning the exact reason
why the facility equipment is vulnerable to voltage sags, the less costly the mitigation solution
can become. EPRI and its utility members have gained this knowledge through years of power
quality research. In some industries, the general knowledge of equipment susceptibilities and
solutions is more mature than in others.
1-10

Introduction
Utility Solutions
Whole Plant Solution

Protect Entire Facility
Relative Cost of Solution
106
Panel Feeder Solution

105
104
Protect Feeder or
Group of Machines
Machine Solutions
Protect Whole Machine or
Machine Control Circuits
103
102
Embedded Solutions
More Robust Relays,
Power Supplies,
Contactors, Sensors, etc.
DC
AC
Knowledge of Equipment Sensitivity
Figure 1-4
Cost of Power Quality Solution Versus Knowledge of Equipment Sensitivity
With costs running into the millions of dollars, a medium-voltage approach to protect an entire
facility or plant can be very expensive; a survey of end users indicates that industrial customers
are rarely willing to pay these kinds of dollars to solve a problem that they perceive as being the
electric utilities responsibility. In addition, the traditional system or custom power approach
may or may not have adequate knowledge of equipment sensitivity to resolve some power
quality performance issues.
However, if you take this traditional approach and turn it upside down, the delivery of service is
a smart interface device that enables utilities to provide power that can respond to and literally
meet the changing dynamic needs of the equipment. This approach could radically alter the way
electric utilities serve their respective customers. By integrating a smart devicethe
transformerto the main delivery point for most customers, the utility can broaden the
traditional service offerings and satisfy a myriad of customer requirements for power quality.
The concept is one that is a scalable, configurable, programmable, transformable, multifunctional approach to serving the customer. By integrating such a smart device to the main
delivery point for most customers, the utility can broaden the traditional service offerings and
satisfy a myriad of customer requirements for power quality. These intelligent devices could then
expand the capabilities of a conventional distribution transformer from primarily a voltagetransformation device to an integrated electrical customer interface and at the same time provide
advanced distribution-automation functionalities.
1-11

Introduction
Short-Range Market Driver Powering Three-Phase Loads From a Single-Phase

Service
In many rural areas and for small commercial and industrial customers, providing three-phase
service is not cost effective. However, these customers have a number of applications that can
benefit from three-phase power, which has created a market for static and rotary phase
converters that convert single-phase service to three-phase for powering certain types of
equipment. Applications that benefit from phase converters include:
Woodworking Workshops
Three-phase equipment in a woodworking shop includes saw, spindle molder, planer,
thicknesser, belt sander, band saw, CNC machine, four-sider, tenoner, mortiser, combination
machine, woodturning lathe, sander, router borer, edge-bander, and dust extractor.
Metalworking Workshops
Three-phase equipment in a metalworking shop includes lathe, drill, milling machine, grinder,
saw, polisher, shaper, guillotines, press, and welder.
Vehicle Servicing
Three-phase vehicle services include post lift, hoist, welder, and wheel balancer.
Farming
Three-phase farming equipment in a farm includes pump, compressor, irrigation system, air
conditioning, refrigeration unit, conveyor, crane, hoist, wine press, olive oil processor, and grain
mill.
Mid-Range Market Driver DC Distribution
The proliferation of power electronics in end-use loads has also resulted in a renewed interest in
dc distribution systems. If most of the power-electronics-based loads convert ac to dc internally
through power supply, then why not provide dc power directly to equipment and bypass the
additional cost and energy waste involved in a built-in equipment power supply? This realization
has led to some long-term strategic thinking among researchers on the merits of a dc distribution
system. The push for a sophisticated transformer design to some extent is also spurred by this
renewed interest in dc distribution systems and the need for dc power for telecommunication and
other applications.
Figure 1-5 shows the schematic of a typical powering configuration for telecommunication
equipment. Traditional telecommunication equipment generally requires 48 volts of dc input
power. The most common configuration for providing 48 Vdc is through multiple parallel1-12

Introduction
redundant rectifiers that convert the utility ac power to 48 Vdc that charges lead-acid storage
batteries and supplies power to the critical load. When other voltages are required, dc-to-dc
converters or dc-to-ac inverters are used to derive the required voltage. When ac power fails, a
battery may be called upon to support a critical load for a long time. Backup battery times may
range from 1 hour to more than 24 hours, with 3 to 8 hours being common. Sometimes, enginegenerators are used to supplement the utility AC power and to reduce reliance on battery backup.
As telecommunication and Internet industries grow, these market segments will continue to push
for dc-powered systems.
Paralleled
Rectifiers
Transient Limiting
Distribution*
DC Loads
Utility
Power ATS
E-G
Primary
Source
Area
Paralleled
Battery
DC
Strings
(48-volt Distribution
System
standard)
Power Equipment Area
Load Area
(Telecom
Equipment)
ATS Automatic Transfer Switch

EG Engine Generator
Figure 1-5
Typical Powering Configuration for Telecommunication Equipment
In the early days of electric power, utilities often had at least some provisions for providing dc
power to their customers. The following is an excerpt from a Pacific Gas & Electric (PG&E)
tariff document:
New direct-current (DC) or two-phase service is not available. Direct-current service and
two-phase service is supplied only to existing customers who continue to operate existing
DC or two-phase equipment. Such service is being gradually replaced by standard
alternating-current service.
In fact, back in the late 1800s, dc ruled. During this time, approximately 121 Edison power
stations delivered dc to Edison customers across America. But with the 3-mile limitation of the
dc system and the advent of a high-voltage ac system that could provide power for hundreds of
miles with little loss, a shift began to take place. In the early 20th century, Westinghouses ac
power distribution scheme became dominant over Edisons dc distribution approach, primarily
because efficient ac power transformers were available and efficient dc transformers were not.
With the development of high-power insulated gate bipolar transistors (IGBTs) and the
development of effective methods for combining IGBTs into very high-power circuits, the
technology now exists to replace traditional ac distribution technology with efficient dc voltage
transformers.
1-13

Introduction
The push for use of direct current will continue and grow because of a number of advantages,
which include:
DC distribution links can directly supply power to digital devices without need for dc/ac
converters.
More and more of the electric equipment used in the home or at the office is internally dcpowered. For connection of such equipment to the mains, rectifiers are needed. In principle,
the electric equipment maybe directly dc-powered, without any modifications.
DC cables can be placed in the same ducts as gas and water pipes because they do not
generation of ac-induced currents.
Technically, dc is more simplistic and adapted to providing longer periods of ride-through

and redundancy.
DC is easier to isolate from disturbance-causing loads.
Long-Range Market Driver High-Frequency AC Power

The last and most futuristic market driver is the potential need for high-frequency ac delivery for
various applications. Many in the research and academic communities are investigating the
feasibility of expanding this type of delivery, with the potential benefits of high end-to-end
system efficiencies, distributed heat profile, point-of-use regulation, and the ability to reduce
overall size of conversion units and other electrical equipment. In fact, the concept of a highfrequency power distribution system originated from the National Aeronautics and Space
Administration (NASA) over 25 years ago. The military, aerospace, and aircraft industries have
used 400-Hz power for many years because of the size and weight advantages of high-frequency
components. Despite the fact that much of the worlds available commercial power is 50 or
60 Hz, many larger mainframe computers require higher-frequency power, because there are
inherent advantages to higher frequencyfor example, high-frequency electrical components
such as transformers and inductors are significantly smaller in size and weight while providing
the same power capacity, and high-frequency ac requires less filter capacitance.
Expanding Traditional Service Offering Through a Sophisticated Device
When the electric service provider asks a potential customer what type of service is needed, that
customer may want dc power, some level of premium power, uninterruptible power, or some
level of voltage sag protection. The local distribution customer may be able to provide some
options, but the customer could be left on its own to install the equipment necessary to protect
sensitive electronic loads or convert to the type of dc voltage required by dc-driven loads. By
expanding the traditional service offerings, utilities could differentiate themselves by integrating
various power requirements, communications, monitoring, and measurement into a truly
universal, integrated, electronic customer interface.
As shown in Figure 1-6, some existing customer power requirements today include:
Load that requires sag protection
1-14

Introduction
Load that requires good voltage regulation (in finer steps than traditional on load-tap
changers)
Load that needs dc power
Load that needs high-frequency ac power (for example, 400-Hz)
Load that may need full outage protection (against either a momentary interruption of 1 to 5
seconds or a long-term interruption where a standby service or generator is required)
Load that needs active harmonic filtering
Load that needs protection from utility capacitor-switching transients
Load that needs protection from single phasing (that is, one primary fuse on the utility feed
blows creating a single-phasing condition)
Figure 1-6
Standard Delivery for Various Requirements Today
If these are legitimate needs that customers have today, is there an opportunity to better serve
these needs? A more flexible, multi-functional approach to the problem might be for the electric
service provider to offer a broad array of services that reach beyond the traditional bounds of
providing electric power. The concept is that in the future, it will be possible for the utility to
offer not only the regular 120-V, 208-V, 240-V, 480-V, or other single-phase or three-phase
service, but as part of its regulated service offering, the utility could also offer 24 Vdc, 48 Vdc,
ac supply with sag protection, ac supply with sag and momentary protection, or virtually any
combination imaginable. This is the first step toward an even broader integration and offering of
power, communications, and data that have been under review in the power industry for some
time. In this first step, for example, a particular customer might have the following total power
demand requirements:
(x + y + z) kVA
Eq. 1-1
Where:
1-15

Introduction
x = demand (in kVA) for 480-V, three-phase unprotected ac power

y = demand (in kVA) for 24/48-V dc power
z = demand (in kVA) for 480-V, three-phase voltage with sag protection up to 50% and
active harmonic compensation
Figure 1-7 offers a graphic illustration of this scenario.
Figure 1-7
New Expanded Service Opportunity
Can the Opportunity to Offer Improved Operational Benefits Be Realized

Through Incremental Improvements in Conventional Transformers?
As well as meeting the customer needs outlined in the scenario illustrated by Figure 1-7, utilities
need to make long-term capital investments on technologies that will completely change
distribution transformer design to achieve other additional key operational benefits, namely:
Significantly reduce inventory costs by introducing standardized transformer designs
Considerably reduce the size and weight of magnetic components
Dramatically reduce environmental concerns by introducing a design that does not use
mineral oil or other liquid dielectrics
Provide reactive compensation
Efficiently manage distribution resources by incorporating on-line monitoring and other

advanced distribution automation (ADA) functionalities. (One potential area for monitoring
resources is to monitor distribution transformers in order to minimize unnecessary
maintenance and replacement, thus enhancing network operation efficiency and providing
outage-notification services.)
1-16

Introduction
Operational Benefits Reduced Inventory Through Standardization

There are fixed and variable costs in maintaining an inventory of distribution transformers.
Recommended practice for distribution planners is to establish standard transformer inventory
sets that provide a linear range of applications. Therefore, the first order of business in planning
and executing stocking practices is to ensure that a good set of basic building blocks (such as a
group of transformer types and sizes for different voltage class ratings, covering the required
range of loading) is readily available and that specifications and utilization are correct.
In an effort to reduce the minimum efficiency standards, NEMA in 1996 developed the voluntary
industry standard TP-1-1996, Guide to Determining Energy Efficiency for Distribution
Transformers (updated in 2002). NEMA has 73 different kVA ratings in its updated TP-1-2002
document, spanning the range of liquid and dry-type transformers. These kVA ratings are based
on industry standard ratings outlined in the ANSI/IEEE C57.12.00 for liquid types and
ANSI/IEEE C57.12.01 for dry-types. Figure 1-8 provides an instance of possible confusion, such
as those often faced by distribution planners while executing stocking practices from these
standard product classes.
Central Generating
Station
Step-Up
Transformer
Typical Service delivery voltages

2.2kV
4.2kV
12.5kV
13.8kV
24.9kV
34.5kV
Receiving
Station
Distribution
Substation
Distribution Transformer
Commercial & Industrial

Customers
How many permutation and combinations are

required to establish a standard inventory
transformer set?
Single Phase
(type-Liquid Immersed)
Three Phase
(type-Liquid Immersed)
Size (kVA)
# of Units
Size (kVA)
# of Units
10
234,098
15
3,032
15
330,825
30
3,032
25
458,965
45
4,042
37.5
82,779
75
6,063
50
211,116
112.5
2,425
75
47,086
150
7,882
100
31,263
225
4,042
167
20,087
300
8,792
250
3,237
500
6,639
333
2,867
750
3,592
500
2,704
1,000
2,155
667
1,500
2,065
833
18
2,000
606
2,500
1,724
Figure 1-8
Importance of Standardization
To cut inventory costs, some utilities are assessing their transformer requirements and are
eliminating some of the sizes. When a utility has fewer transformer sizes available, it must
increase the range of loads for a given size, with the result that some units have higher loads.
Prior studies on loading trends found that most utilities expect the average loads on distribution
transformers to increase. A large survey of 64 utilities by Edison Electric Institute (EEI) found
that nearly half of the respondents plan to load transformers at more than 100% for new
customers. Moreover, the inventory set would also increase as the need for specially customer
designed units (precisely tailored to a specific situation) increases.
1-17

Introduction
The opportunity to realize standardization of distribution transformers through a sophisticated

device (as compared to the existing practice based on multiple kVA size, primary voltage,
secondary voltage) will result in a substantial reduction in inventory cost. It is evident that a
more standardized transformer design would (1) reduce the number of permutations and
combinations that are presently required during planning, (2) save utilities millions of dollars per
year in terms of inventory costs, and (3) simplify stocking practices and procedures that are
presently required to maintain and establish a reliable inventory set. Depending upon the
complexity of the distribution infrastructure (I.e., the number of distribution system voltages
existing at a given utility) the importance of standardization and the associated cost savings
realized via inventory reductions can represent tens of millions of dollars. The dollar value
becomes even more significant when the reduced per-unit cost due to increase volume
purchasing is factored into the economic analysis. As an example, imagine the impact of the IUT
for Carolina Light and Power, north utilitys largest electric operating company, which has ten
different distribution voltages in use today.
It should also be noted that asset-carrying costs usually represent almost 50% of total distribution
resource usage (see Figure 1-9) and that an inventory of distribution transformers represents a
significant portion of the inventory cost. A 5% savings in the asset-carrying cost through
standardization of distribution transformers represents a savings of approximately $12.5 million
for a utility with a total annual revenue of $500 million.
Source: Distribution System Cost Structure , EPRI Report TR-109178
Electrical Losses (2.0%)
Other (2.9%)
Equip ment (3.1%)
Outside Services (7.8%)

M aterials and Supp lies
(12.9%)
Labor (21.8)
Distribution Plant Asset
Carrying Cost (49.5%)
100
200
300
400
500
($ Million)
Figure 1-9
Variations in Distribution Resource Usage
1-18
600
700
800
900
1000

Introduction
Operational Benefits Advanced Distribution Automation

Distribution transformers can be automated to record and transfer vital power quality
information. Advanced distribution automation provides opportunities to develop new
applications for condition monitoring and asset management purposes. An important
functionality of an IUT is to provide an early warning on possible growing operating stresses
which in turn will lead to improved reliability. Reliability today is a significant issue with
customers and regulators alike, in nearly every state in our country. Development of a new
technology which will enable utilities to pro-actively initiate actions that will result in improved
reliability of the overall power system.
Another aspect associated with being able to use the IUT to provide utilities with information
that will improve reliability is the associated cost savings for not to spend maintenance dollars to
repairs or replace equipment which has failed (and caused a customer outage). More often or not,
this maintenance (O&M) work is performed outside normal working hours (and therefore at a
premium wage rates). Transformer-caused outages are common on the distribution system today,
and having the ability to proactively address/correct imminent problems, at normal wage rates,
can provide very significant annual cost savings. Improved reliability and reduced O&M can
provide meaningful value, which can be applied to offset the higher cost for the IUT, compared
to conventional transformers.
Some of the advanced monitoring capabilities that could be incorporated include:
Instantaneous current and average demand current
Instantaneous voltage and current harmonics as a percent of fundamental
Instantaneous and average demand power factor, kW, kVAR, and kVA
Single-phase and three-phase kWh
Real time event data, for example, fault current, voltage-sag magnitude and duration, and so
on
The data can be transferred using either a standard networking protocol or by adopting a new
protocol specifically tailored for the application. The only protocol that is presently available for
TM
all utility operations is the Utility Communication Architecture (UCA ). The UCA provides
interconnectivity among equipment and interoperability among various databases and
microprocessors. The UCA contains open protocols and uses national and international standards
that are publicly available. Hence, it provides interconnectivity among equipment and
interoperability among various databases. Remote monitoring and control of intelligent universal
transformers can provide insight into the operating history and current condition of the
transformer. This early warning on possible growing operating stresses can help prevent costly
and burdensome unplanned outages. More sophisticated automation functionalities, integrated
with the sophisticated transformer, can also serve as an outage notification device that can be
integrated with a utilitys outage-management system.
1-19

Introduction
Operational Benefits Environmental

Appropriate power electronics-based transformer design can yield an oil-free transformer that
would be more environmentally friendly. Using power electronics components along with proper
heat sink and airflow design, the benefits of such an oil-free transformer can be realized.
Operational Benefits Reactive Compensation
Reactive compensation using power electronics inverters serves as the basis for dynamic reactive
compensation systems such as the dynamic static compensator (DSTATCOM). It is feasible to
apply reactive compensation to sophisticated transformer design in order not only to control the
load power factor but also to provide reactive compensation to the system.
Emerging Power Electronic-Based Transformer Designs

Recently, new transformer designs have captured the attention of end users as well as equipment
producers. These new designs have resulted from the marriage of modern power electronics and
advanced solid-state switching technologies to conventional transformer technology. Solid-state
switching technologies allow power conversion between different formats such as dc/dc, dc/ac,
ac/dc, and ac/ac with any desired frequencies. Perhaps the most widely used solid-state switching
technologies are the dc/dc converters for power supply applications and dc/ac inverters for
motor-drive applications.
The solid-state transformer [5, 6, 7] is most often found where the main purpose is to convert ac
to ac for step-up or step-down, its function being the same as a conventional transformer but with
much reduced size and weight. The key elements of the solid-state transformer are an ac/dc
converter and a dc/ac inverter. One problem associated with these basic solid-state ac/ac
conversion techniques is the inability to provide isolation between the primary and secondary
sides of the transformer. To convert two different voltage levels, it is necessary to have
transformer isolation to fully use the silicon switches. To realize such a design, one proposed
solution is to modulate the input ac waveform by a power electronics converter to a highfrequency square wave, which is then passed through a small, high-frequency transformer (see
Figure 1-10).
Input Stage
Power
Electronics
High Frequency
Voltage
Conversion Link
Output Stage
Power
Electronics
Figure 1-10
Realizing the High-Frequency AC Link Stage in a Design
The high-frequency link has been studied extensively in power electronics systems. Several
designs for solid-state power converters having high-frequency ac transformers have been
proposed in the past. The original concept was first proposed in 1970 by McMurray [8], who
1-20

Introduction
termed the high-frequency ac/ac link an electronic transformer. Barbi et al in 1991 [6] added
magnetic isolation by introducing a high-frequency transformer to the classic ac/ac buck-boost
regulator suggested by Bowers in 1980. Their topology provides electrical isolation between
output and input to the buck-boost capability, in this respect adding to the original work of
Bowers. However, the design and simulation was not done for duty-ratio greater than 0.5, where
the simplified output/input voltage relationship is not valid, and a more complicated expression
must be used. Also, Barbi et al suggested no compensation or control schemes to stabilize the
converter for different cases of input and load regulation requirement. Even though the authors
discussed aspects of design including an input filter, power-factor calculation, and output-current
ripple, their discussion features two omissions: (1) Design performance during abrupt changes in
the load and line voltages was not addressed, and (2) primary voltage and power levels used
were several orders of magnitude below typical utility distribution levels.
Another attempt to introduce a high-frequency link, suggested by Prased Enjeti et al, 1999 [9], is
to use ac/ac frequency converters on the primary and secondary sides of the existing transformer.
In this topology, the low-frequency input, sine-wave voltage (60 Hz) is first converted to a highfrequency AC link (typically a few kHz) by the primary-side converter, which is then
magnetically coupled to the secondary side. The isolated high-frequency voltage is unfolded into
a low-frequency (60 Hz) waveform by the secondary-side power converters. This operation
requires both the primary and secondary side static converters to operate synchronously, which is
accomplished by modulating the switches by a high-frequency square wave with 50% duty ratio.
Because the transformer voltage contains only high-frequency AC components, the resulting
core size is small compared to that designed for 60-Hz operations.
Even though this concept avoids stress factors and isolation concerns, one problem with this
topology is the component count and associated reliability issues. The static ac/ac converters in
these topologies employ bi-directional switches, which are realized by pairs of low-voltage
IGBTs connected in series. To interface with primary input voltage that can be as high as 35 kV,
the component count for semiconductor switches based on a suggested design using LV
modules/devices will make it very difficult to achieve the desired reliability goals. Furthermore,
this design does not provide any benefits in terms of power-factor improvement and control.
In recent literature [10], a circuit was proposed to combine multiple stages of ac/dc, dc/dc, and
dc/ac with a high-frequency transformer as a module and to connect the module input in series so
that the circuit could be tied to distribution voltage level with low-voltage silicon devices. The
proposed system structure consists of connecting the input of several modules in series and the
output of these modules in parallel. The main purpose of stacking several low-voltage
semiconductor devices is to allow a high-voltage input that can be tied to distribution voltage
level and to have a low-voltage output that can be used for commercial and residential. The input
of these multiple solid-state building blocks or modules is low-frequency, high-voltage ac, and
the output is a low-voltage ac with the same frequency. The power conversion is equivalent to a
step-down transformer except that the power flow is single directional.
While such designs have some advantages (such as harmonic elimination, transformer isolation,
and reduction in size of magnetic materials), there are several drawbacks as well. For example,
one problem inherent in such designs is the difficulty of ensuring that the input voltages balance
among the different modules in the system structure. With device mismatching and without any
active control, the input voltages among the different modules are unlikely to be maintained at
1-21

Introduction
the same voltage level. One solution may be to add a set of voltage-balancing zener diodes, metal
oxide varistors (MOVs), or other passive voltage-clamping methods. However, a typical passive
voltage-balancing element or clamping circuit consumes a large amount of power and is not
practical in high-power applications.
To overcome voltage-sharing problem for series-connected devices or converter stacks, several
advanced multilevel converter circuit topologies have been proposed [5, 6, 11]. By incorporating
advanced multi-level converters with the use of high-voltage (HV) IGBTs [12], it is possible to
develop power converters for distribution applications.
The 2002 report [11] provided an in-depth literature review of the existing and emerging designs
that employ modern solid-state switching technologies in their design. Two possible approaches
for realizing the goal of an intelligent universal transformer (IUT), the hybrid design and the
all-solid-state design were identified in this report, as shown in Figure 1-11. For each
technology, the report provides a brief overview of the working principle, proposed circuit
topologies and configurations, potential application areas, possible price ranges, pros and cons of
the proposed designs, and, most importantly, the maturity of both technologies.
A
Transformer
secondary
Inverter
A1
C1
B1
Inverter
Inverter
Schematic for CONVENTIONAL

TRANSFORMER
C
Schematic for HYBRID TRANSFORMER
Inv
e
ert
v
n
I
er
ert
r
rte
e
v
In
Inverter
In
ter
r
e
v
Inv
e
rte
r
Schematic for ALL SOLID-STATE

TRANSFORMER
Figure 1-11
Simplified Schematic for Power Electronics-Based Transformer Design
1-22

Introduction
The hybrid design is based on the integration of a conventional transformer with power
electronics only on the secondary side of the transformer. The hybrid transformer is not just
connecting two or more separate products but also actually integrating the functionalities within
the framework of a single system. This is the major technological difference between such
designs as compared to some of the existing medium-voltage power-conditioning devices
presently available in the market. The hybrid designs have the advantage over conventional
transformers in that they can provide not only the traditional ac service, but also virtually
whatever service the customer desires (high-frequency ac, dc power, sag protection, harmonic
filtering, ability to convert single-phase service to three-phase for powering certain types of
equipment, and so on). The drawback is that operational benefits, such as standardized
transformer designs, reduced weight and size, and oil-free environment, cannot be realized from
this approach.
The all-solid-state design, on the other hand, provides a fundamentally different and more
complete approach in transformer design by using power electronics on the primary and
secondary sides of the transformer. The power electronics on the primary side of the transformer
provide a high-voltage interface with the utility ac system, and the power electronics on the
secondary side of the transformer provide a low-voltage interface with consumer applications.
All-solid-state (electronic) transformer technology can provide control over the shape and
amplitude of output voltage waveforms and can, therefore, address many power quality
problems. Electronic transformer designs can solve some shortcomings found in conventional
transformer technology, such as voltage drop under increasing load, flat-topped voltage under
saturation, harmonic sensitivity, containment requirements for oil spill, limited performance
under dc offset load unbalances, providing options for high-frequency ac, ability to convert
single-phase service to three-phase for powering certain types of equipment, providing reactive
compensation, and so on. In addition, this technology has the potential to lend itself to
standardization of distribution transformers and to achieving other operational benefits, such as
reduced weight and size and reduced environmental concerns (that is, by eliminating oil in the
transformer).
However, all new products face barriers to entry, particularly when competing with
entrenched, mature technologies. The disadvantages of the all-solid-state based IUT
technology include:

Higher EMI than conventional transformer.
1-23

Introduction
Window of Opportunity for All-Solid-State Transformer Designs Using HV, LowCurrent Power Electronic Switches
It is noteworthy to mention here that these power electronics-based transformer designs are in the
early stages of development and are not commercially available. However, based on the
preliminary results [11] and on-going research in this area, all-solid-state IUT technologies have
the potential to offer myriad advantages that prospective purchasers may find attractive and
could make them successful in the marketplace. The 2002 report [11] determined that an all
solid-state design for a distribution transformer could provide a fundamentally different and more
complete approach in transformer design. Also, it was identified that use of HV power
electronics in designing the primary side of an all-solid-state transformer offers significant
advantage in reliability and cost over low-voltage (LV) designs.
There has been tremendous advancement in HV power electronics devices in the past several
years, primarily led by high-power (HP) applications for traction and Flexible AC Transmission
System (FACTS) devices. These application areas have used HV and HP switches. While HV,
HP power semiconductor devices can certainly be used in IUT applications, development and
use in the IUT of a HV, LP power semiconductor switch offers significant cost advantage that is
critical for successful market entry of IUT. Currently, HV, HP power electronics devices such as
1
2
3
gate turn-off thyristors (GTOs) , IGBTs , integrated gate commuted thyristors (IGCTs) , and
4
emitter turn-off thyristors (ETOs) are available at the 6-kV level. R&D work is being conducted
for achieving the holy grail of higher switching speed, lower losses, and increased reliability
using either IGBT, GTO, ETO, IGCT, or other technologies. Moreover, industry and other
consortia in the field of SiC and diamond are also conducting considerable research work in this
field. These high-voltage, high-power power electronics, once they mature, will result in a
significant reduction in the overall cost of solid-state designs.
Typically, power electronics researchers have to choose off-the-shelf power devices with the
specifications that best fit their applications. They usually do not have a say about how they
would like the device parameters to be changed. On the other hand, materials and device
researchers build switching devices for the power electronics researchers to use in their circuits,
but they rarely know how and where the devices are going to be used. As represented in Figure
1-12, a barrier exists between the people who design and build power devices and the people
who use them in their circuits and systems. Close interaction between the both sides of the
barrier is needed to obtain the most performance for devices and systems. With this interaction,
the design loop will be closed and the possibility for building optimal application-specific power
devices will arise.
A companion EPRI report, titled Feasibility Study Development of High Voltage, Low Current
Power Semiconductor Devices, lays the foundation for EPRIs HV, LP solid-state electronics
program and includes the following information:
Gate turn-off thyristors. The capacity of the state-of-the-art GTO device has reached 6 kV and 6000 A.
Insulated gate bipolar transistors. Today, 1.2-kV, 1.7-kV, 2.5-kV, 3.3-kV, and 6.5-kV, 600-A IGBTs are
commercially available.
3
Integrated gate commuted thyristors. These have reached the same power level as that of the GTOs.
4
Emitter turn-off thyristors. These have reached the same power level as that of the GTOs.
2
1-24

Introduction
A comprehensive set of functional requirements for a range of HV, LP switches and diodes
that can be used in an IUT
Existing and emerging power semiconductor switches to these functional requirements
Evaluation of the suitability of silicon and wide-band-gap semiconductor technology for HV,
LP switches
Possible technology options for development of HV, LP switches and the prospects and risks
for the various options
An R&D roadmap for EPRIs HV, LP solid-state program

Circuit Design,
Develop Functional Specifications,
Develop Hardware Requirements,
Define Physical layout and Package Requirements
Bench Model Development

Fabrication, & Testing
Si/SiC Processing
Device Design,
Fabrication, & Testing
Basic R&D for Power Semiconductor Devices

Research Activities should focus on possible
improvements in technology
Reduce conduction and switching losses
Faster switching
Improvement in efficiencies
Improvement in short-circuit capability
Improvement in thermal management to
handle high temperature
Reduce possible voltage balancing
Reduce EMI Levels
Optimize isolation designs to satisfy HV
applications
Low saturation level
Improved Gate design to reduce
noiseSnubber-less operation
Fast turn-on and turn-off capabilities
Ability to withstand high V&I
Improvement in current density
Figure 1-12
Closing the Device Design Loop A Key for Building Optimal Application-Specific Power
Devices
Organization of the Report

This report is organized into 6 sections:
Section 2 provides a brief overview of the circuit topology and working principles of the
proposed multi-level converter-based IUT system. The section includes a comprehensive design
analysis of all active and passive elements that are used in the power stages: active front-end
ac/dc multilevel converter, dc/dc multilevel half-bridge converter, and dc/ac inverter based on a
certain kVA and input/output voltage range. These include specifications and selection of duty
cycles modulation strategy, dc bus capacitor voltage level, size of the dc capacitor, size of the
1-25

Introduction
boost inductor, high-frequency transformer, output filter designs, and so on. AutoCAD drawings
of the physical layouts of the proposed IUT system are also presented in this section.
Section 3 provides details of the power electronics circuits and the associated open-loop and
closed-loop controller designs for the proposed multi-level converter-based IUT. Modeling
and simulation results of the active front-end ac/dc multilevel converter, dc/dc multilevel halfbridge converter, and dc/ac inverter are included. To ensure voltage balancing between the highside dc capacitors, performance verification of the proposed intelligent pulse-width-modulation
(PWM) technique is also presented. Also provided is the performance evaluation of the complete
IUT system with respect to its ability to meet the desired functionalities that were earlier
addressed in the generic functional specification for a desired sophisticated transformer, which
includes voltage sag compensation, instantaneous voltage regulation, outage compensation,
capacitor-switching protection, harmonic compensation, single-phasing protection, DC output,
and 400-Hz output.
Section 4 provides results of an in-depth reliability assessment of the proposed IUT system using
an industry standard reliability calculation method. MIL-HDBK-217F is a most commonly used
method for reliability prediction of electronic equipment. The different input parameters that are
required to perform a reliability assessment of the proposed design are provided. The chapter
also provides a detailed reliability assessment of a design proposed by S. Sudhoff et al. [10, 13,
7] and compares it with the proposed multi-level converter-based IUT system.
Section 5 provides the overall cost estimates of the proposed IUT system based on existing
component costs and estimated component costs. Complete listings of all parts, including
potential vendors, and its associated costs for the associated printed circuit boards (PCBs), are
also provided. These include: (1) Active-Front-End (AFE) power circuit, (2) HV gate drive
circuit, (3) gate drive interface circuit, (4) sensor conditioning circuit, (5) inverter circuit, and (6)
Digital-Signal-Processing (DSP) board.
Finally, Section 6 provides a technology roadmap for the next-generation transformers. This
chapter provides the rationale for the roadmap based on the technical- and market-potential
assessments; a prioritization of universal transformer design based on customer need, design
evaluation, cost, and functionality requirement; maturity of high-voltage power electronic
devices; and research and development recommendation (long-term as well as short-term) for
developing a prototype unit.
1-26
2
DESIGN OF THE POWER STAGE
By incorporating advanced multi-level converters with the use of high-voltage (HV) IGBTs, it is
possible to develop power converters for distribution applications. This section provides a brief
overview of the circuit topology and working principles of the proposed multi-level converterbased IUT system. It includes a comprehensive design analysis of all active and passive elements
that are used in the power stages: active front-end ac/dc multilevel converter, dc/dc multilevel
half-bridge converter, dc/ac inverter-based, and a certain kVA and input/output voltage range.
These include specifications and selection of duty cycles, modulation strategy, dc bus capacitor
voltage level, size of the dc capacitor, size of the boost inductor, high-frequency transformer,
output filter designs, and so on. Physical layouts of the complete multi-level converter-based
IUT system are also presented in this chapter.
There are three basic multilevel converter circuit topologies [14, 15], namely (1) diode-clamped,
(2) capacitor-clamped, and (3) cascade inverter. Although the cascade inverter type has been
considered as the most promising multilevel converter topology for high-voltage, high-power
applications, to use it for IUT is nontrivial because it requires numerous isolated dc sources. The
diode-clamped and capacitor-clamped multilevel converters are likely to be the candidate for
distribution-level solid-state transformer applications. When taking the dynamic voltage
balancing among different levels into account, the diode-clamped multilevel converter is a better
candidate and is chosen for the initial power stage design.
2.1 Basic Principle of Diode-Clamp Multilevel Converter

A three-level diode-clamped inverter is shown in Figure 2-1(a). In this circuit, the dc bus voltage
is split into three levels by two series-connected bulk capacitors, C1 and C2. The middle point of
the two capacitors, n, can be defined as the neutral point. The output voltage, van, has three states:
Vdc/2, 0, and Vdc/2. For voltage level Vdc/2, switches S1 and S2 need to be turned on; for Vdc/2,
switches S1 and S2 need to be turned on; and for the 0 level, S2 and S1 need to be turned on.
The key components that distinguish this circuit from a conventional two-level inverter are D1
and D1. These two diodes clamp the switch voltage to half the level of the dc bus voltage. When
both S1 and S2 turn on, the voltage across a and 0 is Vdcthat is, va0 = Vdc. In this case, D1
balances out the voltage sharing between S1 and S2, with S1 blocking the voltage across C1 and
S2 blocking the voltage across C2. Notice that output voltage van is ac, and va0 is dc. The
difference between van and va0 is the voltage across C2, which is Vdc/2. If the output is moved to
between a and 0, then the circuit becomes a dc/dc converter, which has three output voltage
levels: Vdc, Vdc/2, and 0.
2-1

Design of the Power Stage
Figure 2-1(b) shows a five-level diode-clamped converter in which the dc bus consists of four
capacitors, C1, C2, C3, and C4. For dc bus voltage Vdc, the voltage across each capacitor is Vdc/4,
and each device voltage stress will be limited to one capacitor voltage level, Vdc/4, through
clamping diodes. Four complementary switch pairs exist in each phase. The complementary
switch pair is defined such that turning on one of the switches will exclude the other from being
turned on. In this example, the four complementary pairs are (S1, S1), (S2, S2), (S3, S3), and (S4,
S4).
Vdc
2
Vdc
2
C1
Vdc
S1
D1
van
S2
Vdc
D1
C3
V
dc
4
C4
S1
C2
S2
V dc
2
(a)
S2
D1
D1
S3
D2
D3
C1
Vdc
4
C2
S1
S4
van
a
S1
S2
D2
D3
V dc
2
S3
S4
(b)
Figure 2-1
Multilevel Diode-Clamped Converters: (a) Three-Level and (b) Five-Level
Although each active switching device is only required to block a voltage level of Vdc/(m1), the
clamping diodes must have different voltage ratings for reverse voltage blocking. Using D1 of
Figure 2-1(b) as an example, when lower devices S2~S4 are turned on, D1 needs to block three
capacitor voltages, or 3Vdc/4. Similarly, D2 and D2 need to block 2Vdc/4, and Da3 needs to block
3Vdc/4. Assuming that each blocking diode voltage rating is the same as the active device voltage
rating, the number of diodes required for each phase will be (m1)(m2). This number
represents a quadratic increase in terms of m. When m is sufficiently high, the number of diodes
required will make the system impractical to implement. If the inverter runs under PWM, the
diode reverse recovery of these clamping diodes becomes the major design challenge in highvoltage, high-power applications. Thus, it is preferred to have a lower-level system to avoid
potential problems caused by the clamping diodes.
The multilevel converter allows the input directly connecting to the distribution voltage level
with the use of existing high-voltage silicon IGBT devices. The proposed circuit consists of a set
of back-to-back interconnected multilevel converters, a high-frequency transformer, and a dc/ac
inverter. The input can be tied to high-voltage distribution system, and the output can be tied to
low-voltage household applications. As compared to the conventional copper-and-iron based
2-2

transformer, the proposed multilevel solid-state transformer not only reduces the size but also
enhances the power quality performance and increases the functionality.
Figure 2-2 shows the complete circuit configuration of a multilevel IUT. Here the high-voltage
insulated-gate-bipolar-junction-transistor (HV-IGBT) can be used as the switching device.
Switches SA1, SA2, SA1, SA2, SB1, SB2, SB1, SB2 constitute a multilevel full-bridge dc/dc converter that
takes ac voltage as the input and produces a dc voltage output. HV-IGBT switches Sa1, Sa2, Sa1,
Sa2, Sb1, Sb2, Sb1, Sb2 constitute a multilevel full-bridge dc/ac inverter that takes the dc bus voltage
and converts it to a high-frequency ac. Notice that for phase-a and -b, the voltage between a and
n or b and n is a three-level ac. However, the line-to-line voltage vab has a total of five levels.
HV-IGBT based M-level diode-clamp converter
Vdc
2
SA1
SB1
C1
SA2
SB2
high
side
Sa1
Sb1
Sa2
Sb2
SA2
SB2
Lf
Cdc
B
SB1
Ldc
SA1
b
C2
Sa1
Sb1
Sa2
Sb2
V dc
2
Cf
low
side
High-frequency
transformer
Figure 2-2
Complete Circuit Diagram of a Three-Level IUT
In order to reduce the amount of high-voltage semiconductor devices, it is possible to tie the
input from line to neutral and tie the neutral to the middle point of the capacitor stack. As a
result, the front-end converter becomes a half-bridge converter. Figure 2-3 shows the circuit
diagram of using a half-bridge-based three-level IUT. Here, the second stage dc/ac inverter is
also a half-bridge three-level inverter. The total number of high-voltage devices used in Figure
2-3 is only half of what has been used in Figure 2-2. For a system with 13.8-kV line-to-line
voltage, the line-to-neutral voltage is 8 kV, and its peak voltage is 11.3 kV.
2-3

Vdc/2
Lf
Sa1
Sb1
Sa2
Sb2
8 kVrms
11.3 kVpk
Sa1
Sb1
Sa2
Sb2
Vdc/2
Figure 2-3
Half-Bridge-Based Three-Level IUT
The problem with the circuit shown in Figure 2-3 is that the voltage stress across the device is
twice. If both upper switches, Sa1 and Sa2, are turned on, then the upper capacitor sees Vdc/2, which
is at least the peak ac input voltage, or 11.3 kV. With the three-level circuit structure, the HVIGBT needs to switch at least 11.3 kV. For the utility environment, the device needs to have a
voltage blocking level more than twice the switching voltage. In other words, the device needs to
be rated with a blocking voltage of 22.6 kV or higher. Unfortunately, the modern semiconductor
device technology has not been able to reach this blocking voltage level, and thus a circuit with
lower blocking voltage level is more desirable.
In order to allow the use of semiconductor devices with a lower voltage blocking-level, while
reducing the amount of semiconductor devices, a compromise of using full-bridge three-level
dc/dc converter and a half-bridge three-level dc/ac inverter is proposed. The complete circuit
diagram of the proposed IUT (three-level as well as five-level design) is shown in Figure 2-4. In
this circuit, the line-to-neutral voltage of 8 kV (in rms) is tied to a three-level full-bridge dc/dc
converter. When diagonal switches Sa1, Sa2, Sb3, and Sb4 are turned on, the voltage across both
capacitors, or Vdc, is slightly higher than the peak voltage of 11.3 kV. The difference between Vdc
and the peak ac voltage is the inductor voltage. The circuit diagram indicates a total of 13.2 kV,
or 6.6 kV across each capacitor. This means that the semiconductor devices need to switch at 6.6
kV level. With double voltage blocking requirement, a 13.2 kV device will be adequate. This
voltage level may be achievable with new silicon carbide (SiC) devices in a foreseeable future.
2-4

6.6kV
8 kVrms
11.3 kVpk
Lf i
a
Sa1
Sb1
Sc1
C1
Sa2
Lo
Sb2
Sc2
Lac
vin
Sa3
Sb3
Sa4
Sb4
Co
Cac
Sc3
C2
Sc4
6.6kV
A 3-Level Scheme
6.6 kV
Sr11
Sr21
Si1
Sr12
Sr22
Si2
Sr13
Sr23
Si3
Lf Sr14
Sr24
Si4
120V
400 Hz
8 kV
16.6 kVA
120/240 V
60 Hz
Sr11
Sr21
Si1
Sr12
Sr22
Si2
Sr13
Sr23
Si3
Sr14
Sr24
Si4
1r
-6.6 kV
5
3
4
Isolated
DC/DC
converter
+
48 Vdc
_
1i
A 5-Level Scheme
Figure 2-4
Combination With Full-bridge 3/5-Level Converter and Half-Bridge 3/5-Level Inverter That
Allows the Use of Semiconductor Devices With a Lower Voltage Blocking Level
2.2 Design Calculation for the Front-End AC/DC Multilevel Converter

Major components in the front-end ac/dc converter that need to be calculated and designed are:
(1) the dc bus voltage level, Vdc, (2) the dc bus capacitors, C1 and C2, and (3) the boost inductor,
Lf.
2-5

A. Selection of DC Bus Capacitor Voltage Level

The dc bus capacitor voltage level can be selected based on different modulation schemes. With
sinusoidal pulse-width-modulation (SPWM), the dc bus capacitor voltage should be higher than
the peak ac input phase voltage to allow a voltage drop across the inductor. The switching
current ripple is a function of the filter inductance and the difference between the input source
voltage, vin, and the dc bus voltage, Vdc. Eqs. 2-1 through 2-4 express the inductor current changes
as a function of switch turn-on combinations.
dia vin Vdc

=
dt
Lf
when Sa1, Sa2, Sb3, Sb4 are on
dia
v V
= in dc
dt
Lf
dia vin
=
dt L f
when Sa3, Sa4, Sb1, Sb2 are on
when Sa3, Sb2 are on
dia
v
= in
dt
Lf
when Sa2, Sb3 are on
Eq. 2-1
Eq. 2-2
Eq. 2-3
Eq. 2-4
Notice that Vdc is selectable as long as it is higher than the peak input voltage. Lowering Vdc gives
smaller ripple. However, if Vdc is dropped too low, then the input current waveform may not be
shaped to sinusoidal. In general, Vdc needs to be 10 to 15% higher than the peak input voltage.
Theoretically, Vdc can be formulated using the input voltage and the converter modulation index.
The input line-to-neutral voltage va0(t) is a sinusoidal function of the peak input voltage Vm, i.e.,
va0(t) = Vm sin(t). The upper switch duty cycle can be expressed as da0(t) = Dm sin(t). Here Dm is
the modulation index, and da0(t) is the upper switch duty cycle as a function of time. The line-toneutral voltage can then be expressed as a function of the duty cycle da0(t) and the dc bus voltage,
Vdc, as shown in Eq. 2-5.
va0(t) = da0(t) Vdc
Eq. 2-5
By substituting sinusoidal functions into the voltage and duty cycle in Eq. 2-5Vm sin(t) = Dm
Vd sin(t)we have dc bus voltage as a function of the input ac peak voltage Vm and the
modulation index Dm, as shown in Eq. 2-6.
Vd =
Vm
Dm
Eq. 2-6
Consider a three-phase, 13.8 kV system. If the modulation index is limited to 0.85, then the dc
bus voltage Vdc becomes:
Vm = 13.8/1.732 1.414 = 11.3 kV
2-6

Vdc = Vm/Dm = 13.2 kV

Although the theoretical maximum modulation index is 1, a value less than 1 allows a voltage
margin for better input current waveform shaping and more reactive power flow control margin.
B. Size of DC Bus Capacitor
The size of dc bus capacitor depends on the magnitude of ripple voltage and capacitor current.
When the filter current is positive, the capacitor is charged. When the filter current is negative,
the capacitor is discharged. The charging frequency is apparently twice the line frequency.
Assume that the charging time is the same as discharging time. This may not be accurate, but it
serves as a good starting point. With charge and discharge balance, we have
I a rms t = Cd Vdc
C1 = C2 = Cd =
I arms t
I
= arms
Vd
2 f r Vdc
Eq. 2-7
Eq. 2-8
Here, t is one half of the 120-Hz cycle, or 4.17 ms, and Ia-rms is the rms value of Ia for the 4.17ms period. The total capacitor value needs to be divided by 2 because there are two capacitors in
series. Assume that Ia-rms = 2 A and fr = 120 Hz. If the voltage peak-to-peak ripple is limited to
330 V (2.5% of 13.2 kV), then Cd = 26 F.
C. Size of Boost Inductor
The size of boost inductor depends on the switching frequency, current ripple, and the difference
between the source voltage and the dc bus voltage. For a three-level converter, the equivalent
switching frequency is twice the switching frequency, and the inductor size can be determined by
the following equations.
dia vin Vdc
=
dt
Lf
L f = Dm
Vm Vdc
2 f sw ia
Eq. 2-9
Eq. 2-10
Higher switching frequency means a smaller inductor can be used. For the above example, let ia
= 0.2 Apk-to-pk, or 10% of the rms current and fsw = 10 kHz. With a voltage difference of 13200
11300 = 1900 V and a modulation index of 1, the inductance can be calculated as Lf = 475 mH.
Notice that this inductance value is high, but its current is relatively small. If the ripple current
specification is released to 20%, then the inductance value can be reduced to half the calculated
value. The tradeoff is between the ripple current and the inductor size.
The selected inductor and capacitor values have been used in the computer simulation with 8-kV
input, 13.2-kV dc bus voltage. Under overloaded condition, the simulated input current is 2.83 A
2-7

rms, and the maximum duty cycles is 0.86. This should translate to Vdc = 453 V and iL = 0.172
A. The simulation results, shown in Figure 2-5 and Figure 2-6, indicate that Vdc = 450 V and iL
= 0.17 A. Both agree with the calculation very well.
13.5k
vdc (V)
13.2k
13k
12.8k
450V
12.5k
5 50m 55m
60m
65m
70m
75m
80m
85m
90m
95m
0.1 t
70m
75m
80m
85m
90m
95m
0.1 t
iLf (A)
2
0
-2
-5
50m 55m
60m
65m
Figure 2-5
Simulated DC Bus Capacitor Voltage and Boost Inductor Current in Three Line Cycles
4.3
4
3.85
3.7
3.5
iLf (A)
0.17Apk-pk
86m 86.2m 86.4m 86.6m 86.8m
87m
87.2m 87.4m 87.6m 87.8m 88m t
Figure 2-6
Zoomed-in Simulated Line Current to Show the Inductor Ripple Content
2.3 Design Calculation for the DC/DC Multilevel Half-Bridge Converter

As shown in Figure 2-4, major components that need to be calculated and designed for the dc/dc
multilevel half-bridge converter are (1) the high-frequency transformer, (2) the dc output filter
inductor, Lo, and (3) the dc output filter capacitor, Co.
A. Transformer Design
Assuming that the maximum duty cycle achievable is 90%, with output 410 V and input 6600 V
(high line) or 6000 V (low line), the turns ratio needs to be <14.6:1. Choose n = 14 for a
conservative design. The core selection can be based on the area product requirement, as shown
in Eq. 2-11.
2-8

Ap =
16.6 103 108

Po 108
=
= 92 cm 4
4 J c Bmax f s ku 4 300 2500 20000 0.3
Eq. 2-11
where
Ap = area product = core window area effective area, cm4
Po = output power, W
Jc = copper current density, A/cm2
Bmax = maximum flux density, Gauss
fs = switching frequency, assume to be 20 kHz
ku = core utilization factor
Off-the-shelf ferrite cores are normally available in relatively lower power levels. For the abovementioned 16.6-kW transformer, it is necessary to utilize two sets of transformer cores if the off-theshelf cores are used. Figure 2-7 shows physical size of the selected planar E102 transformer cores.
10.2cm
4.0cm
3.75cm
Figure 2-7
Physical Size of the Transformer Cores
B. Output Filter Capacitor Design

The output power is 16.6 kW at 240 V or 8.33 kW at two split 120 V. Thus the ac output current
is 69.2 A, or 100 A peak. The output filter capacitor needs to handle 120-Hz ripple current
generated from the next-stage inverter. Assume that a 20-A current ripple or 20% of 100 A
comes from the next stage inverter. To limit the capacitor voltage ripple to 2.5%, the capacitance
for each dc bus can be calculated as:
Co =
I
20
=
= 4.1 mF
8 f V 8 120 205 0.025
Eq. 2-12
Here we assume the output stage inverter has a dc bus voltage of 205 V, which corresponds to a
modulation index of 0.83. Because the commercial off-the-shelf capacitors are limited to certain values,
the 250-V, 4.7-mF capacitors are selected in this case. Another factor for sizing the capacitor is to
consider for the momentary outage. Assume that the converter trips at 150 Vdc bus voltage. The total
energy stored in capacitor from 205 V to the trip point of 150 V is 4.7103(20521502)/2 = 46 J. For a
8.3-kW output, the trip time will be 5.5 ms, or 1/3 cycle. If the design is to have at least one cycle of
energy backup, then the total capacitance needs to be 14.1 mF.
2-9

C. Output Filter Inductor Design

The rectifier output inductor current ripple is caused by the difference between the transformer
secondary output rectified voltage, Vd, and the dc output capacitor voltage, Vo. Higher voltage
difference means higher inductor current ripple. It is also a function of the switching frequency.
Figure 2-8 shows the rectifier output inductor ripple and its relationship with the voltage
difference and switching frequency.
Vd=471
Vo=410
IL=100Apk
50 s
45 s
Figure 2-8
Rectifier Output Inductor Current Ripple
By assuming 20% inductor ripple and 90% maximum duty cycle, the inductance can be
calculated as shown in Eq. 2-13.
Lo =
V
6600 / 28 205
t =
45 10 6 = 138 H
i
50 0.20
Eq. 2-13
The above power component design has been simulated to verify the ripple current calculation.
Figure 2-9 shows the simulation diagram for the three-level dc/dc converter with two split dc outputs.
The two input voltages E1 and E2 come from the active front-end ac/dc converter with 6.6 kV each.
RL1
pwm1
PWM
S1
D1
28:1
D7
Tr1
126 H
138 uH
D8
+
TWT
E1
D5 PULSE1 S2
D2
L1 = 784mH
L2 = 1mH
k = 0.9988
D9
L1
VM1
C1
4.7 mF
R1
5
D10
+
RL2
D6 PULSE2 S3
D3
28:1
D11
D12
L2
VM2
126 H
138
uH
Tr2
TWT
E2
pwm2
PWM
S4
D4
L1 = 784mH
L2 = 1mH
k = 0.9985
D13
Figure 2-9
Simulation Diagram of the Three-Level DC/DC Converter
2-10
D14
C2
R2
4.7 mF

The switches are PWM with a fixed duty cycle to produce a quasi-square wave across the
transformer primary. Figure 2-10 shows the control signals for all four switches. The middle
switches S2 and S3 are turned on 50% time per switching cycle. The outer switches S1 and S4 are
turned on with 45% time per switching cycle. Overall, the duty cycle is equivalent to 90%.
1.2
0.8
pwm1.val
DS1 = 0.45
0.4
-0.2
1.2 0
0.8
0.1m
0.2m
0.3m
0.4m
0.5m
0.6m
0.7m
0.8m
0.9m 1m t pwm2.val
[s]
DS4 = 0.45
0.4
-0.2
1.2 0
0.5
0
-0.5
-1.2
1.2 0
0.1m
0.2m
0.3m
0.4m
0.5m
0.6m
0.7m
0.8m
0.9m 1m t PULSE1.VA
[s]
DS2 = 0.5
0.1m
0.2m
0.3m
0.4m
0.5m
0.6m
0.7m
0.8m
0.5
0
-0.5
-1.2
0.9m 1m t PULSE2.VA
[s]
DS3 = 0.5
0
0.1m
0.2m
0.3m
0.4m
0.5m
0.6m
0.7m
0.8m
0.9m 1m t [s]
Figure 2-10
Switch Control Signals for the Three-Level DC/DC Converter
Figure 2-11 shows the simulated transformer primary voltage and secondary output voltage
before and after the filter inductor. The primary input voltage is a 10 kHz quasi square wave with
6.6 kV peak. The reflected secondary voltage is rectified to Vd with 20-kHz pulses and peaking at
236 V. The difference between Vd and the output voltage Vo creates the inductor current ripple, as
shown in Figure 2-12. The simulated inductor current has 10-A peak-to-peak ripple, which
agrees with the calculation very well.
Figure 2-11
Transformer Primary Voltage and Secondary Output Voltage Before and After the Filter
Inductor
2-11

Figure 2-12
Output Filter Capacitor Voltage and Inductor Current Waveforms
2.3 Design Calculation for the DC/AC Inverter Output Filters

Figure 2-13 shows the dc/ac inverter with split outputs. The input of the inverter is from the
previous-stage dc/dc converter split outputs, Vo1 and Vo2. The output of a dc/ac inverter before
filtering is a chopped square wave with significant harmonic contents around the switching
frequency or twice the switching frequency. These harmonics need to be filtered with high-order
passive filters. For cost consideration, the filter design is typically to have second-order inductorcapacitor (LC) components to clean the inverter output waveform. Thus, the components that
need to be calculated and designed are: (1) filter inductor, Lac, and (2) filter capacitor, Cac.
Q1
Co
Vo1
Q3
Lac-1
Cac-1 vac1
Vo
Lac-2
Q2
Vo2
Cac-2 vac2
vac
Q4
Figure 2-13
The DC/AC Inverter With Split Outputs
The inverter is operating with sinusoidal PWM operation at a carrier frequency of fs. The basic
operating principle of SPWM method is to compare a reference sinusoidal voltage Vref and a
triangular carrier wave vc. The reference voltage has a frequency equal to the line frequency f0,
and the carrier wave has a frequency equal to the switching frequency fs. When Vref is higher than
vc, then switches Q1 and Q4 are turned on, or duty cycle dab = 1. When Vref is lower than vc, then
switches Q2 and Q3 are turned on, or duty cycle dab = 0. The average duty cycle of dab(t) is a
sinusoidal function, or
2-12

dab = Dm sin 0t
Eq. 2-14
Here, Dm is the modulation index, and 0 is the line frequency in rad/s. The resulting average
output voltage becomes dabVo = DmVo sin t.
Figure 2-14
Sinusoidal PWM Method
Figure 2-15 shows the 20-kHz switched inverter output voltage before and after filtering. The
output of the inverter before filtering is a chopped square wave. Its harmonic contents are
analyzed and shown in Figure 2-16. It can be seen that with the fundamental voltage magnitude
of 170 V at the line frequency, the most significant harmonic is about 160 V at the switching
frequency of 20 kHz. The side-band frequencies (19.88 kHz and 20.12 kHz) also indicate
significant harmonic contents with a magnitude of 50 V. This chopped square waveform requires
substantial filtering effort to attenuate the high harmonic content.
0.3k
Vm1 (V)
0.1k
0
-0.1k
-0.3k
5m
10m
16m
Time (s)
Figure 2-15
Inverter Output Voltage Before and After Filtering
2-13
f (Hz)
14
06
0
0
14
01
2
0
13
96
4
0
12
04
2
0
11
99
4
94
6
11
01
2
64
0
10
99
18
0
80
70
0
12
0
79
60
64
0
59
94
0
39
20
12
0
350
300
250
200
150
100
50
0
60
Vm1 (V)
Figure 2-16
Harmonic Contents of the Inverter Output Voltage Before Filtering
It should be noticed that the two phase legs of the full-bridge inverter can be individually
modulated to reduce the harmonic contents. The method is called dual modulation method.
Here, phase-a switches Q1 and Q2 are controlled by duty cycle da, which is similar to the
abovementioned dab. However, phase-b switches Q3 and Q4 are control by another duty cycle db,
which has the same carrier wave but with an opposite sinusoidal wave.
Figure 2-17
Dual Modulation Method With Two Sets of Duty Cycles da and db
The mathematical formulation of dual modulation method can be summarized as follows:

da = duty cycle of switch S1, average(da) = 0.5(1 + Dm sint) , 0 < da < 1
db = duty cycle of switch S3, average (db) = 0.5(1 + Dm sin(t 180)), 0 < db < 1
va0 = phase a to negative dc bus voltage = daVo = 0.5Vo (1 + Dm sint)
2-14

vb0 = phase b to negative dc bus voltage = dbVo = 0.5Vo(1 + Dm sin(t 180)),

vab = va0 vb0 = Vo(da db) = Vo(Dm sint) same as the case with single modulation
Figure 2-18 shows the inverter output voltage with the dual modulation method. The chopped
square wave swings only from dc bus voltage down to zero or from zero down to negative dc bus
voltage, but not between positive dc bus voltage and negative dc bus voltage. Figure 2-19 shows
the harmonic analysis results for the dual modulated inverter output voltage before filtering. Here
the most significant harmonic contents are the line frequency f0 around the twice the switching
frequency fs, or fsf0. For the output magnitude of 340 V at the line frequency, the most
significant harmonic content is 120 V at fs+f0 tand fsf0. The filtering effort with such a dual
modulation method is much easier than that with the conventional sinusoidal PWM method.
Vm2 (V)
0.5k
Vm2
0.2k
0
-0.2k
-0.5k
5m
10m
16m
Time (s)
f (Hz)
24
04
2
0
23
98
2
0
23
91
0
0
20
06
6
0
19
95
8
0
16
06
6
0
16
01
8
0
15
97
0
0
12
05
4
00
6
12
95
8
18
0
11
70
0
80
79
40
06
0
350
300
250
200
150
100
50
0
60
Vm2 (V)
Figure 2-18
Inverter Output Voltage With Dual Modulation Method
Figure 2-19
Harmonic Contents of the Dual Modulated Inverter Output Voltage Before Filtering
When designing the inverter output filter, it is necessary to decide the filter cutoff frequency fc
and the order of the filter. The cutoff frequency needs to be low enough to ensure a clean
sinusoidal ac output voltage. Given the switching frequency of fs, the filter cutoff frequency, fc,
can be determined as a function of the order of the filter, n. The following equation expresses the
relationship using an nth order Butterworth filter for attenuation of the db value dbr.
fc =
10
s
dbr / ( 20 n )
Eq. 2-15
2-15

Assume that the line frequency is 60 Hz, switching frequency fs is 20 kHz, dc bus voltage is 410
V, and the ac output peak voltage is 170 V for 120 Vrms and 340 V for 240 Vrms. Consider for
the most significant harmonic content of 160-V content at 20 kHz. It is necessary to attenuate
such a harmonic at least 100 times (or 40 dbr). With a conventional second-order LC filter, the
filter cutoff frequency can be determined in Eq. 2-15.
fc =
2 20000
= 4 kHz
10 40 / (202 )
Eq. 2-16
A. Determine Inverter Output Filter Inductor

It is known that the inverter switching duty cycle is 50% at the zero-crossing region. If the
inductor current ripple is determined to be at a certain percentage, then the inductor value can be
calculated accordingly. Here, assume that 30% of the inductor current ripple is allowable at the
zero-crossing region. The inductance can be calculated as:
L=
V
205
t =
50 10 6 0.5 = 171 H
i
100 0.30
Eq. 2-17
where
V = half the dc bus voltage at 205 V

i = 30% of the peak current at 100 A
t = 50% of the switching period
To verify the inductor design validity, the above inductor value was directly used in the
computer simulation. The simulation results shown Figure 2-20 indicate that for 100-A inductor
or load peak current, the ripple magnitude at zero-crossing region is about 30 A peak to peak.
Figure 2-20
Simulated Inductor Current and Resistive Load Current
2-16

B. Determine Inverter Output Filter Capacitor

After determining the filter cutoff frequency and the filter inductor value, the filter capacitor can
then be determined with the following simple relationship:
fc =
Eq. 2-18
2 LC
Vo (V)
With cutoff frequency of 4 kHz, and inductor value of 171 H, the capacitor value can be
calculated as 10 F. Figure 2-21 shows the inverter output voltage waveforms after filtering.
0.4k
0.2k
Vo1
Vm3
Vo2
-0.2k
-0.4k
10m
20m
30m
40m
50m
Figure 2-21
Inverter Output Voltage Waveforms After Filtering
2.4 Design Calculation for the 400-Hz Inverter Output Filters

The 400-Hz inverter is assumed to be rated 20% of the entire system. Similar to the 60-Hz
inverter design procedure, the harmonic contents of the inverter output before filtering need to be
identified for determination of the filter cutoff frequency. If the switching frequency is again
chosen at 20 kHz, with dual modulation, it is possible to select the cutoff frequency at 4 kHz to
obtain a 40-db reduction on the most significant harmonic. The filter inductor and capacitor can
then be determined accordingly.
A. Determine Inverter Output Filter Inductor
Consider the 50% inverter switching duty cycle at the zero-crossing region. If 15% of the
inductor current ripple or 6.15 A is allowable at the peak current, the inductance can be
calculated as
L=
200 163
V
t =
50 10 6 0.81 = 244 H
i
41 0.15
Eq. 2-19
where
V = the dc bus voltage at 200 V
2-17

i = 15% of the peak current at 41 A

t = 81% of the switching period
To verify the inductor design validity, the above inductor value was directly used in the
computer simulation. The simulation results shown Figure 2-22 indicate that for 50-A inductor
peak current, the ripple magnitude is about 6 A peak to peak and agrees with the calculation very
well.
60
Lf.I [A]
RL.I [A]
50
45
6A
40
30
0.6m
0.65m
0.7m
0.75m
0.8m
0.85m
0.9m t [s]
Figure 2-22
Simulated Inductor Current and Resistive Load Current
B. Determine Inverter Output Filter Capacitor

Given the filter cutoff frequency (4 kHz) and the filter inductor value, the filter capacitor can
then be determined with the following equation.
C=
1
(2f c )2 L
Eq. 2-20
With a cutoff frequency of 4 kHz and an inductor value of 244 H, the capacitor value can be
calculated as 6.5 F. Figure 2-23 shows the simulated inverter output voltage waveforms after
filtering in one cycle and its peaking region. The peak-to-peak ripple voltage is about 1 V and is
quite acceptable.
Figure 2-23
Inverter Output Voltage Waveforms After Filtering
2-18

2.5 Power Stage Design for Three-Level 4.16-kV System Active Front-End
Converter
A. Selection of the DC Bus Capacitor Voltage Level
The13.8-kV system requires at least 12-kV devices for the three-level full-bridge converter. The
availability of these 12-kV devices is very limited, and thus it is reasonable to start with a lower
voltage system such as the 4.16-kV system to start the design to verify the IUT concept. Once
the 12-kV-level devices are available, the same control system can be used to migrate to 13.8-kV
systems.
The 3-phase 4.16-kV system has a line-to-neutral voltage of 2.4 kV-rms or 3.4 kV-peak. The dc
bus voltage level can be selected about 20% higher than the input line peak voltage to allow
waveform shaping and reactive power control. Thus in this case, the dc bus capacitor can be
selected as Vdc = 4 kV. For 16.6 kW power, the dc output current is Idc = 4.15 A, and the ac input
current is Ia-rms = 6.92 A-rms.
B. Size of DC Bus Capacitor
The dc bus capacitor can be determined using Eq. 2-21. Given input current Ia-rms = 6.92 A-rms
and output voltage Vdc = 4 kV, if the dc bus voltage is allowed to have 5% ripple, then the
capacitance can be calculated as follows:
C1 = C 2 = C d =
I a rms
6.92
=
= 144 F
2 f r Vdc 2 120 4000 0.05
Eq. 2-21
Figure 2-24 shows simulation results for the dc bus and the split capacitor voltages over a 100ms range. The waveforms indicate that the ripple frequency is 120 Hz, and the ripple voltage is
200 V on the dc bus and 100 V on the split capacitor. The results agree with the design value
very well.
4.2k
Vdc.V [V]
3.6k
3.2k
2.8k
2.2k
vdc = 200V
2.2k 0
10m
20m
30m
40m
50m
60m
70m
1.9k
1.7k
1.5k
1.2k
80m
90m
0.1 t C2.V
[s] [V]
vc = 100V
0
10m
20m
30m
40m
50m
60m
70m
80m
90m
0.1 t [s]
Figure 2-24
Verification of Capacitor Ripple Voltage
2-19

C. Size of Boost Inductor

The boost inductor can be determined using Eq. 2-22. Assume 10% of the rms current is allowed
for the inductor ripple current, i.e., ia = 0.7 Apk-to-pk. With switching frequency fsw = 10 kHz,
the boost inductor can be calculated as follows.
L f = Dm
Vm Vdc
2 f sw ia
= 0.85
4000 3400
= 36 mH
2 10000 0.7
Eq. 2-22
Figure 2-25 shows simulation results for the boost inductor current over a 100-ms range. The
waveforms indicate that the ripple frequency is 10 kHz, and the ripple current magnitude is 0.7A,
which again agrees with the design value very well.
-10
L1.I [A]
iL
0.7A
-10.3
-10.5
-10.7
-11
95.6m
95.7m
95.8m
95.8m
95.9m
95.9m
96m
96m t [s]
Figure 2-25
Verification of Inductor Current Ripple
2.6 Physical Layout of the IUT

A. Power Stage Layout
Although the power circuit has been designed and simulated for a three-level full-bridge
converter, equivalently a five-level half-bridge converter would require the same amount of
power devices with the same voltage blocking level. Figure 2-26 shows the three-dimensional
view for the entire five-level half-bridge converter power circuit. The picture of custom-made
HV-IGBT is also shown with dimensions marked. A total of 8 HV-IGBTs are needed for a fivelevel half-bridge converter or three-level full-bridge converter. The high-voltage capacitors and
IGBT devices are placed underneath the PCB.
2-20

Figure 2-26
Three-Dimensional View of the Five-Level Half-Bridge Converter Power Stage
B HV-IGBT Gate Drive and Interface Layout

The HV-IGBT gate drive requires high-voltage isolation. For signal isolation, the optical fiber
transmitter and receiver are used to avoid common-mode noise trigger. For power isolation, the
high-voltage isolated power supplies are selected to block 6.6 kV between the device power
connection and the gate signals. Between the gate drive board and the computer controller, an
interface circuit will be present to transmit and receive the optical driving signals. The threedimensional view of the interface board is shown in Figure 2-27.
2-21

Figure 2-27
Gate Drive Interface Board
C. Physical Layout of the Complete IUT System

Figure 2-28 shows the complete IUT system. The entire system consists of (1) ac/dc converter
power board and associated HV gate drive boards, (2) dc/dc converter power board and associate
HV gate drive boards, (3) transformer, (4) dc/ac inverter and associated filter board, and (5)
computer controller and associated interface boards. The heat sink is embedded underneath the
power circuit PCBs. The Auto-Cad drawing indicates that the complete system can be
accommodated in a standard 19-inch (48.3-cm) rack-mount unit.
2-22

filt
l
t ro
n
co ard
bo
t
rec
er
bo
ard
r
rt e
e
inv ard
bo
ard
o
rb
ifie
ga
te
dri
ve
t ra H F
nsf
orm
14
er
10
rd
oa
b
er
w
po
HV
rs
ito
c
pa
ca
18
Figure 2-28
Physical Layout of the Complete Five-Level Half-Bridge Converter
2-23
3
MODELING AND SIMULATION FOR PERFORMANCE
VERIFICATION
This section provides details of the power electronics circuits and the associated open-loop and
closed-loop controller designs for the proposed multi-level converter-based IUT. Modeling
and simulation results of the active front-end ac/dc multilevel converter, dc/dc multilevel halfbridge converter, and dc/ac inverter are included. To ensure voltage balancing between the highside dc capacitors, performance verification of the proposed intelligent PWM technique is also
presented. Also provided is a performance evaluation of the complete IUT system with respect to
its ability to meet the desired functionalities that were earlier addressed in the generic functional
specification for a desired sophisticated transformer (which includes voltage-sag compensation,
instantaneous voltage regulation, outage compensation, capacitor-switching protection, harmonic
compensation, single-phasing protection, dc output, and 400-Hz output).
Active Front-End Control Design

The front end of the IUT consists of a full-bridge (or H-bridge) three-level diode-clamped
converter, a boost inductor, Lf, and a high-voltage DC capacitor bank, as shown in Figure 3-1.
Unlike a conventional diode bridge, the active front end (AFE) allows bidirectional power flow
and thus allows input current shaping that yields a pure sinusoidal wave for the input current.
The active control also allows reactive power flow control by shifting the input current phase
angle. For the 8-kV input voltage of the 16.6-kW system, the passive component parameters as
calculated in the previous section are given in Table 3-1.
Sr11
Sr21
Lf Sr12
Sr22
8 kV
16.6 kVA
+Vd/2
Cd
Si1
Si2
Vo
Sr11
Sr21
Sr12
Sr22
Cd
120/240 V
60 Hz
Si1
Si2
-Vd/2
Active Front End

Rectifier
Controller
Secondary Output
Controller
High Freq.
Inverter
Controller
Figure 3-1
Schematic of the Active Front End of IUT
3-1

Modeling and Simulation for Performance Verification
Table 3-1
Power Stage Parameters for the Active Front End
Parameters
Values
Vdc
13.2 kV 2.5%
Pd
16.6 kW
Lf
475 mH
Cd
26 F
Switching frequency
10 kHz
A. Open-Loop Transfer Functions of AFE

With sinusoidal pulse-width-modulation, the input line voltage is simply a sinusoidal function of
the dc bus voltage Vdc. Using duty cycle representation, the input line-to-neutral voltage, va0, can
be expressed as
v a 0 (t ) = d a (t )Vdc = Dm sin(t ) Vdc
Eq. 3-1
where Dm is the modulation index and da(t) is the duty cycle. Averaging the duty cycle over a
switching period, Eq. 3-1 becomes
v a 0 (t ) = D(t )Vdc
Eq. 3-2
Given the source voltage as a sinusoidal function, va0 = Vmsin(t), the boost inductor voltage can
be expressed as follows:
Vm sin(t ) D(t )Vd = L f
di Lf (t )
Eq. 3-3
dt
Introducing small signal perturbation [16] to Eq. 3-3, the duty cycle and the inductor current are
split into two terms. The first term is the operating condition, and the second term is the small
signal term. Eq. 3-4 and Eq. 3-5 show the expanded equations that include the small signal terms
in the original inductor current equation.
d i Lf + iLf (t )
Vm sin(t ) ( D + d (t ))Vd = L f
dt
di Lf
diLf (t )
+ Lf
Vm sin(t ) DVd d (t )Vd = L f
dt
dt
3-2
Eq. 3-4
Eq. 3-5

By subtracting Eq. 3-3 from Eq. 3-5, the voltages around the operating point condition cancel
each other, and the small-signal inductor voltage equation becomes
diLf (t )
d (t )Vd = L f
dt
Eq. 3-6
Applying Laplace transform to Eq. 3-6, the frequency domain transfer function of the inductor
voltage becomes
d ( s)Vd = sL f iLf ( s)
Eq. 3-7
Thus, the open-loop transfer function of the inductor current can then be obtained as
Gid ( s ) =
i Lf ( s )
V
= d
sL f
d ( s )
Eq. 3-8
According to the schematic shown in Figure 3-1, the dc bus capacitor voltage is charged by the
inductor current, and the boost inductor current relationship can be expressed as
dv dc (t )
2
=
D (t )i Lf (t )
dt
Cd
Eq. 3-9
Introduce small signal perturbation to Eq. 3-9 by splitting capacitor voltage and the inductor
current into two terms. The first term is the operating condition, and the second term is the small
signal term. Eq. 3-10 shows the expanded equations that include the small signal terms in the
original capacitor voltage equation.
dv dc (t ) dvdc (t )
2
+
=
( D(t ) I Lf (t ) + D(t )iLf (t ))
dt
dt
Cd
Eq. 3-10
By subtracting Eq. 3-9 from Eq. 3-10, the small-signal capacitor voltage becomes
dvdc (t )
2
=
D iLf (t )
dt
Cd
Eq. 3-11
Applying Laplace transform to Eq. 3-11, the current-to-voltage transfer function, GEd(s), is
obtained as follows:
GEd (s ) =
2D
sC d
Eq. 3-12
3-3

B. Feedback Control Design for AFE

The entire closed-loop control block diagram of the AFE with small-signal model is illustrated in
Figure 3-2. The sinusoidal line voltage Vm(t) is sensed and fed through a phase-lock-loop (PLL)
to provide synchronization signal for the power-factor control. The controller forces the output
dc bus voltage Vd equal to the reference dc bus voltage Vd*. There are two control loops: inner
current loop Hi(s) and outer voltage loop Hv(s). Both controllers can be either a PI or a PID
regulator as long as the stability is guaranteed. A limiter is placed after the controller to prevent
the large signal swing.
The duty cycle, d(t), is derived from the inner current feedback loop whose output is
compensated by Hi compensator. The output current command is derived by the required amount
of real power by which the dc bus voltage needs to be regulated. The input of the dc voltage loop
is the error voltage across the dc capacitors. This control assumes that an additional controller,
which will be introduced in the PWM generator section, balances the two dc bus capacitor
voltages.
PLL
Vm(t)
Vd*
Feedback Control
Sin()
K1
Hv
Hi
Koffset
Digital
Delay
io(t)
Vd (t)
GEd
Gid
d(t)
Active Front End Small-Signal Model
Figure 3-2
Closed-Loop Control Block Diagram for AFE
C. Current Loop Compensator Design

With given power stage parameters and Eq. 3-12, the frequency domain plots of the open-loop
transfer function can be shown in Figure 3-3.
3-4

Figure 3-3
Bode Plot of the Open-Loop Transfer Function
Notice that the converter switching frequency is limited, and a digital delay associated with the
finite switching frequency can be expressed in Eq. 3-13.
Digital_Delay = esTd
Eq. 3-13
Here, Td is the delay time. With a 10-kHz switching frequency, the delay time is approximately
0.1 ms. By incorporating the digital delay into the control-to-current transfer function, the phase
angle tends to have a sharp reversal and rapid roll off near the half switching frequency region.
Figure 3-4 indicates a phase reversal at 2.5 kHz and a rapid roll-off after that. Thus the digital
controller delay significantly limits the current loop control bandwidth. In general, the current
control bandwidth is limited to less than half the switching frequency. However, with the digital
controller delay, this frequency should be further reduced. In this design case, the current loop
controller should have a crossover frequency less 2.5 kHz.
3-5

Figure 3-4
Phase Plot of the Open-Loop Control-to-Current Transfer Function Associated With Digital
Delay
A PID compensator is used for Hi with one integrator, one pole, and one zero. Eq. 3-14 shows
the frequency representation of the PID controller.
H i 0 1 +
2f zi
H id ( s ) =
s
s 1 +
2f
pi
Eq. 3-14
The following criteria are used to derive the compensator parameters:

1. Select the desired crossover frequency, 120 Hz << fc = 1 kHz < 5 kHz.
2. Determine phase margin at fc, 50.
The compensator pole, zero, and dc gain can be determined by the following equations:
f zi = f c
1 sin
1 + sin
Eq. 3-15
f pi = f c
1 + sin
1 sin
Eq. 3-16
H i0 =
1
2f c
Gid (2f c )
f zi
f pi
Eq. 3-17
Using the design criteria and the plant transfer function, the PID controller pole and zero
frequencies and gain can be calculated as follows: fpi = 2.75 kHz, fzi = 364 Hz, and Hi0 = 525.
3-6

With unity current sensor gain and unity PWM peak voltage, the current loop gain can then be
expressed as
Td(s) = Gid(s)Hid(s)
Eq. 3-18
Figure 3-5 shows the Bode plots of the current loop gain to verify crossover frequency and phase
margin. The resulting crossover frequency is 1 kHz, and the phase margin is 50. Both agree
with the design criteria very well.
Figure 3-5
Bode Plots of Current Loop Gain
D. Voltage Loop Compensator Designs

After the current loop is closed with the known loop transfer function, the voltage loop transfer
function can be obtained accordingly. Eq. 3-19 shows the voltage loop transfer function before
compensator design.
TEd ( s ) = G Ed ( s )
Td ( s )
1 + Td ( s )
Eq. 3-19
3-7

Using Eq. 3-12 for GEd(s) and Eq. 3-18 for Td(s), the Bode plots of the voltage loop transfer
function with closed current loop can be obtained, as shown in Figure 3-6.
Figure 3-6
Bode Plots of the Voltages Loop Transfer Function With Current Loop Closed
To achieve stable regulated dc voltage, a PID compensator is needed to attenuate the highfrequency component of the voltage loop. This alleviates interference of the voltage loop to the
current loop response. The transfer function of the voltage loop compensator Hvd(s) is similar to
the current loop compensator Hid(s) with one integrator, one pole, and one zero.
H v 0 1 +
2f zv
H vd ( s ) =
s
s 1 +
2f
pv
The following design criteria are used to derive the compensator parameters:
1. Select the desired crossover frequency, fc = 20 Hz < 120 kHz.
2. Determine phase margin at fc, 65.
3-8
Eq. 3-20

Eqs. 3-15, 3-16, and 3-17 can be used again to find the voltage loop compensators. The resulting
dc gain Hv0, pole frequency fpv, and zero frequency fzv are obtained as follows: Hvo = 0.105, fpv =
90.2 Hz, and fzv = 4.4 Hz. With unity voltage sensor gain, the entire voltage loop gain including
the PID compensator can be expressed in Eq. 3-21.
TE(s) = TEd(s)Hvd(s)
Eq. 3-21
Figure 3-7 shows the Bode plots of the voltage loop transfer function with inclusion of the
voltage loop compensator Hvd(s). The results indicate that the crossover frequency is 20 Hz, and
the phase margin is 65. These results, again, agree with the design calculation very well.
Notice that the voltage loop crossover frequency is generally lower than the line frequency of 60
Hz to avoid stability problems. The current loop crossover frequency, however, is much faster
than the line frequency to ensure that the input line current tracks the input line voltage with a
clean sinusoidal waveform.
Figure 3-7
Bode Plot of Voltages Loop Gain
3-9

E. PWM Generator and DC Link Voltage Balancing Techniques

The dc bus capacitors tend to be unbalanced due to parameter mismatch. The unbalanced voltage
can cause dc components in excitation current and consequently saturate the high-frequency
transformer. This section presents a dc bus voltage-balancing technique with feedbackcompensated PWM. The technique can be further extended to more than three levels by fully
utilizing the redundant switching patterns.
To explain the voltage-balancing technique, two three-level diode-clamped converter phase legs
in the full-bridge converter are used as an example. Figure 3-8 illustrates a simplified circuit of
the three-level diode-clamped active front-end converter. The dc loads are assumed to be
connected across the two capacitors and are assumed to be balanced. The four-switch structured
phase-leg switches are replaced with a single-pole, triple-throw switch. The triple-throw
positions represent three voltage levels: VP = Vdc/2, 0, and VN = Vdc/2. Based on the selected
switch position, each phase leg can synthesize three output voltage levels accordingly. The fullbridge with two phase legs can synthesize a total of 5 voltage levels with respect to the midpoint
between two capacitors. By normalizing the voltage levels with respect to the half-dc bus
capacitor voltage, the five voltage levels can be represented as: +2, +1, 0, 1, 2. The voltage
levels +1 and 1 can be obtained with two different switching patterns, while the voltage level 0
can be synthesized with three different switching patterns. In other words, there are some
redundant switching states that can be used for voltage balance among the capacitors. Overall,
there are nine possible switching patterns for the full-bridge, five-level AFE converter.
ILP
IRN
nLP
nL0
IO
SL
Vm
VL
ICP
VP CP
IL0
nLN
ILN
IR0
+ ICN
VN CN
_
nRP
nR0
nRN
IRN
IO
SR
VR
Figure 3-8
Three-Level Diode-Clamped Converter as an Active Front End Using Single-Pole, TripleThrow Switches to Represent the Phase Legs
Table 3-2 shows all possible switching states of the three-level full-bridge diode-clamped AFE
converter. The three switching states of the left phase leg are defined as nLP, nL0, and nLN, and
the three switching states of the right phase leg are defined as nRP, nR0, and nRN. At each
3-10

switching state, the currents flown out of the left phase leg are ILP, IL0, and ILN, and the currents
flown into the right phase leg are IRP, IR0, and IRN. The charging currents of two split capacitors are
ICP and ICN. The output of the left phase leg is defined as VL, and the output of the right phase leg
is defined as VR. The difference between VL and VR, VL VR, is the overall voltage across the ac
line.
Table 3-2
Possible Switching States of Three-Level Diode-Clamped AFE Converter
nLP
nL0
nLN
nRP nR0 nRN ILP
IL0
ILN
IRP
IR0
IRN
ICP
ICN
VL
VR
VLVR
Level
1 1
IO
IO
IO
IO
VP
VN
VP +VN
+2
2 1
IO
IO
IO
VP
VP
+1
3 0
IO
IO
IO
VN
VN
+1
4 1
IO
IO
VP
VP
5 0
IO
IO
6 0
IO
IO
VN
VN
7 0
IO
IO
IO
VP
VP
8 0
IO
IO
IO
VN
VN
9 0
IO
IO
IO
IO
VN
VP
VN VP
Derived from Table 3-2, the state machine of the synthesized voltage level is shown in
Figure 3-9. The voltage level of +2 and 2 can be synthesized only by states 1 and 9,
respectively. No redundancy is in these two states. The voltage level of +1 can be generated by
states 2 and 3, while the voltage level of 1 can be generated by states 7 and 8. States 4 through 6
are used to synthesize zero voltage level.
1
+2
+1
0
-1
-2
Figure 3-9
State Machine of the Proposed PWM Technique
3-11

Using state 2 as the example and by observing Table 3-2, the upper capacitor CP is charged by
the load current, whereas CN is disconnected from the ac line. For state 3, if VP equals VN, the
AFE voltage is identical to that of state 2, but CN is discharged instead. The condition is opposite
when the output current is in opposite direction.
Thus, the unbalanced voltages in the dc bus capacitors can be overcome by properly selecting
state transition. Figure 3-10 shows the block diagram of the PWM generator. The output PWM
switching signals are determined by the three input parameters: (1) duty cycle from feedback
control D(t), (2) the output current, io(t), and (3) the two dc bus capacitor voltages VP(t) and VN(t).
D(t)
iO(t)
VP(t)
PWM
Generator
Switching Signals
VN(t)
Figure 3-10
PWM Generator Block Diagram
The switching pattern selection method is shown in Figure 3-11. The first step is to determine the
voltage level. There are five voltage levels, and thus the leveling function, Lev(t), is defined to
have five members {2, 1, 0, +1, and +2}, as shown in Eq. 3-22.
Lev(t ) = { 2,1,0,+1,+2}
3-12
Eq. 3-22

VPVN
VP<VN
IO0
IO<0
+2
c
e
+1
d
e
Lev(t)
g
i
-1
j
i
-2
Figure 3-11
Flowchart of PWM Generator
The duty cycle command, D(t), shown in Figure 3-2 is derived from the feedback control system
and is used to generate determine the voltage level. In every switching cycle, two levels, Levmax
and Levmin, are used to generate an average output voltage, as shown in Figure 3-12. The
following relationship is used to determine the level boundaries Levmax and Levmin:
Levmin (t ) < D (t ) (
N +1
) < Levmax (t )
2
Eq. 3-23
where N is the number of level, which is five in this case.

D(t) is the duty cycle.
Levmin(t) and Levmax(t) are a set of { 2,1,0,+1,+2} and are adjacent.
3-13

D(t)
VO(t)
LevMAX
D1
LevMIN
t(s)
0
D1T
Figure 3-12
Pulse Width Modulation as Function of Duty Cycle
The next step is to compare each dc bus capacitor voltage as shown in the second column in
Figure 3-11. As previously explained, levels +2 and 2 have singular switching pattern;
therefore, there is only one pattern for these two levels. None of the three zero level switching
patterns affect the charge balance of the dc bus capacitor. Thus only one pattern is employed.
The last consideration is the direction of the output current. The switching pattern is then
selected to satisfy the current flow mode defined in Table 3-2.
F. Simulation Results for the Three-Level Active Front End Converter
The stability and performance of both voltage and current loops for the 3-level AFE converter
are verified with the time-domain simulation. Simplorer Version 6 was used as a simulation tool.
Figure 3-13 shows the simulation results of input voltage and current. The current waveform
maintains a sinusoidal waveform and is in phase with the voltage regardless of load conditions.
Input Voltage
Input Current
Figure 3-13
Unity Power Factor Is Maintained Regardless of Load Conditions
3-14

The simulation setup is to have a step load change at 20 ms. It can be seen from Figure 3-13 that
the input current rises and from Figure 3-14 that the dc bus voltage dips after the load transient.
With voltage control loop closed, the dc bus voltage gradually moves to the preset level after the
load transient. The simulated peak-to-peak capacitor voltage of 300 V agrees with the original
design very well. The current maintains a sinusoidal waveform even during the load transient
condition because it has a fast control loop bandwidth with a crossover frequency of 1 kHz.
Figure 3-14
Regulated DC Link Voltage
The voltage loop response also corresponds to the control loop design very well. From
Figure 3-14, it can be seen that the dc bus voltage returns to the steady-state condition within
0.15 s, which corresponds to 3 cycles of 20-Hz voltage loop control bandwidth. Similar to the
performance verification in power stage design, the performance is also well verified in the
control loop design. Overall, both current and voltage loops are effectively modeled and
designed to have satisfactory performance.
3.2 Modeling and Simulation of the 60-Hz DC/AC Inverter

The full-bridge inverter circuit shown in Figure 3-1 can be simplified in Figure 3-15(a) for
modeling and controller design purpose. Each phase leg is controlled independently with two
output nodes: a and b. Voltages va0 and vb0 represent the output voltages against the negative dc
rail. These two voltages contain dc components, but their difference, vab = va0 vb0, is a pure ac
output. As described before, vab is a PWM chopped square wave, and it requires a set of nondissipative filters to make it a clean sinusoidal output, which in this case is vac.
3-15

Q1
Lac
Co
Q3
Cac
Vo
Q2
Q4
vac
0
Figure 3-15(a)
Full-Bridge DC/AC Inverter Circuit
A. Behavior Circuit Modeling

The circuit diagram in Figure 3-15(a) can be converted to a behavior circuit model, as shown in
Figure 3-15(b). The IGBT switches are replaced with PWM duty controlled voltage sources and
current sources. The average outputs are simply the product of average duty cycles, da and db,
and the dc bus voltage, Vo. Eqs. 3-24 and 3-25 show the mathematical expressions of the two
average duty cycles.
va 0
idc
+
Vo
d a ia
d b ib
Lac
ia
d aVo
Load
Cac
RL
LL
ib
vb 0
d bVo
Average inverter model

Figure 3-16(b)
Behavior Circuit Model of a Full-Bridge Inverter Circuit
d a = average(d a ) = 0.5(1 + Dm sin t )
Eq. 3-24
d b = average(d b ) = 0.5(1 + Dm sin(t 180))
Eq. 3-25
Here, Dm is the modulation index. The transfer function between control input dab and the output
voltage vac is simply a second-order equation characterized by an LC filter circuit with the
resonant frequency equal to the previously cutoff frequency fc, as shown in Eq. 3-26.
3-16

fc =
1
2 Lac Cac
Eq. 3-26
B. Inverter Controller Design With a Simple Voltage Loop

Because the plant transfer function is identical to the full-bridge dc/dc converter and the threelevel ac/ac converter, the controller design approach for the full-bridge dc/ac inverter is similar
to previously described procedure. It can have both voltage loop and current loop, or simply just
a voltage loop. Figure 3-17 shows the full-bridge dc/ac inverter control system with a simple
voltage loop. The compensator Gc(s) can be a simple PI or PID controller. For placement of pole
and zero, a zero is normally included to cancel the filter pole to reduce the overshoot during load
transient, and an integrator is generally incorporated to eliminate the steady-state error. Similar
to the design in the ac/dc converter circuit, the control loop needs to maintain a proper phase
margin for stability concern.
iLac Lac
+
Full Bridge
Inverter
Vo
+
Cac
vab
da(t) db(t)
H(s)
vc
Pulse-width
modulator vc
Load vac
Gc(s)
vsense
+
vref = Vref-pksin(t)
Figure 3-17
Control System of a Full-Bridge DC/AC Inverter With a Simple Voltage Loop
The problem with a simple voltage loop is it requires a large gain to achieve fast response. A
system with a high control loop gain tends to have stability concern and high overshoot during
load transients. Figure 3-18 shows the transient response of a voltage-loop controlled inverter
with load steps and load dumps at different positions of the sinusoidal wave. Two load branches
are connected to have a small current iRL1 and a large load current iRL2. The total load current iRL is
the sum of two currents. The load can be dumped and stepped at any time and in consecutive
cycles. The example here is to keep the small load iRL1 constant and switch the load branch iRL2
fully on and off to represent a 10.5-kW load step and load dump. The most severe transient
condition is when the load transient occurs at the peak, or at 20 ms in the simulated case. A
severe output voltage and current oscillation occurs when load dumps near the peak ac output
condition. Physically, this oscillation can be explained that the dc bus voltage cannot supply
enough energy to compensate for the need of the transient load. A control loop with high gain
tries to draw too much energy in a short time and thus causes severe output waveform
3-17

oscillations. If the load transient occurs at near the zero crossing, the oscillations are typically not
noticeable.
350
vac
200
100
0
iRL2
-100
-200
-350
70.0
40.0
20.0
0
-20.0
-40.0
-70.0
20m
40m
60m
80m
20m
40m
60m
80m
40m
60m
80m
iRf & iRL

iRL1
0
1.0
0.5
0
-0.5
-1.0
dm sint
20m
Figure 3-18
Transient Response With Simple Voltage Control Loop
C. Inverter Control Design With Feed-Forward Voltage Loop

For the control loop to respond to load transients more smoothly, several methods have been
proposed [17, 18, 19, 20, 21]. These methods were proposed mainly for uninterruptible power
systems (UPSs). In this project, we propose to use a novel feed-forward control in the voltage
loop, as shown in Figure 3-19. The control design is very simple: only a simple integrator and a
zero to cancel the filter pole. A high gain can be used to achieve fast response, and an integrator
can be used to eliminate the steady-state error. The only difference from the simple voltage loop
control system is to add the reference signal to the controller output. This approach prevents the
compensator output being too large during load transients, thus preventing severe overshoot
voltage.
3-18

iLac Lac
+
Full Bridge
Inverter
Vo
+
vab
Cac
Load vac
H(s)
da(t) db(t)
vc
PWM
vc
negate
+
+
Gc(s)
vsense
vref = Vref-pksin(t)
Figure 3-19
The Full-Bridge Inverter Control System With Feed-Forward Control
Figure 3-20 shows the transient response with the proposed feed-forward voltage loop control
method. Two load branches are connected to have a small current iRL1 and a large load current iRL2.
The total load current iRL is the sum of two currents. The load can be dumped and stepped at any
time and in consecutive cycles. The example here is to keep the small load iRL1 constant and
switch the load branch iRL2 fully on and off to represent 10.5-kW load step and load dump. The
output voltage vac under such a severe load transient sees only a small glitch, but no oscillation.
The most severe voltage glitch, again, occurs at the peak output voltage region because the
availability of supply voltage margin is limited. The output voltage glitch is practically invisible
for any other occurrence of the load transient. The controller output signal Gc(s) is relatively
small as compared to the reference signal dmsin(t), but the control response is much smoother,
and the steady-state error is eliminated. Here, dm represents the modulation index.
3-19

350
vac
200
100
iRL2
0
-100
Load dump
10.5 kW
-200
-350
0
70
40
20
0
-20
-40
-70
20m
Load step
10.5 kW
Load dump
10.5 kW
Load step
10.5 kW
40m
60m
80m
40m
60m
80m
60m
80m
iRf & iRL

iRL1
0
1.0
20m
dm = 0.85
dm sint
0.5
0
-0.5
-1.0
20m
Controller output
40m
Figure 3-20
Transient Response With Feed-Forward Voltage Loop Control
3.3 Performance Verification for the Entire IUT System

Shown in Figure 3-21, the entire IUT system contains four major blocks: (1) the 3-level diodeclamped ac/dc converter, (2) the 3-level high frequency dc/ac inverter, (3) high-frequency
transformer along with the rectifier and LC filter, and (4) the full-bridge dc/ac inverter along
with LC filter. The semiconductor switches can be replaced with ideal switches in simulation to
reduce the simulation time. The input source voltage vin is 8 kV rms, and the output contains two
split ac voltages vac1 and vac2, each 120 V. The sum of these two voltages becomes vac12 = 240 V.
The simulation is typically to study the relationship between input source and output load. An
example is to apply a disturbance at the input and to check the performance at the output, or vice
versa. In order to explain the disturbance effects, some intermediate stage signals will be shown.
3-20

3-level diodeclamped converter
iin
SA1
SB1
SA2
SB2
VHV-dc
Sa1
C1
V HV _ dc
vin=8kV
3-level
inverter
Sa2
B
SA1
SB1
SA2
SB2
C2
xformer+
rectifier+
LC filter
Sa1
+i
i
vac1 ac1 ac12
+
inverter 120V
v
ac12
+ LC
v
filter ac2
120V
+ iac2
Sa2
0
Figure 3-21
Complete IUT for System Simulation
The IUT presents several distinct features over conventional transformers. Many of them can be
verified with the computer simulation. The following sections will explain some key IUT
features through the computer simulation results:
(A) Voltage-sag compensation
(B) Outage compensation
(C) Instantaneous voltage regulation under load transients
(D) Unbalanced load, overload operation, and reactive load
(E) Nonlinear load and harmonic compensation
(F) 400-Hz output and variable-frequency output
(G) Capacitor-switching protection
(H) DC output
A. Voltage-Sag Compensation
The voltage sag can be compensated by pumping more current into the active-front-end
converter. In terms of how many cycles and how much of a voltage sag the IUT can compensate,
the design can be flexible enough to accommodate specific requirements. For example, the dc
bus capacitors can be increased several times for compensating for more cycles.
Figure 3-21 shows the simulation diagram for the AFE converter with the use of step functions
for voltage-sag simulation. Step function STEP1 drops the voltage to half at 20 ms, and step
function STEP2 brings the input voltage back to normal at 50 ms. In this simulation, the dc bus
capacitors C1 and C2 are kept as the original designthat is, C1 = C2 = 26 F. All other
3-21

parameters are unchanged, including all parameters for dc/dc converter and dc/ac inverter, as
shown in Figure 3-23. The output of the inverter is connected with different loads, including pure
resistive and RL loads. These loads are either connected across the 120-V output or 240-V
output. Notice that both AFE converter and inverter are controlled by closed-loop compensators
to ensure sinusoidal input current and output voltage. The power circuit contains simplified
switches, ideal diodes, and RLC components. Two transformers are used to provide split ac
outputs. The control circuits are represented with colored blocks.
SPWM
AM3
D3
Sr11
PWM1
EQU
Sr21
D11
D1
D9
EQU
TRIANG2
PWM
Input: DUTYp
TRIANG1
D22
Tri2
D17
Si1
R2
PWM2
Tri1
EQU
D4
Sr12
MUL3
Sr22
TWT1
TWT
E5
Vdc +
SUM51
CONST6
D18
Si2
C1
L1
R1
SINE1
D2
CONST
STEP1
SUM52
Sr211
D7
Sr111
D12
D19
Si11
D5
R3
D21
D10
STEP2
CONST1
DUTYppp
C2
D6
INPUT[0] := SINE1.VAL
MUL2 LIMIT1
Hi
DUTY3
G(s)
SUM5
CONST
OFFSET
TWT2
TWT
MUL1
LIMIT
CONST
D20
Si22
CONST
CONST := 88.75u
DUTYp
Sr222
D8
Sr122
DUTY_OP
Hv
LIMIT
SUM2
B[0] := 5.12k
B[1] := .918
A[0] := 0
INPUT[0] := LIMIT1.VAL
Vdc_ref
G(s)
CONST
CONST := 13.2k
B[0] := 105m
B[1] := 3.8m
A[0] := 0
Figure 3-22
AFE Converter Simulation Diagram Showing Step Functions for Voltage-Sag Simulation
TPH2
SUM3
TRIANG3
sin083
LIMIT3
Gs1
SUM10
LIMIT
sin085
LIMIT2
SUM9
LIMIT
D13
D14
TWT1
TWT
Rf3
Lf3
2m
126u
Gs
GAIN
SUM8
h0025
G(s)
GAIN
SUM7
S1
Vrec1
G(s)
TPH1
SUM6
h0024
S3
D23
D25
AM1
Lf1
Cd1
Cf1
D16
D27
Rstp1
+ VM1
V
RL
RL1
D15
D28
Rf4
Lf4
2m
126u
Lf2
AM2
Rstp2
Cd2
NEG4
S2
D30
NEG
+ Vrec2
TWT
NEG
Lf11
TWT2
D24
NEG2
S4
Cf2
Lf12
+VM2
RL2
D26
D29
Figure 3-23
Inverter Simulation Diagram Showing Fixed Load Under Voltage-Sag Operation
3-22

Figure 3-24 shows voltage sag simulation results, where individual traces can be explained as
follows:
1. The input voltage vin drops to 50% at 20 ms and recovers back to 100% at 50ms.
2. The input current iin is more than double when voltage drops to half, because the AFE
converter closed-loop control tries to put the same amount of power into high-voltage dc bus
capacitors.
3. The controller also tries to regulate the high-voltage dc bus voltage VHV-dc and dc bus capacitor
voltage VC2, but the regulation is not effective until the input voltage recovers back to normal.
4. The low-side dc bus voltage VLV-dc follows the high-side dc bus voltage with capacitor
voltages reduced.
5. The output 240 V ac voltage vac and both 120-Vac voltages vac1 and vac2 are very well regulated
during voltage-sag conditions.
6. The 240-V output load current iac and both 120-Vac output load currents iac1 and iac2 are not
affected by the voltage sag.
3-23

12k
vin
0
-12k
90
4
10m
20m
30m
40m
50m
60m
70m
80m
90m
0.1 t
40m
50m
60m
70m
80m
90m
0.1
iin
0
-4
-9
14k 0
10k
7k
4k
0
0.25k 0
10m
VHV-dc
20m
30m
VC2
10m
20m
VLV-dc
30m
40m
50m
60m
70m
80m
90m
0.1 t
10m
20m
v30m
ac
40m
50m
60m
70m
80m
90m
0.1 t
iac1
10m
20m
30m
40m
iac2
50m
60m
70m
80m
90m
0.1 t
10m
20m
30m
40m
50m
60m
70m
80m
90m
0.1 t
0.14k
80
0
0.35k 0
0.15k
0
-0.15k
-0.35k
0.16k 0
vac1
vac2
0
-0.16k
0
iac
Time (s)
Figure 3-24
Voltage-Sag Simulation Results
To show how the control loop reacts after a voltage sag, the high-voltage dc bus capacitor
voltage VC2, the high-voltage dc bus voltage VHV-dc, and the input current iin are shown in
Figure 3-25 with expanded scales. It can be seen that after a voltage sag at 50 ms, the dc bus
voltage and input current tend to recovered within one line frequency cycle.
3-24

7k
6.7k
6.5k
6.3k
6k
VC2
14k 50m 55m 60m

VHV-dc
13.4k
13k
12.6k
12k
10 50m 55m 60m
65m
70m
75m
80m
85m
90m
95m 0.1
65m
70m
75m
80m
85m
90m
95m
0.1
65m
70m
75m
80m
85m
90m
95m
0.1
iin
4
0
-4
-10
50m 55m
60m
Time (s)
Figure 3-25
Responses of DC Bus Voltages and Input Current After Voltage Sag
B. Outage Compensation
Similar to voltage sag compensation, the IUT can be designed such that the output compensation
can accommodate any number of cycles as long as the dc bus capacitors are well sized.
The difference is that when the input voltage is totally out of service, the input current is also
completely interrupted. In this case, the output supply needs to rely on the energy stored in the dc
bus capacitor. Thus, in order to have more outage compensation capability, the dc bus capacitor
needs to be sized accordingly.
In the simulation study, the dc bus capacitance is doubled to C1 = C2 = 52 F for outage
compensation for about two cycles. The simulation diagram is the same as that used in voltagesag compensation. The input voltage drops to zero t = 20 ms and recovers back at t = 50 ms.
Figure 3-25 shows outage simulation results, where individual traces can be explained as
follows:
1. The input voltage vin drops to 0% at 20 ms mark, and recovers back to 100% at 50ms.
2. The input current iin ceases conducting when voltage drops to zero because the closed-loop
controller senses a zero reference in the AFE converter.
3. The high-voltage dc bus voltage VHV-dc and dc bus capacitor voltage VC2 are not regulated and
start drooping after outage occurs. The regulation is resumed after the input voltage recovers
back.
3-25

4. The low-side dc bus voltage VLV-dc follows the high-side dc bus voltage with capacitor
voltages reduced.
5. The output 240-Vac voltage vac and both 120-Vac voltages vac1 and vac2 are very well regulated
during outage until the low-side dc bus voltage drops below 160 V, which occurs after the
outage period and before the AFE pumps sufficient energy into high voltage dc bus.
6. The 240 V output load current iac and both 120 V ac output load currents iac1 and iac2 are
affected in the same wave as their respective voltages.
12k
vin
0
-12k
16 0
10m
20m
30m
40m
50m
60m
70m
80m
90m
0.1
40mV 50m
60m
70m
80m
90m
0.1 t
50m
60m
70m
80m
90m
0.1
iin
0
-6
-16
14k 0
10k
7k
4k
0
0
0.25k
10m
20m
30m
HV-dc
VC2
10m
20m
30m
40m
10m
v
20m
v30m
ac
40m
50m
60m
70m
80m
90m 0.1
30m
iac1
40m
50m
60m
70m
80m
90m
0.1 t
30m
40m
50m
60m
70m
80m
90m
0.1 t
VLV-dc
0.14k
80
0
0.35k 0
0.15k
0
-0.15k
-0.35k
0.16k 0
ac1
vac2
10m
iac 20m
0
-0.16k
0
10m
iac2
20m
Time (s)
Figure 3-26
Outage Compensation Simulation Results
To show how the control loop reacts after an outage, the input current iin, the high-voltage dc bus
voltage VHV-dc, the high-voltage dc bus capacitor voltage VC2, and the low-voltage dc bus voltage
VLV-dc are shown in Figure 3-26 with expanded scales. It can be seen that after voltage outage at
3-26

50 ms, the dc bus voltage and input current recover slowly with about three line cycles to reach
steady state. It should be noted that the input current shoots up to five times the rated current
immediately after the outage because the dc bus voltage has been dropped too low, and the
control loop computes a duty cycle that is much higher than the normal value. Practically all dc
bus voltages see an overvoltage during recovering process after outages. This phenomenon is
quite different from voltage-sag compensation conditions where the transient overshoot is much
less and much easier to handle.
16
iin
0
-6
-16
14.4k 50m 55m
12.5k
60m
65m
70m
75m
80m
85m
90m
95m
0.1
60m
65m
70m
75m
80m
85m
90m
95m
0.1
65m
70m
75m
80m
85m
90m
95m
0.1
65m
70m
75m
80m
85m
90m
95m
0.1 t
VHV-dc
11.5k
10k
7.2k 50m 55m
VC2
6.4k
5.8k
5k
0.24k 50m 55m
0.2k
60m
VLV-dc
0.18k
0.15k
50m 55m
60m
Time (s)
Figure 3-27
Responses of DC Bus Voltages and Input Current After Outage
The fact that the input current is exceedingly high is because the dc bus voltage drops to below
the input line voltage. Because the AFE is a boost converter, it is similar to short-circuit
condition when the output voltage is lower than the input voltage. Thus the controller needs to
have a current-limiting control to prevent excessive current after an outage.
C. Instantaneous Voltage Regulation Under Load Transients
The voltage-sag and outage compensations deal with the disturbance coming from the input
source voltage. For the disturbance coming from the load, the inverter closed-loop needs to be
fast enough to provide instantaneous output voltage regulation.
In the simulation study, two load transients are applied. The first one is applied at 20 ms with a
load dump, and the second one is applied at 40 ms with a load step. The output voltage sees a
small glitch at 20 ms because it is near the peak voltage region. However, the glitch disappears
3-27

almost immediately. The second load transient is near zero-voltage crossing, and the output
voltage regulates very well with nearly an invisible voltage glitch.
Figure 3-28
Simulation for Instantaneous Voltage Regulation Under Load Transients
D. Effects of Unbalanced Load, Overload, and Lagging Power Factor

There are three output load connections: vac1 = 120 V, vac2 = 120 V, and vac12 = 240 V. The IUT
allows a rated output load power of 16.6 kW. If the two split-phase loads are not balanced, as
long as each split phase does not exceed 8.3 kW, the IUT should run normally. The input is not
affected by any unbalanced load condition.
Figure 3-29 shows simulation results of the IUT under unbalanced load condition. A highly
unbalanced load has been simulated to show that it does not have any impact on the input line
voltage or current. Initially, only iac1 is fully loaded and iac2 is in no-load condition. At 50ms, the
loading situation is totally reversed, with iac1 under no-load condition and iac2 under full-load
condition. In fact, the design allows 100% unbalance load condition.
3-28

Figure 3-29
Simulation Under Unbalanced Load Condition
The IUT allows a rated output load power of 16.6 kW. Another case was simulated wherein the
overall output was 100% overloaded. The results are shown in Figure 3-29. As compared to the
previous cases, the input current rms value increases to 0.21kA, or 100% higher than the rated
2.1 A rms. This overload condition can be handled with sufficient thermal handling. In general,
5,6
the UPS products are specified 1 minute for 150% overload and 10 minutes for 125% overload .
Such a specification can also be used for the IUT design guideline.
Figure 3-30
Simulation Results Under 100% Overload
5 Product specification of Toshiba G8000 Series UPS 150, 225, 300 kVA.
6 Product specification of Powerware UPS 9315-250.
3-29

Figure 3-30 shows the simulation results with the output load operating under lagging power
factor. Even under this condition, the input remains unity power factor. Physically, it can be
explained that the dc link capacitors, including high-voltage side and low-voltage side, absorb all
the reactive power, and the input sees unity a power factor. Figure 3-30 shows simulation results
of the IUT with phase 1 under unity power factor and phase 2 under lagging power factor
condition. Both phases are loaded under a 10-kVA condition. Notice that the power factor of
phase 2 is below 0.5, but the input power factor remains unity.
Figure 3-31
Harmonic Compensation
E. Effects of Nonlinear Loads

The nonlinear load current contains significant harmonics, possibly exceeding 100% THD.
Figure 3-32 shows the time-domain simulated nonlinear load current and its associated line
voltage. The top of line voltage is highly distorted due to the inductance voltage drop with
nonlinear current change rate. Figure 3-32 shows a frequency spectrum of the simulated
nonlinear load. Typical THD exceeds 100% for a single-phase nonlinear load.
3-30

Figure 3-32
Time-Domain Voltage and Current Waveforms of a Nonlinear Load
60
30
60
24
20
22
80
19
40
17
00
15
60
12
20
10
0
78
0
54
IRw (A)
30
60
7
6
5
4
3
2
1
0
Harmonic number
Figure 3-33
Harmonic Contents of the Nonlinear Load
Figure 3-34 shows the time-domain simulated voltage and current waveforms for the IUT output
inverter operating under open-loop control conditions. Figure 3-35 shows the time-domain
simulated voltage and current waveforms for the IUT output inverter operating under closed-loop
control conditions. The output voltage tends to distort and oscillate if the inverter is not closedloop controlled. With closed-loop control, the output voltage remains clean and sinusoidal even
with a nonlinear load with higher than 100% THD.
3-31

Figure 3-34
Inverter With Open-Loop Control
Figure 3-35
Inverter With Closed-Loop Control
F. Performance Verification for the 400-Hz Inverter

The same feed-forward voltage-loop controller can be used for the 400-Hz inverter. Figure 3-35
shows the load transient response for the 400 Hz using the same feed-forward control technique.
The inverter contains two loads with currents iR1 and iR2. Current iR1 is lagging because it contains
an inductor in the load branch. The second branch contains only a resistive load, and thus current
iR2 is in phase with the output voltage with magnitude slightly higher than iR1. A load dump occurs
at near the positive peak ac voltage, and a load step occurs at near the negative peak ac voltage.
During these two load transients, the pure resistive load branch is either totally on or off. The
first branch with RL load remains in the circuit. This implies a more than 50% load transient
3-32

occurs in both load dump and load step. With the proposed feed-forward control technique, both
occurrences indicate only a small glitch on the output voltage waveform.
Figure 3-36
Transient Response for the 400-Hz Output
3.4 Modularization for Three-Phase IUT Design

The IUT can be designed in a modular fashion that multiple IUTs can be paralleled or combined
to be a three-phase system. Figure 3-37 shows the block diagram of the modular IUT design for
three-phase configuration. It is assumed that the output line-to-line is 208 V, and line-to-neutral
is 120 V. The input remains 13.8 kV for line-to-line and 8-kV for line-to-neutral.
Figure 3-38 shows the simulated input voltage and current under load-step condition. Assume
initially that the IUT is not loaded. At 20 ms, the output is loaded with 16 kW. It can be seen that
the dc bus voltage droops, but the input voltage remains unaffected. The input current increases
gradually to the full-load current in about 2 line cycles.
A
8kV
B
8kV
N
C
8kV
M-level 6.6kV M-level

converter 6.6kV inverter
Xformer+
Rectifier+
LC Filter
Inverter

Xformer+
Rectifier+
LC Filter
Inverter

Xformer+
Rectifier+
LC Filter
Inverter
a
208V
b
+
120V
208V
n
c
Figure 3-37
Modular IUT Design for Three-Phase Connection
3-33
Input voltage
Vin = 8kVrms
vin (V)

12k
6k
0
-4k
HV dc bus
voltage = 13.2kV
10m
20m
30m
40m
50m
60m
70m
80m
90m
0.1 t
13.2k 0
10m
20m
30m
40m
50m
60m
70m
80m
90m
0.1 t
10m
20m
30m
40m
50m
60m
70m
80m
90m
0.1 t
4
1.5
0
-2
-4
VHV_dc (V)
Input current
with AFE
Iin = 2.85Arms
iin (A)
-12k
12.2k
11.6k
11k
Output dc
currents
Io_dc=0 step to 40A
Io_dc (A)
Output dc
voltages
Vo_dc = 400 Vdc
Vo_dc (V)
10k
0.44k0
0.275k
0.2k
0.125k
0
45 0
32.5
22.5
Load step
10m
20m
30m
40m
50m
60m
70m
80m
90m
0.1 t
10m
20m
30m
40m
50m
60m
70m
80m
90m
0.1 t
12.5
0
0
Figure 3-38
Simulated Three-Phase IUT Input Voltage and Current Under Load-Step Condition
3-34
4
RELIABILITY ASSESSMENT OF THE PROPOSED IUT
SYSTEM
This section provides results of an in-depth reliability assessment of the proposed IUT system
using an industry standard reliability calculation method. MIL-HDBK-217F is a most commonly
used method for reliability prediction of electronic equipment. The different input parameters
that are required to perform a reliability assessment of the proposed design are provided. This
section also provides a detailed reliability assessment of a design proposed by S. Sudhoff et al.
and compares it with the proposed multi-level converter based IUT system.
Background of Reliability Assessment

The buzzword of any industry that provides products or services to its customers is undoubtedly
reliability. Without quantification, it would be very difficult to explain the term reliability.
For example, if one circuit breaker failed thousands of operations after its estimated lifetime and
another circuit breaker of the same kind failed after just hundreds of operations, which one of the
two circuit breakers is more reliable? Without quantification, the question is difficult to answer,
because both circuit breakers are of the same kind. A formal definition of reliability can be given
as the probability that a product or service will operate properly for a specified period of time
(design life) under the design operating conditions without failure [22].
A products life cycle can be explained using a typical bathtub curve, which shows the
relationship between the failure rate of the product (or service) versus time.
4-1
Failure Rate
Reliability Assessment of the Proposed IUT System
Solid-State
Hybrid
Traditional
Burn
In
Useful Life
Wear Out
Number of hours of
Operation
Figure 4-1
Typical Reliability Bathtub Curve
From Figure 4-1, it could be seen that there are three stages in a product (or service) life cycle:
Burn-in stage: It is also commonly known as infant mortality. This is the product inception
stage, where there are many failures. But as time progresses, we can see a sharp decline in
the failure rate and it settles down to a period of constant failure rate.
Useful life: This is the period of useful life of the product where the failure rate is almost a
constant.
Wear out: This is the final stage of the life cycle of the product. As the product reaches its
end-of-life cycle, we can see that there is a sharp inclination in the failure rate of the product.
In Figure 4-1, there are three different curves, one each for traditional, hybrid, and solid-state
devices. The traditional device has a lower failure rate of all the three kinds of devices, whereas
the hybrid device has little higher failure rate than the traditional one. The hybrid and the
traditional devices still may contain mechanical parts and after a certain number of operations
will start to wear out, following the bathtub model. But the solid-state device has a constant
failure rate for infinite time, meaning that there is no particular period where the solid-state
device needs any maintenance. Though the constant failure rate () for the solid-state device is
higher than the other two categories, it has less or no maintenance and in the long run will not
wear out at the rates of the other two types of devices.
Quantifying Reliability
Reliability can be mathematically depicted as a probability distribution function given by the
- t
equation R(t) = e . The unreliability function or the cumulative distributive function of failures
F(t) is given by the equation F(t) = 1-e-t. The failure function F(t) gives the probability of
equipment or devices that will fail after a certain number of hours of operations. Therefore, we
can see that the sum of the reliability and unreliability function is given by R(t)+F(t) = 1.
4-2

In predicting the reliability of the entire system, it is necessary to understand the different units
that represent the level of reliability of any system.
Failure rate () is defined as the anticipated number of times an item will fail in a specified time
period. The unit for failure rate is taken as failure per million hours (fpmh). For electronic parts,
this value is constant over an infinite period of time.
The term mean time between failure (MTBF) is defined as the passed time before a
component, assembly, or system fails under the condition of a constant failure rate. The value of
MTBF corresponds to the uninterrupted reliable operation for that time. This factor apparently
indicates the inverse of the failure rate. The unit for MTBF is hours. The mean time between
failures for the devices with constant failure rate is given by the following equation:
MTBF = R(t )dt = e t dt =

0
Where R(t) is the reliability function.
If, for example, the failure rate of a device, say a transformer, is = 5 failures per million hours
-3
or 43.8x10 failures per year, then the MTBF is 200,000 hours or 22.8 years. This does not mean
that the average time between two failures will be 22.8 years! But it helps in determining the
probability of operation without failure given by the following reliability equation:
R (t ) = e t ,
Where R(t) is the reliability of the device.
*
= e 1 = 36.8% . So an MTBF of 22.8 years means that for a

When t = MTBF, then R (t ) = e
period of 22.8 years, 36.8% of the components of the device with constant failure rate will
continue to operate failure-free. The reliability column in Table 4-1 gives an idea of the
percentage of the components that would operate failure-free with respect to their number of
years of operation. The failure function shown in the table gives the percentage of devices that
would fail after certain years of operation. For example, after five years, 19.67% or nearly 20%
of the devices with constant failure rate would have failed in the transformer.
4-3

Table 4-1
Reliability of Components Versus Number of Years of Operation of the Components
Reliability, R(t) = e-t,
=43.8x10-3 Failures per
Year
Number of Years of
Operation,
t (Years)
Failure Function
F(t) = 1-R(t)
100.00%
0.00%
95.71%
4.29%
91.61%
8.39%
87.69%
12.31%
83.93%
16.07%
80.33%
19.67%
Let us take as an example two transformers and their failures with respect to their operational
years. Consider a transformer (say transformer 1) with a failure rate of =5fpmh or =0.0438
failure per year (MTBF = 22.83 years) and another transformer (say transformer 2) with a failure
rate of =0.025 failure per year (MTBF=40 years) as given by the IEEE Gold Book [23]. Figure
- t
4-2 shows the failure function F(t), which is given by F(t) = 1-e , for the two transformers. From
the figure we can see that more parts fail in transformer 1 than transformer 2 for the same
number of years of operation.
100%
90%
80%
Transformer-1
70%
F(t)
60%
50%
Transformer-2
40%
30%
20%
10%
0%
0
10
15
20
25
30
35
Time (Years of Operation)
Figure 4-2
Cumulative Distribution Failure Function F(t) for the Two Transformers
4-4
40
45

In order to estimate the failure rate and subsequently the reliability of any system, some
standards can be used. There are many standards established so as to assist in evaluating the
reliability of the system, which are discussed in the following paragraphs.
Various Reliability Standards

There are some standards that can be followed to predict the reliability of any system. Inevitably,
each of the standards has some limitations and none of them is completely suitable to estimate
the reliability of a system. The major standards are:
MIL 217
Mil 217 is the most common and widely used standard to measure the reliability of a system.
Initially, this standard was introduced for military and aerospace engineering in the defense
industry, but later on, commercial companies started to use it because of its worldwide
acceptance and compatibility. The most recent version of this standard is depicted in MILHDBK-217 revision-F, notice-2, which was released in February 1995. This version of MIL-217
includes failure-rate models for numerous electronic components such as integrated circuits,
transistors, diodes, resistors, capacitors, and other discrete components used in power electronics
circuits.
Bellcore
AT&T Bell Laboratories introduced this reliability model to predict the reliability in
telecommunication applications. This standard was derived from the MIL-217 standard to make
it compatible and more useful in telecommunication industries. Many commercial electronic
product companies are using Bellcore these days becauase it is more suitable than MIL-217.
Currently, this standard is maintained by Telcordia Technologies Inc.
NSWC (Naval Surface Warfare Center)
This reliability prediction model is commonly used for mechanical components and systems.
This standard involves different kinds of models for a wide range of mechanical components to
predict the failure rate caused by temperature, stresses, flow rates, and various other parameters.
In this standard, it is possible to model various mechanical devices such as springs, bearings,
seals, and motor brakes.
RDF 2000
This standard is used in France for reliability prediction in the telecommunication sector. RDF
2000 introduces a new approach for modeling the failure rate of a system. While determining
failure rate, this standard considers cyclic profiles and their applicable phases. Moreover, RDF
2000 provides the capability to handle the PCB in a very unique way.
PRISM
This standard incorporates system reliability assessment methodology developed by the
Reliability Analysis Center (RAC). PRISM is suitable for both military and commercial use. It
involves the NPRD (non-electronics parts reliability) and EPRD (electronic parts reliability)
standard databases of failure rates. This standard enables the use of process grading factors,
predecessor data, and tests of field data.
4-5

Comparison of Different Standards

Although there are several models available for reliability prediction, each of them is designed to
work for a particular application. Thus, a model cannot be characterized as a good or bad one for
all kinds of applications. However, different models can be mixed to yield a better result.
Table 4-2 offers a comparison of the different models.
Table 4-2
Comparison of Various Reliability Models
Reliability
Standard
Originating Country
and Application
Advantage
Can be applied in
preliminary design stage or
in the complete system to
measure the reliability.
USA
Mil 217
Commercial &
Military
It includes models for a

wide range of parts.
Predictions can be done in
a broad range of
environment types.
Disadvantage
It does not consider some factors

such as burn-in data, lab testing
data, field test data, designer
experience, and wear out, which can
contribute to failure rate.
Some very essential part types such
as gyroscopes, batteries, heaters,
coolers, and computer systems are
not available in this standard.
It is well known and world

wide accepted.
USA
Analysis can be done

ranging from preliminary to
complete design by
changing calculation
methods.
Bellcore
Commercial
Considers burn-in data, lab

testing data and field test
data.
Well known and accepted.
4-6
Predictions can be done only in a

limited number of environment types.
It only considers electronic parts.
It has fewer part models compared
to MIL 217.
It does not consider the factors such
as designer experience and wearout.

Table 4-2 (cont.)
Comparison of Various Reliability Models
Reliability
Standard
Originating Country
and Application
France
Advantage
Disadvantage
It includes models for a

wide range of parts.
It considers only electronic parts.
RDF 2000
Telecommunications
USA
PRISM
Military
It handles the PCB in a very

unique way.
It is available only in French.
This standard has the

ability to use the process
grading factors,
predecessor data, and test
of field data.
It can model only a limited set of

parts.
It considers only electronic parts.
It cannot model hybrid system.
& Commercial
USA
NSWC
Military
& Commercial
This standard incorporates

the NPRD / EPRD
database.
It has the capability to
analyze a broad range of
mechanical parts such as
seals, springs, solenoids,
and bearings.
Its relatively newer and still getting

acceptance.
It can only model mechanical parts.
Reasons for Choosing MIL 217

There are many reasons for choosing the MIL 217 to predict the reliability of the IUT system.
The key features of this standard make it suitable for most electronics companies. The reasons
for choosing MIL 217 as a reliability prediction tool for the IUT are as follows:
It is the most accepted reliability prediction model worldwide for electronic components.
MIL 217 is used both by commercial companies and the defense industry.
MIL 217 involves different kinds of models to cover a broad range of electronic components
and part types such as discrete semiconductors, integrated circuits, resistors, capacitors,
inductors, relays and switches, and other different kinds of components. This standard also
provides the ability to model the PCB.
This standard provides the option to predict the reliability in different operating environment
affected by heat, humidity, air pressure, and so on. In a nutshell, it is possible to characterize
the system in extreme ambient conditions.
MIL 217 has the advantages to predict the reliability of a preliminary design as well as a final
improved design by progressing from parts.
4-7

Demerits of MIL 217

MIL 217 suffers from the unavailability of new electronic devices that might be used in a
project. For example, in this particular project, MIL217 could not provide information for parts
such as the IGBT and varistor.
The calculations performed by MIL 217 are sometimes more pessimistic, and generally more
parts parameters are required for accurate calculation. The number of parts parameter required is
greater than other standards.
The prediction accuracy in MIL 217 depends upon the amount of compiled data. These data take
a long time to collect, particularly data from the space environment. Because of this longer time,
the rapid development of the technology limits the ability to collect sufficient data for any
particular technology.
MIL 217 also does not consider some factors such as burn-in data, lab testing data, field test data,
designer experience, and wear out, which can contribute to failure rate.
Application of MIL 217 in Various Stages of IUT

Reliability analysis of the IUT requires several stages of refining design in order to come up with
a higher reliability prototype. The final product form is preceded by the design and lab prototype
stages. The different stages where IUT reliability is measured are:
Design stage
Laboratory prototype stage
Final production stage
Design Stage
Reliability prediction for the IUT starts with the design stage and uses the MIL 217 standard. In
the reliability test, substantial amounts of simulation data were found for different parts of the
system. Seven major blocks are integrated to build the overall IUT: Five blocks are connected in
cascade, and two blocks are connected parallel at the output stage to generate different values of
output voltage, both ac and dc. Naturally, all the stages in the work chain are not the same. The
different stages are high-voltage rectifier, dc bus link, moderately high voltage inverter, highfrequency transformer, low-voltage high-frequency rectifier, low-voltage inverter, and so on. All
the stages differ from each other in operating voltage or frequency range of operation. The
devices used in the different stages are also different, and thus they have different reliability and
MTBFs during their life cycle. To predict the reliability of this kind of hybrid system is not easy,
and this difficult task has been accomplished with the help of Item Toolkit, a software that
uses the MIL 217 standard to predict the reliability of a system.
4-8

Lab Prototype Stage

This measurement step starts when the lab prototype of IUT is completed. The measurement
involves some key factors such as burn-in data, lab testing data, field test data, designer
experience, wear out, and so on. As discussed earlier, MIL 217 could not predict reliability when
these factors are present in the system. A convenient standard should be figured out to get
reliability data during this stage.
Final Production Stage
Reliability analysis in this stage reflects the ultimate results of the actual performance.
MIL 217 Analysis Methods

There are two major kind of reliability analysis followed in MIL 217: 1) parts count analysis and
2) parts stress analysis.
Parts Count Analysis
This technique is normally used when accurate design data and component specifications have
not yet been determined, when the design is in a very preliminary stage. Parts count analysis
helps to give an idea of system reliability at the beginning of the project, for example during the
proposal and bid process time. The advantage of this method lies in the fact that it requires a
minimum amount of data. The generic formula for parts count analysis follows and uses a
different base failure rate or generic failure rate for each MIL 217 operational environment. The
formula can be stated as:
i=n
Equip = Ni (gQ ) i
Eq. 4-1
i =1
where
Equip
= Total equipment failure rate (number of failures/106 hours)
= Generic failure rate for the ith generic part (number of failure / 106 hours)
N = Quantity of the ith generic part

= Quality factor for the ith generic part
i
n = The number of different generic part categories in the equipment

The failure rate calculated from the above expression is normally more conservative than the
results from the parts stress analysis method. The parts count analysis method does not factor in
the numerous variables and uses the worst-case generic or base failure rates and pi factors ( Q ).
To illustrate the parts count analysis, let us consider an example of estimating the failure rate of a
simple discrete semiconductor device, say a low-frequency diode. The failure rate of the device
4-9

i =n
is given by Diode = Ni (gQ ) i . The default values for calculating the failure rate of the
i =1
equipment is given in Appendix A of the MIL 21 handbook7. Let us consider just one diode used
in switching operation, with JANTX quality, in a ground benign environment, with a junction
o
temperature of TJ = 50 ( C). Then the values as given in the MIL 217 handbook are as follows:
n=1
Q = 1.0
g = 0.00094
N=1
So Diode= 1*0.00094*1 = 0.00094
Diode_pc = 0.00094 fpmh.
We can see from this example that parts count analysis helps in estimating the ballpark failure
rate of the system under consideration. Suitable components can then be selected so as to bring
down the value of the failure rate before doing further analysis with the parts stress method.
Part Stress Analysis
This method is used when the design is near completion, and adequate data are available
regarding the detailed part list, component stresses, and the balance of the plant. In the IUT
design, the real values of the components that are going to be used were known beforehand, so
the parts stress analysis was directly applied to the system without going through the parts count
analysis.
By component stresses, this method is capable of producing results indicating the actual
operating conditions of the system for different temperatures, voltage, current, and power levels.
The MIL 2 17 parts stress analysis method categorizes the parts in major groups and then by
subgroups within categories. For the IUT design, reliability for the individual parts was
computed first, and then reliability of the individual blocks as well as the complete system was
measured.
Let us consider the same example used in the parts count analysis to estimate the failure rate of a
single low-frequency diode. The failure rate as a function of various parameters is given in the
MIL 217 handbook. In this case, the failure rate function for the diode is given by:
Diode = b T S C Q E
where
fpmh (failures per million hours)
b = Base failure rate

T = Temperature factor
S = Electrical stress factor
C = Contact construction factor
Q = Quality factor
E = Environmental factor
7 Military Handbook Reliability Prediction of Electronic Equipment, MIL-HDBK-217F, 2 December 1991.
4-10
Eq. 4-2

According to the MIL 217 standard parts count analysis, values for the factors listed above are
used to estimate the failure rate. Let us consider the same diode (as in the parts count example)
used in a switching operation, with JANTX quality, in a ground benign environment, with a
junction temperature of TJ = 50 (o C), with an electrical stress of 0.8, and having a metallurgically
bonded construction. The parameter values are given by:
b = 0.0010
T = 2.2
S = 0.58
C = 1.0
Q = 1.0
E = 1.0
The overall failure rate of the diode is then given by
Diode = b T S C Q E
Diode= 0.0010*2.2*0.58*1.0*1.0*1.0
Diode_ps= 0.00128 fpmh
It can be seen that the value of failure rates determined by the parts count (Diode_pc = 0.00094) and
parts stress (Diode_ps= 0.00128) methods are a little different. This difference occurs basically
because, in the parts stress analysis, the actual values of the parameters are used instead of the
default values used in the parts count analysis.
Reliability Analysis of the Proposed IUT Design Using Item Toolkit

A block diagram representation of the IUT and the components used in the IUT design are
described in this section. Figure 4-3 shows the actual IUT circuit model, and Table 4-3 shows the
list of components used in the system. A simple block diagram representation is shown in
Figure 4-4. In order to evaluate the reliability of the IUT system, a software tool called Item
Toolkit was used. The reliability standard chosen to analyze the IUT model was MIL 217
because of the merits it has over other standards, as discussed earlier.
4-11

6.6 kV
Sr11
Sr21
Si1
Sr12
Sr22
Si2
Sr13
Sr23
Si3
Lf Sr14
Sr24
Si4
120V
400 Hz
8 kV
16.6 kVA
120/240 V
60 Hz
Sr11
Sr21
Si1
Sr12
Sr22
Si2
Sr13
Sr23
Si3
Sr14
Sr24
Si4
-6.6 kV
1r
5
3
4
Isolated
DC/DC
converter
+
48 Vdc
_
1i
Figure 4-3
Schematic of Intelligent Universal Transformer Circuit Model
7.2 kV
15 kVA
1.r
1.i
Note:
1 = Five-level neutral-point-clamped converter
2 = DC capacitor bank (4 in series)
3 = High-freq transformer
4 = Rectifier & filter circuit
5 = Full-bridge inverter with split DC buses
6 = Full-bridge inverter with single DC buses
7 = Buck converter
8 = Controller
Active Front End Rectifier Controller
High Frequency Inverter Controller
Secondary Output Controller
Communication Controller
120 V
120 V,
400Hz
48 VDC
Figure 4-4
Block Diagram Representation of Intelligent Universal Transformer (IUT) Design
4-12
120 V

Table 4-3
Components Used in the IUT Design
Sub-circuit
Component
IGBT
Values
6.6 kV, 10 A
Quantity
16
Anti-parallel diode
16
Blocking diode
24
1r High-voltage rectifier
2 High-voltage dc link
1I High-voltage Inverter
3 - Isolation transformer
4 - Rectifier filter circuit
5 Full-bridge inverter with

split dc bus
Line inductor
0.475 H
Capacitor
26 uF/Capacitor
IGBT
6.6 kV, 10 A
Anti-parallel diode
Blocking diode
12
High-frequency transformer
Diode
LC filter
IGBT
Anti-parallel diode
DC capacitor
LC filter
6 Full-bridge inverter
without split dc bus
C = 4.7 mF,
L = 126 uH
C = 25 uF;
L = 171 uH
IGBT
Anti-parallel diode
LC filter
Capacitor
C = 25 uF;
L = 171 uH
An Introduction to Item Toolkit

Item Toolkit is a suite of comprehensive prediction and analytical modules. It uses globally
recognized reliability standardssuch as MIL 217, Bellcore/Telcordia, and RDF 2000and
methodologies to analyze components, systems and projects.
4-13

Project
Project View Section

System
Block
Components
Data Entry Section

System View Section
Figure 4-5
Snapshot Showing Different Regions in the Item Toolkit
In order to evaluate the reliability of the system using Item Toolkit, the system has to be divided
into blocks, and then each block can be separately implemented in the Item Toolkit. The key
elements that should be known in order to evaluate the reliability of the system in the Item
Toolkit are as follows:
Components: Components are the basic building units. The prediction modules of the Item
Toolkit will give the failure rates of components in accordance with specified standards,
which in this case is MIL 217 standard.
Blocks: Blocks are logical units that are comprised of many components. The reliability of
the block is the sum total of the reliability of all the components in the block. Blocks (or
units) are used to break the system down into smaller, more manageable pieces, forming an
overall hierarchical breakdown of the system under consideration.
System: A system can be described as a single device or a group of components (blocks) that
are assembled together to perform a function. The Toolkit can be used to analyze the
performance of the system in the design or production process.
Project: A project can be a single system or a combination of multiple systems undergoing a

reliability prediction analysis. For example, a project could be a printed circuit board or a
more complex project such as a piece of medical diagnostic equipment composed of many
individual internal systems, such as a power supply, monitor, switches, and PC boards.
4-14

To illustrate various elements of the Item Toolkit, let us consider an example as shown in
Figure 4-5. In this example:
Project occupies the highest level in the hierarchy of elements in the Toolkit software. In this
case, the project is the IUT Design Project. If there is more than one project, they will be
displayed at the project view section.
System is the next highest level in the hierarchy of representation in the Toolkit software. In
this example, IUT system is the system-level element, which includes the failure rate (FR)
of all the blocks and components.
Block is a logical unit that comprises of different components of a device. In this example,
the HV Inverter block consists of two different components, diode and transistor (IGBT).
The failure rate of any block is the sum of the failure rates of individual components.
The Item Toolkit has three major sections where the information about the system can be input to
the software. The snapshot of the Item Toolkit in Figure 4-5 shows the different sections of the
software. The three sections are:
Project view section: This section contains the information about the project under study. A
project may consist of several systems, and each system is shown under the project. In this
example, the project is MIL-217 Systems, whereas the system is IUT Preliminary
Model. The failure rate shown here is the overall failure rate of the system.
System view section: This is the main section where the blocks and the components that are
relevant to the system are added. Depending upon the information provided by the user, the
Item Toolkit automatically evaluates the failure rate of the components.
Data entry section: The parameters needed for each component for the Toolkit to evaluate
the failure rate and other reliability indexes are entered in this section. For parts count
analysis, the Toolkit itself provides default values to the parameters based on the reliability
standard chosen. But for parts stress analysis, the user has to provide parameter values based
on the application and environment conditions.
The data-entry section has two views, dialog and grid. The dialog view has three tabs, which are
general, physical, and application tabs, respectively. The general view window lets the user to
input basic details about the component. It should be noted that the basic details required varies
from component to component. Figure 4-7 and Figure 4-8 show the various tabs for the IGBT
component used in block1r (shown in Figure 4-6).
4-15

Figure 4-6
Section of IUT Schematics Showing Block 1r
Figure 4-7
Dialog Window of Item Toolkit Showing the General View (Left) and Physical View (Right)
Section
4-16

Figure 4-8
Dialog Window of Item Toolkit Showing the Application View Section
Figure 4-9 shows the grid window of the Item Toolkit. The grid window allows the user to view
the results of the reliability analysis in a tabular fashion.
Figure 4-9
Grid View of Item Toolkit Showing the Blocks and Their Failure Rate
4-17

Parameter Values Used in the Reliability Analysis

As mentioned earlier, each component has different parameters, and the parameter values of the
same components differ from each other depending upon the block to which they belong. For
example, the parameter values of the component IGBT used in block 1r (high-voltage rectifier)
will be different from the parameter values of IGBT used in block 1i (highivoltage inverter).
Table 4-4 through Table 4-8 give the default parameter values required by all the components
used in the intelligent universal transformer (IUT) design, such as IGBT, capacitor, diode,
transformer, and inductor. The specific values required by the components in different blocks are
added as per the model design.
Table 4-4
Parameter Values Required by the Component Diode
4-18

Table 4-5
Parameter Values Required by the Component IGBT
4-19

Table 4-6
Parameter Values Required by the Component Capacitor
Table 4-7
Parameter Values Required by the Component Transformer
4-20

Table 4-8
Parameter Values Required by the Component Inductor
Results of Reliability Analysis

The results of the IUT reliability prediction are shown in Table 4-9. The failure rate of the
overall IUT system was found to be 21.407 failures per million hours (fpmh). The mean time
4
between failure (MTBF), which is the inverse of the failure rate, was found to be 4.67x10 hours
(approximately 5.3 years).
The table also shows the contribution of each block as a percentage of the total failure rate of the
entire system. It should be noted that the block that contributes most to the total system failure
rate is the high-voltage rectifier block, with a share of around 46%. Voltage stress experienced
by the IGBTs at the high-voltage side may be a cause of the high failure rate for the voltage
rectifier block.
4-21

Table 4-9
Results of the Reliability Prediction of IUT Design Using Item Toolkit
Contribution (%)
Block
Number
Name
1R
High-voltage rectifier
10.101
47.183
1I
High-voltage inverter
5.050
23.591
High-voltage dc link
0.048
0.223
Transformer
0.183
0.855
Rectifier and filter circuit
0.145
0.677
Full-bridge inverter with split

dc bus
3.387
15.822
Full-bridge inverter with single

dc bus
2.493
11.648
21.407
100.000
Total
Total Block Failure Rate

(fpmh)
Figure 4-10 gives a pictorial representation of the reliability analysis results. It can be seen that
Block 1R (High Voltage Rectifier) is the major contributor for the total system failure rate.
Figure 4-10
Failure Rate of Different Blocks of IUT
4-22

The mean-time-between-failure is the inverse of the failure rate and is expressed in the unit of
hours. The mean time between failures of the total system is close to 46700 hours (5.33 years).
Figure 4-11 shows the contribution of failure rate of each block towards the total failure rate of
the system.
Figure 4-11
Contributions of Each Block of IUT Towards Total Failure Rate of the System
ABB Power Electronics-Based Distributed Transformer

The ABB power electronics-based distributed transformer consists of three distinct stages, an
input stage, an isolation stage, and an output stage. The schematic of the ABB design is given in
Figure 4-12. The component list of ABB is given in Table 4-10.
4-23

Figure 4-12
Schematics of ABBs Power Electronics-Based Distributed Transformer
Table 4-10
Component List of ABB Design
Component
Value
Quantity
Lin
417 H/10 A
12
Lbst
2.2 mH /10 A
12
Cout
144 F/1.2 kV
12
MOV
720 V rms
12
8.6 kV rms
IGBT
1.7 kV/50 A
12
Boost diode
1.6 kV/30 A
12
Rectifier diode
1.6 kV/30 A
48
Free-wheeling diode
1.7 kV/50 A
48
Rectifier diode
1.2 kV/30 A
48
Input Stage
Isolation Stage
4-24

Table 4-10 (cont.)
Component List of ABB Design
Component
Value
Quantity
IGBT
1.7 kV/50 A
48
Transformer
5 terminals
12
Cdc
2 mF/350 V
Cacout
100 F/ 250 V
Lout
375 H/ 100 A
Free-wheeling diode
1.2 kV/200 A
IGBT
1.2 kV/200 A
Output Stage
In the input stage8, the primary voltage is divided equally between the input stage modules. Each
modules voltage is rectified using a unity-power-factor rectifier. Each isolation stage module
generates a high-frequency square wave from the incoming dc, transforms and isolates it, and rerectifies the transformer output. The bipolar dc outputs can then be connected in parallel to
supply the output stage. The series-to-parallel connection provides the bulk of the voltage
reduction. The output stage converts the resulting bipolar low-voltage dc into single-phase ac
with a groundable mid-tap.
The schematics of the IUT design can be reorganized into three stages as shown in Figure 4-13,
so as to assist in comparing the two systems. The input stage of the IUT now consists of blocks
1R and 2, the isolation stage consist of Blocks 1I, 3, and 4, and the output stage consists of
Blocks 5 and 6. Essentially, the input, isolation, and output stages perform similar operations, as
mentioned in the above design.
8 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 17, NO. 2, APRIL 2002, A power electronics based
distribution transformer, Edward R. Ronan, Scott D. Sudhoff,, Steven F. Glover, and Dudley L. Galloway.
4-25

Input Stage
Isolation Stage
Output Stage
Figure 4-13
Schematics of Intelligent Universal Transformer Divided Into Three Distinct Sections
Table 4-11 gives the failure rate of the ABB system as estimated by the Item Toolkit software.
The isolation stage has the highest failure rate, which contributes to nearly 67% of the total
system failure rate. This can be attributed to the fact that the number of components in this stage
is more than in the other two stages. It should be noted that the failure rate of a system is the sum
total of the failure rate of the individual components that make up the system.
Table 4-11
Results of the Reliability Prediction of ABB Design Using Item Toolkit
Block Name
Contribution (%)
Total Block Failure

Rate (fpmh)
Input stage
18.00
27.44
Isolation stage
43.82
66.78
Output stage
3.79
5.78
Total failure
rate
65.61
100
Comparison of Results of Both Designs

From the Table 4-12 it can be seen that the total number of components used in the ABB design
was almost nearly 100% more than that of the IUT design. The failure rate of the ABB design
was 65.61 fpmh, whereas the failure rate of the IUT design was found to be 21.41 fpmh. As
mentioned before, the failure rate of a system is the sum total of the failure rates of the individual
components that make up the system. So, if the number of components in a system is more, then
4-26

one may expect a higher failure rate. However, the failure rate also depends on the nature and
type of the component. For example, the failure rate of the diode is less than that of the IGBT,
according to MIL 217 standards. Hence, depending on the type of the component used, the
failure rate of the system may vary. This explains the fact that though the number of components
used in the ABB design is twice that of the IUT, the failure of the ABB is nearly three times
more than that of the IUT design.
Table 4-12
Comparison of Total Components Used in ABB and IUT Design
S. No.
Block Name
ABB
Input stage
121
61
98.36
Isolation stage
156
34
358.82
Output stage
14
22
-36.36
291
117
148.72
Total Components Used
IUT
Percentage
Difference
Table 4-13
Comparison of the Failure Rates of ABB and IUT Design, Block-Wise
S. No.
Block Name
Failure rate
(fpmh)
Failure rate
(fpmh)
ABB
IUT
Percentage
Difference
Input Stage
18.00
10.15
69.97
Isolation Stage
43.82
5.38
712.99
Output Stage
3.792
5.88
-35.62
Overall Failure Rate
65.61
21.41
206.45
The mean time between failure (MTBF) for the IUT and ABB design are given below:
MTBFIUT = 1/ = 1/(21.41*10-6) = 45725 hours or 5.33 years
MTBFABB = 1/ = 1/(65.61*10-6) = 15421 hours or1.74 years
The MTBF of the IUT is greater than that of the ABB design; hence there will be fewer failures
in the IUT design for the same number of years of operation. Figure 4-14 shows the cumulative
distribution function for failure F(t), which is given by F(t) = 1-e-t. F(t) gives the probability of
failure of the system over a given period of time t. The figure shows the F(t) for three
4-27

transformers: 1) IUT, 2) ABB, and 3) traditional transformer. The mean time between failure of a
traditional transformer is taken as 40 years, as per the IEEE Gold Book [23]. For example, after
the completion of fifth year in service, the probability of failure for the ABB system is around
95% and for IUT system is approximately 60%, whereas for the traditional transformer it is
around just 15%.
C u mu la tiv e Fa ilure D istrib ution of IU T , AB B a nd
T ra dition al T ran sform er D e sign
120%
100%
A BB
F(t)
80%
IUT
60%
T raditional
T rans fo rmer
40%
20%
0%
0
10
15
20
25
30
35
40
Time (Y e ars o f Op eration )
Figure 4-14
Cumulative Distribution Function of Failure Function F(t) for the IUT, ABB, and Traditional
Transformer
Figure 4-15 shows the comparison of the failure rates of the IUT and ABB design on a stage-bystage basis. It can be seen that even though the failure rate of IUT is greater than the ABB design
in the output stage, overall the IUT design has a lower failure rate than the ABB design. The IUT
design involves fewer parts, and the cumulative failure distribution of the IUT is better compared
to the ABB design. Hence, from the above discussion of the results, it can be seen that, on the
whole, the IUT design is better than the ABB design.
4-28

Figure 4-15
Comparison Showing the Failure Rate (Failures per Million Hours) of IUT Design and ABB
Design
4-29
5
CIRCUIT DESIGN AND OVERALL COST ESTIMATION
This section provides the overall cost estimates of the proposed IUT system based on existing
component costs and estimated component costs. Complete listings of all parts, including
potential vendors, and its associated costs for the associated PCBs, are also provided.
The entire IUT requires numerous schematic circuits and associated PCBs. Figure 5-1 shows the
partition of circuit boards and major magnetic components. These circuit boards and key
magnetic components include: (1) AFE power circuit, (2) HV gate drive circuit, (3) gate drive
interface circuit, (4) sensor conditioning circuit, (5) 60-Hz inverter circuit, (6) 400-Hz inverter
and dc/dc converter circuits, (7) high-voltage, high-frequency transformer, (8) boost inductor, (9)
DSP board for M-level converter, and (10) DSP board for inverters. The two DSP boards can be
purchased off-the-shelf, and the rest of 6 circuit boards need to be designed and laid out. In
additional to these circuit boards, the IUT also needs a high-frequency transformer, a boost
inductor, and auxiliary power supplies. The cost estimation in the following sections focuses on
the six circuit boards assuming that the DSP boards and auxiliary power supplies can be
purchased off-the-shelf.
(1) M-level converter
SA1
(8)
SB1
SA2
Sa1
(6)
C1
SB2
400 Hz
Inverter
Sa2
vin
DC/DC
Converter
(7)
B
SA1
SA2
SB1
C2
SB2
Sa1
(5)
Sa2
(2) HV-Gate drives

optical link
(3) Gate drive interfaces
(4) Sensor
conditioning
(10) DSP board 2
(9) DSP board 1

Figure 5-1
Partition of Circuit Boards and Major Circuit Components
5-1

Circuit Design and Overall Cost Estimation
The cost estimation procedure is to start with schematic circuit diagram design and select all the
circuit components. The source and price of these circuit components are identified through Web
sites and their vendors. Because the bench prototype requires only a small quantity of parts, the
price is generally much higher as compared to the mass production price. It is not a surprise to
see 5 to 10 times cost reduction when the cost estimation is based on large-quantity production.
However, the cost estimation in the following paragraphs gives a baseline and initial idea about
major cost items and overall system cost of this new-generation power electronics-based
distribution transformer.
Active-Front-End Power Circuit

Given the availability of high-voltage devices today, two active-front-end power circuits can be
designed: (1) three-level, 4.16 kV, 16.6kW AFE converter and (2) five-level, 8 kV, 16.6 kW
AFE converter. Their costs are estimated separately. The entire power circuit contains two-phase
legs for the full-bridge AFE converter and one phase leg for the half-bridge dc/dc converter.
These phase legs all share the same high-voltage dc bus capacitors.
The HV IGBT devices are used as the switching device as the baseline estimate. Possible cost
reductions of these HV IGBTs will depend heavily on the quantity. The small-quantity purchase
price is $200 for a quantity less than 12. However, when the quantity reaches a few hundred, the
price can go down to $120. In fact, the majority of the cost goes to packaging. When the quantity
reaches more than 100,000 units, the packaging cost drops dramatically, and an additional five to
10 times cost reduction is possible through negotiation. These HV IGBTs, in fact, dominate the
entire IUT cost. Considering that there are 24 devices in one power circuit, the total device cost
is $2,880, more than 50% of the entire IUT cost.
For a lower-voltage system such as the 4.16-kV system, a three-level converter can be used, and
the number of devices drops to 12. This represents significant reduction in parts count and the
cost. Thus the cost of a three-level AFE using the same device is also estimated. Table 5-1 and
Table 5-2 show the bill of materials for the power circuit of a three-level 4.16-kV AFE converter
and five-level, 8-kV AFE converter, respectively.
5-2

Table 5-1
Bill of Materials for Three-Level 4.16-kV Power Circuit Board
Type
Part Type
Source
Description
Footprint
Qty
Price
Film capacitor
Electronic Concept
26uF, 3500V
bulk cap
$120.00
HV Diodes
QRD3310001
Powerex
3.5kV 100A dual
QRD3310001
$540.00
1N6517LL
Voltage Multipliers Inc
5kV 2.2A
DIO15.458.9X3.7
$33.00
Header 3
Digikey
Header, 3-Pin
Gate drive
conn
12
$30.00
Header 2
Digikey
Header, 2-Pin
HDR1X2
$7.50
HV IGBT
Powerex
4.5kV, 60A IGBT
QIS4506001
12
$1,440
PCB
4PCB
Converter
$60.00
PCB
4PCB
Inverter
$30.00
Total
43
$2261
One 3-level full bridge + one 3-level half bridge

Table 5-2
Bill of Materials for the Five-Level 8-kV Power Board
Type
Part Type
Source
Description
Footprint
Qty
Price
HV IGBT
Powerex
4.5kV, 60A
QIS4506001
24
$2,880
1N6517D
5kV 2.2A
DIO15.45-8.9X3.7
36
$198
1N6517D
5kV 2.2A
1N6517LL
24
$132
26uF, 3.5kV
Electronic concept
Capacitor
Bulk cap
$240
Header 3
Digikey
Header, 3-Pin
Gate drive conn
16
$40
PCB
4PCB
converter
$60
PCB
4PCB
inverter
$30
Total
106
$3580
Three 5-level phase legs
HV Gate Drive Circuit

The high-voltage gate drive circuit is much more expensive than its low-voltage counterpart
because of isolation requirement. The gate drive circuit takes DSP control signals and converts
them to high-current driving signals. When IGBT is heavily loaded or short circuited, the gate
5-3

drive will sense it as a fault condition and send a fault signal back to DSP to shut down the
converter. The logic also takes an over-temperature protection signal to incorporate it as a fault
signal that can be sent back to DSP through optical fibers. Each PCB contains two gate drivers.
The major cost items in this circuit are: (1) high-voltage isolation power supply and (2) optical
fiber transmitters and receivers. Table 5-3 lists the bill of materials of the HV gate driver board.
It should be noticed that each five-level phase leg requires four such boards, and the entire fivelevel AFE requires 12 such boards. For a three-level phase leg, it requires two such boards, and
the entire three-level AFE requires six such boards.
Table 5-3
Bill of Materials for the Gate Driver
Type
Part Type
Source
Description
Designator
Footprint
Qty Price
0.1u 50V
Digikey Ceramic cap
C1
C3216-1206
13 $1.755
22u,25V Tantalum
Digikey PCS5226CT-ND
C4
NSPZ-25V 22uF
$4.842
22u,25V Tantalum
Digikey PCS5226CT-ND
C6
NSPZ-16V 22uF
$1.3
47u
Digikey Capacitor
C13
100V 47uF
$0.7
CON2
Digikey Connector
CON1
CON2
$2.5
mur1100
Digikey Ultrafast D/FR1MDICT-ND
D1
D-REC(SMB)
$1.44
20-mA 2.0-V LED
Digikey P956 FIG5 D/67-1103-ND
LED1
LED
$0.42
Con
Digikey Position hole
hole
HOLE
$0
MJD243
Digikey BJT ONSEMI/MJD243
Q1
DPAK-MJD243
$3.78
10
3.3K
Digikey resistor
R1
1206
16 $1.408
11
HFBR-1522
Future
T1
FIBER OPTICAL
$21.75
12
A7805CKTER
Digikey Pos-Voltage Regulator/ TI
U1
uA7805CKTE1
$0.52
5-4
Optical fiber receiver

Table 5-3 (cont.)
Bill of Materials for the Gate Driver
Typ
e
Part Type
Source
Description
Designator
Footprint
Qty Price
13
HCPL-2630
Future
Mouser/512-HCPL-2630S
U2
HCPL-2630
$2.43
14
MC33153D
Newark
Onsemi/mc33153d
U3
SO-G8
$1.48
15
WP06R48D15N Mouser
HV isolated power supply
U5
WP06R
$65
16
A79M05CKTP Digikey
R
Neg-Voltage Regulator /TI U7
uA79M05CKTPR1 2
$1.44
17
Zener diode
D/SMAZ18DICT-ND
Z1
SMB
$0.52
18
MMBZ15VALT1 Digikey
D/MMBZ15VALDICT-ND
Z2
SO-G3
$2
19
PCB
PCB
$15
Digikey
4PCB
One Board with two Gate Drivers
Total
$128
Gate Drive Interface

Between the gate driver circuit and the DSP output ports, an optical fiber based gate driver
interface is needed to transmit and receive the signals. Optical fiber prevents noise triggering and
is most desirable for any high-voltage applications. However, the cost of fiber optic transmitter
and receiver is nontrivial. Thus, in this design, for every two IGBTs, two signal receives are
used, but only one transmitter is used for fault signal transmission. In other words, any IGBT
fault will shut down the converter.
Table 5-4 lists bill of materials for the gate drive interface circuit. Each gate drive interface is
designed to interface with two sets of gate drivers. In other words, for the five-level AFE
converter, it requires six gate drive interface boards, and for the three-level AFE converter, it
requires three gate drive interface boards.
5-5

Table 5-4
Bill of Materials for the Gate Drive Interface
Type
PartType
Description
Designator Footprint
Qty
Price
74AC125
Quad Tri-state Gate 74AC125
SO-14
$0.75
CAP
Capacitor
C1
1206
$0.675
T2521
Optical Receiver
Fault1
HFBR2521 4
$29
Fault
LED
LED1
LED
$0.21
HEADER 14
Connector
MOLEX14 IDC-14
$0.21
4 HEADER
4 Pin Header
Power
DSPCONN 1
$0.5
T1521
Optical Transmitter PWM1
HFBR2521 2
$14.5
Resistor
R1
1206
12
$1.056
AND Gate
U1
DIP14
$0.15
8
9
74HC08
10
MC74HC14AD Hex Inverter SCH
U2
SO-14
$0.15
11
74HC74
Dual D-Latch
U3
DIP14
$0.12
12
DS75452
Dual Drivers
U4
SO-8
$1.3
13
PCB
4PCB
PCB
$10
One board with 4 channels
Total
$59
Sensor Conditioning Circuit

The sensor conditioning circuit provides filtering and scaling functions for the voltage and
current sensor signals. Scaling is to convert the signal voltage level to the analog-to-digital port
voltage range. Table 5-5 lists bill of materials of a sensor conditioning circuit board. Each board
can accommodate two voltage and two current channels. For each five-level AFE, it requires five
boards, and for each three-level AFE, it requires three boards.
5-6

Table 5-5
Bill of Materials for the Sensor Conditioning Circuit
Type
Source
Description Designator Footprint
Qty
Price
Digikey
Capacitor
C1
1206
28
$1.62
Digikey
Connector
J1
SIP2A
$3.00
LEM USA Hall Sensor
LEM1
LEM_LTS25 4
$76.8
Digikey
Potentiometer POT1
POT1
$0.352
Digikey
Resistor
R1
1206
24
$2.112
Digikey
Resistor
RLEM11
AXIAL0.4a 10
$0.88
Digikey
Op-amp
U1
so-14
$2.88
4PCB
One board with 4
receivers
PCB1
$15.00
Total
103
Inverter Circuit
The inverter circuit includes rectifiers on the transformer secondary and a full-bridge inverter.
Major cost items are IGBTs and filter components. If more energy storage is needed on the dc
bus, then more electrolytic capacitors can be added. The circuit board reserves additional space
for the energy-storage capacitors. All the inductors and transformers are designed and prototyped
by the magnetic component supplier. The gate drives are all opto-coupler based and are much
cheaper than the fiber-optic-based gate drives. lists bill of materials of the entire inverter circuit.
5-7

Table 5-6
Bill of Materials for the Inverter Board
Part Type
No
Source
Description
Footprint
Qty
Price
0.1u
Digikey
X7R cap
1206
56
$7.56
33u
Digikey
Electrolytic
cap
SMTD
$12.91
47u
Digikey
Electrolytic
cap
RB.2/.4
$6.46
4.7n
Digikey
X7R cap
axial0.6
$0.14
1u
Digikey
X7R cap
C1400
$0.28
2.2mF, 250V
Digikey
Electrolytic
cap
PanCETH
$100
20u, 250Vac
Digikey
Film cap
EC400u
$0.28
10
DB25
Digikey
Connector
DB25/F
$1.20
11
MURS160T3
Digikey
Ultrafast diode
403A
$2.88
12
MURS120t3
Digikey
Ultrafast diode
403A
$1.44
13
ZM4750ACT
Digikey
Zener diode
DL41
$2.08
14
ZM4733ACT
Digikey
Zener diode
DL41
$2.08
15
P6KE200
Digikey
TVSS
D0.4
$0.65
16
BYV26C
Digikey
Ultrafast diode
Diode0.4
$0.32
17
IN4148
Digikey
Switching
diode
Diode0.4
$0.22
18
50SQ100
Digikey
Schottky diode
DO204
$2.28
19
DIODE
Digikey
Diode
TO247V
$28.00
5-8

Table 5-6 (cont.)
Part Type
No
Source
Description
Footprint
Qty
Price
20
50SQ100
Digikey
Schottky diode
DO204
$1.52
21
IRG4PSC71UD
Digikey
CoPack IGBT
TO247V
$30.00
22
INDUCTOR
LTE
Inductor-DC &
AC
Lrect
$21.00
23
IRF510S
Digikey
MOSFET
D2PAK
$2.40
24
47k
Digikey
Resistor
1206
$0.32
25
10k
Digikey
Resistor
1206
$0.32
26
15k
Digikey
Resistor
1206
$0.32
27
22k
Digikey
Resistor
1206
$0.16
28
2.2k
Digikey
Resistor
1206
$0.32
29
6.2
Digikey
Resistor
Axial0.4
$0.02
30
100
Digikey
Resistor
1206
$0.40
31
9.1k
Digikey
Resistor
1206
$0.09
32
2.4k
Digikey
Resistor
1206
$0.09
33
1Meg
Digikey
Resistor
1206
$0.16
34
1k
Digikey
Resistor
1206
$0.16
35
6.8
Digikey
Resistor
1206
$0.32
36
1m
Digikey
Resistor
BVS-A-R001
$0.16
37
3.6k
Digikey
Resistor
1206
$0.16
38
HCPL316J
Future
Gate driver
SO16
$18.00
39
UC3845N
Future
Control IC
SO8
$2.40
40
TOP_SW
Power
Integration
Topswitch
TO220V
$2.50
41
NEC2501
Digikey
Opto coupler
DIP4
$0.67
5-9

Table 5-6 (cont.)
No
Part Type
Source
Description
Footprint
Qty
Price
42
TL431
Digikey
Voltage ref
TO92
$0.50
43
IR2171
Digikey
Current sensor
SOIC8
$6.40
44
HCPL2530
Future
Opto coupler
SOP8
$3.00
45
XFORMER
LTE
Flyback
GateXfmr
$2.40
185
TRANS
LTE
Flyback
TopXfmr1
$1.20
186
PCB
60 Hz full bridge Inverter with rectifier
$50.00
Total
186
314
Cost Estimate for the 400-Hz Inverter and DC/DC Converter

The 400-Hz inverter and 48-V dc/dc converter are incorporated in one circuit board. Because the
high-frequency transformer already provides isolation, it is not necessary to design an isolated
dc/dc converter. An interleaved two-phase buck converter is adopted for the 48-V dc/dc
converter.
The full-bridge rectifier is connected to the transformer output to provide dc sources for the 400Hz inverter and 48-V dc/dc converter. All gate drives are isolated with opto-couplers. Fault
protection is built-in at the gate drive level to provide the first line protection. The logic inputs
are connected to the DSP board for PWM control.
Bill of materials for the entire 400-Hz and 48-V dc/dc converter is listed in Table 5-7. Major cost
items are the big PCB and the dc bus electrolytic capacitors. Gate drivers and power devices are
also expensive parts. However, the entire circuit cost is much less than the high-voltage board.
Cost Estimate for the Entire IUT

The high-frequency transformer, DSP boards, and auxiliary power supplies are not included in
the above cost estimate. Their prices are estimated as $120, $150, and $100, respectively. The
heat sink, packaging, and protection circuit can be lumped together with a cost of $200. With
inclusion of these parts and the above circuit boards, the material cost of the entire IUT can be
calculated as below.
Table 5-7 lists the price for the individual boards and the total price of the entire three-level 4.16kV IUT. Notice that the assembly and manufacturing cost are not included. However, the parts
cost will be dramatically reduced in large-quantity production.
5-10

Table 5-7
Cost Estimate for the Three-Level 4.16-kV IUT
Part
Three-level power circuit
Price
Quantity
Ext. Price
$2,261
$2,261
$128
$768
$59
$177
Sensor conditioning
$103
$309
60-Hz inverter
$314
$314
400-Hz inverter + 48-V dc/dc converter
$215
$215
HF transformer
$120
$120
DSPs
$150
$150
$100
$100
$200
$200
HV-gate drive
Total
$4,614
Table 5-8 lists the price for the individual boards and the total price of the entire five-level 8-kV
IUT. Notice that the assembly and manufacturing cost are not included. However, the parts cost
will be dramatically reduced in large-quantity production. The cost of the five-level IUT is much
more expensive than that of the three-level IUT even with the same power level due to expensive
semiconductor devices and their associated high-voltage isolation gate drivers. Figure 5-2
compares the cost estimates of individual items for the above design options.
Table 5-8
Cost Estimate for the Five-Level 15-kV IUT
Part
Price
Quantity
Ext. Price
$2,261
$3,580
$128
12
$1,536
$59
$354
Sensor conditioning
$103
$515
60-Hz inverter
$314
$314
HV-gate drive
5-11

Table 5-8 (cont.)
Cost Estimate for the Five-Level 15-kV IUT
Part
Price
Quantity
Ext. Price
$215
$215
HF transformer
$120
$120
DSPs
$150
$150
$100
$100
$200
$200
Total
$7,084
Total Cost of Design
Cost estimate for the 3-level 4.16-kV IUT
Cost estimate for the 5-level 15-kV IUT

DSPs
HF transformer
60-Hz inverter
Sensor conditioning
HV-gate drive
0.00%
10.00%
20.00%
30.00%
(% of total)
Figure 5-2
Associated Cost of Individual Factors in the Two Design Options
5-12
40.00%
50.00%
60.00%
6
UNIVERSAL TRANSFORMER ROADMAP PLANNING
Opening New Frontiers for Next-Generation Transformers

The opportunity to make significant improvements in asset utilization can be found in research
and development of new technology or through radical design modifications. In this report, a
high-voltage multilevel converter-based intelligent universal transformer is proposed for the
next-generation distribution transformer (see Figure 6-1). The proposed IUT design includes
back-to-back, interconnected, multi-level converters coupled to a switched inverter circuit via a
high-frequency transformer. The input of the universal transformer can be coupled to a highvoltage distribution system (such as 4.16-kV), with the use of existing high-voltage silicon
insulated-gate-bipolar transistor (IGBT) devices, and the output of the universal transformer can
be coupled to low-voltage applications (such as 240/120 V). General comparisons of the
proposed design with a conventional transformer are provided below.
6-1

Universal Transformer Roadmap Planning
Table 6-1 through

Table 6-3 summarize the comparison results in terms of their ability to provide:
Improved operational benefits
Enhanced power quality and reliability functionalities
Additional functionalities for expanding services opportunities
The advantages of the IUT technology are:
Possible to integrate additional functionalities (such as power quality and reliability) and
provide options for reactive compensation, dc powering, high-frequency ac powering, and
converting single-phase service to three-phase for powering certain types of equipment.
Using HV-IGBTs at the input stage would significantly reduce price as a result of mass
production.
Possible to implement a standardized transformer design. A standard design will drastically

reduce inventory volume and costs. Reduced core losses.
Possible reduction in weight and size.
Possible to facilitate voltage, current, and power factor monitoring; provide real-time voltage
regulation and facilitate PLC communications and advanced distribution automation
functions.
Possible environmental improvement from conventional transformer.
6-2

The disadvantages of the IUT technology are:

Higher EMI than conventional transformer. Lack of customer acceptance and willingness to
try new untested technologies
6.6 kV
Lf
S r11
Sr21
Si1
S r12
Sr22
Si2
S r13
Sr23
Si3
S r14
Sr24
Si4
120V
400 Hz
8 kV
16.6 kVA
120/240 V
60 Hz
Sr11
Sr21
Si1
Sr12
Sr22
Si2
Sr13
Sr23
Si3
Sr14
Sr24
Si4
5
3
4
Isolated
DC/DC
converter
-6.6 kV
1r
Active Front End

Rectifier Controller
+
48 Vdc
_
1i
High-Frequency
Inverter Controller
Low-Voltage
Inverter Controller
Figure 6-1
Proposed Multi-Converter-Based Intelligent Universal System
6-3

Table 6-1
Operational Benefits An Overall Comparison
Operational Benefits
Conventional Transformer
Multi-Level Design
(HV-IGBT)
Standardized design
Reactive support
Eliminating oil in transformer
Reducing overall weight and size
Magnetic isolation
Advanced distribution automation function
Ability to provide the specified functionality.

Cannot provide the specified functionality.
Table 6-2
Power Quality and Reliability Benefits An Overall Comparison
Power Quality and Reliability Benefits
Multi-Level Design
(HV-IGBT)
Limited, slow in response
Outage compensation
Capacitor-transient protection
Harmonic filtering
Flicker mitigation
Single-phase protection
Voltage balancing
Sag protection
Voltage regulation

6-4

Table 6-3
Options for Expanding Services Opportunities An Overall Comparison
Added Functionalities
Multi-Level Design
(HV-IGBT)
DC power output
400-Hz output
Options for energy storage
Variable-frequency output

Overall Roadmap Technology Characteristics How to Realize the Vision

in the Future
Following the General Trends to Support the Vision Direction
One approach, commonly known as the stage-gateTM model, whose chief characteristic is a
hierarchical flow of possible milestones that would have to be realized, in general, during the
various phases for the development of any new technology is shown in Figure 6-2. Stage gate
breaks the innovation process into a predetermined set of stages, each consisting of prescribed,
multifunctional, and parallel activities. Many leading companies and research organizations have
developed a systematic stage-gate process for moving a new product through the various steps
from idea to launch. Most importantly, they have built the key lessons into the roadmap for
new product success in order to improve the effectiveness and timeliness of their product.
6-5

Concept
Definition
Design, Development,
and Testing
Market Launch
Adaptive Process
Degree of
Uncertainty
in Product
Definition
Traditional Process
Time
Full Production &

Market Launch
Testing & Validation
Prototype
Development
Detail Design
Analysis
Market Analysis
&
Feasibility Study
&
Conceptual Design
STAGE GATE APPROACH
Figure 6-2
A Stage-Gate Approach for New Product Development
Traditional stage-gate or PACE processes (shown on the left in Figure 6-2 where the gates are
transparent) assume that there is little uncertainty associated with the technologies to be
6-6

utilized for product development. The gates can be identified, clearly defined, and planned for,
and their outcomes are known right from the beginning of the development process. In simple
terms, the product development team can see all the deliverables at the gates, because most of
product-development stages are predictable. It should be noted that even though this curve varies
with individual application areas and technologies, it does convey a trend relative to the effects
of realizing the ultimate vision.
From the information provided in the earlier chapters, it is evident that significant opportunity
exists using this sophisticated device called the intelligent universal transformer. With the recent
advances in power electronics, especially in the areas of high-voltage power electronics, the
proposed HV multilevel converter-based universal transformer design (using HV, low-power
electronic devices) is well within the realm of possibility. The primary activity of this years
research was to develop a comprehensive design analysis and verify the functionality of the
proposed high-voltage multilevel converter-based IUT design. This preliminary research is the
first step before embarking on development of the hardware and associated controls for a
prototype universal transformer. This is the most critical stage because the commitment to a
certain design topology will ultimately lead to hardware and controller development and lab
prototype. The next section adopts the traditional stage-gate approach to provide a more refined
EPRI long-term roadmap for the development of the intelligent universal transformer, budget
estimates, and schedule for the development work in 20042007.
Long-Term Research Timeline for Any All-Solid-State Design
The solid-state transformer undoubtedly provides a quantum leap compared to traditional
distribution transformer designs. The risks involved in the solid-state transformer design is much
higher; however, the upside potentials are also enormous. In order for the solid-state approach to
achieve mass-market penetration, the dominating factor will clearly be the total cost of
ownership (TCO). Both first cost and transformer losses dominate the TCO for existing
distribution transformers. Market penetration of any intelligent universal transformer design
for mass application will only be realized if it is comparable to existing distribution transformers.
The solid-state transformer can also meet the niche-market application needs identified in this
report. For these niche-market applications, the cost and efficiency targets for an intelligent
universal transformer are much less stringent. The target TCO for these applications is not
dictated by traditional distribution transformers but by the combination of traditional distribution
transformer and existing technologies such as dc power supplies and dynamic voltage restorers
(DVRs) used for the niche application. Even if the solid-state transformer fails to realize the
TCO target required for mass-market application, it still can be applied to the niche-market
applications targeted by the hybrid approach. Therefore, even with the higher risk involved in the
solid-state design, the preferred research path should aim for the quantum leap in distribution
transformer technology that is possible with the solid-state transformer rather than an
incremental improvement achieved through combination of existing technologies. The overall
technology roadmap characteristics, as shown in Figure 6-3, provide a consolidated summary of
the key technology metrics that are required to realize the development of any all-solid-state
based IUT.
6-7

All-Solid-State
Concept
Prototype Development Technology
All Solid-State Design
Maturity
Conceptual Stage in Development
Risk High
Product Development
5-8 Years
Field Testing
8 Years
Potential Market Drives
Improved PQ, Reduced weight and Size,
Environmentally Friendly Oil-Free
Transformers, Standardized Designs,
Advanced Distribution Automation
Basic R&D for Power Semiconductor Devices

Research Activities should focus on possible
improvements in technology
Reduce conduction and switching losses
Faster switching
Improvement in efficiencies
Improvement in short-circuit capability
Improvement in thermal management to
handle high temperature
Reduce possible voltage balancing
Reduce EMI Levels
Optimize isolation designs to satisfy HV
applications
Low saturation level
Improved Gate design to reduce
noiseSnubber-less operation
Fast turn-on and turn-off capabilities
Ability to withstand high V&I
Improvement in current density
Figure 6-3
A Generic Technology Roadmap for All-Solid-State Based Distribution Transformers
The design proposed by S. Sudhoff et al. among all the other existing designs has got the most
publicity, because the proof of concept was demonstrated by a laboratory prototype for a 10kVA, 7.2-kV-to-240/120-V distribution transformer. Assuming that some of the major
difficulties associated with the ABB design are overcome, the next step could be the
development of a field prototype and field evaluation. An estimate for a commercial product
development and field application could take anywhere from six to eight years. It should be
noted, however, that the technology risk for such solid-state-based transformer design that
incorporates low-voltage power electronics is high (one of the problem associated with this
circuit is reliability due to increased overall component counts), and the time frame will be
greater than for the hybrid approach. Moreover, low-voltage power semiconductor devices are a
mature product. A significant reduction in price in these devices as a result of application in the
distribution transformer market will therefore not be possible. The research plan outlined in the
next section is targeted towards an HV multi-converter-based intelligent universal transformer.
Long-Term Research Timeline for any HV Multi-Converter-Based Intelligent

Universal Transformer Design
Power electronics will be a key element in the solid-state design. There are many ways to guide
the power electronics research. Although the availability of the semiconductor device dictates the
circuit development, history indicates that the success of a semiconductor device is heavily
dependent on the success of the application. Examples are power MOSFETs in switching-powersupply applications and IGBTs in variable-frequency drive (VFD) applications. Blind
development of semiconductor devices without a proper guidance of application and circuit
design would be a wasteful effort. Failure to bring the MOS-controlled thyristors (MCTs) to the
market is the most recent and obvious example. Market demand triggers the need for power
electronics equipment such as power supply and adjustable-speed drives, but the right choice and
development of semiconductor devices enables the development of power electronics equipment.
6-8

Thus, long-term research should have the application in mind and the power electronics circuit as
the core to guide the development of semiconductor devices and other peripherals.
The distribution system has been identified to be the next major target for solid-state power
conversion. Lack of strong initiative and proper long-term research plan has always been a
barrier in new technology development. EPRI, as the leading research institute in the power
industry, is ideally suited to take the first step to initiate the research in this direction based on a
long-term research plan targeting the development of HV, low-power semiconductor switches
and parallel development of circuit topology, controller, and prototype of solid-state distribution
transformer.
Solid-State Designs Using HV Power Electronic Switches and Diodes A Key for
Success
Use of HV power electronics in designing the primary side of a solid-state distribution
transformer offers significant advantage in reliability (lower parts count) and cost over existing
LV designs. There has been tremendous advancement in HV power electronics devices in the
past several years, primarily led by high-power (HP) applications for traction and FACTS
devices. These application areas have used HV and HP switches. Currently, HV, HP power
electronics devices such as gate turn-off thyristors (GTOs), IGBTs, integrated gate commuted
thyristors (IGCTs), and emitter turn-off thyristors (ETOs) are available at the 6-kV level. R&D
work is being conducted for achieving the holy grail of higher switching speed, lower losses, and
increased reliability using IGBT, GTO, ETO, IGCT, or other technologies. Moreover, industry
and other consortia in the field of silicon carbide (SiC) and diamond are also conducting
considerable research work in this field. These high-voltage, high-power power electronics, once
they mature, will result in a significant reduction in the overall cost of solid-state designs.
A pictorial representation of the available HV semiconductor devices and their applications are
shown in Figure 6-4. The overall technology roadmap characteristics, based on DARPAs R&D
program (shown in Figure 6-5 and Figure 6-6), provide a consolidated summary of the key
technology metrics that are required to realize the development of high-voltage semiconductor
devices. Figure 6-7 outlines the key requirements for these next-generation semiconductor
devices. A companion EPRI report [24] provides details for the next generation semiconductor
devices and lays the foundation for EPRIs HV, LP solid-state electronics program. Information
provided in this report includes:
A comprehensive set of functional requirements for a range of HV, LP switches and diodes
that can be used in an IUT
Mapping of existing and emerging power semiconductor switches to these functional

requirements
Evaluation of the suitability of silicon and wide-band-gap semiconductor technology for HV,
LP switches
Possible technology options for development of HV, LP switches and the prospects and risks
for the various options
An R&D roadmap for EPRIs HV, LP solid-state program

6-9

TRACTION
Application Field
Line Voltage:
0.5 - 5 kV DC
0.1-10MVA
PE Design
Max. Voltage Across

Semiconductor
Standard
Converter &Inverter
1 6.5 kV
INDUSTRIAL
DRIVES
Line Voltage:
2-5 kV AC
0.1 10MVA
Standard
Converter &Inverter/
3-Level Circuit
1 6.5 kV
PULSE POWER
Line Voltage:
>10kV / 10MVA
Series Connection
Pulse Transformer
> 6.5 kV
> 4.5kV IGBT Modules

Figure 6-4
Available HV Semiconductor Devices and Their Applications
6-10
INTELLIGENT UNIVERSAL
TRANSFORMER
Line Voltage:
15-100kVA 15kV Class
3-Level/
5-Level Circuit
> 4.5 kV

Phase I
Task
FY02
FY03
Phase II
FY04
FY05
FY06
Conducting SiC substrate

Thick SiC Epitaxy
Materials Validation
(on-state characteristics)
Device Optimization
(freq. and power)
Integrated Control
>100 kHz Power circuits
Packaging and Integration
Phase I
Go/No-Go
Phase II
Go/No-Go
Figure 6-5
DARPAs R&D Development Plan for HV Device
Devices
2004
1. Si IGBTs
6.5 kV HV-IGBT available

6.5 kV IGBT matured with cost reduction
2005
2006
2007
2008
2. SiC diodes
reduce forward voltage degradation

13 kV PIN diodes available for research
further improvement on forward voltage degradation
13 kV diode available
6.5 kV available for sampling
13 kV diode available for sampling
25 kV diode available for sampling
4. SiC power
MOSFETs
6.5 kV research device available

13 kV MOSFET research device available
P-channel MOSFET available
6.5 kV MOSFET technology matured with cost reduction
6.5 kV MOSFET available for sampling
13 kV MOSFET technology matured with cost reduction
5. SiC IGBTs
Thick EPI material resarch starts

IGBT research starts
P-type wafer available
13 kV IGBT research device available
6.5 kV IGBT available for integration
25 kV IGBT research device available
13 kV IGBT available for system integration
Figure 6-6
HV Device Roadmap and Development Projection Based on DARPAs R&D Program
6-11

IGBT
Galium Arsenide (GaAs) / Galium Nitride (GaN)
Silicon Carbide (SiC)
Diamond
Properties
Results
Large Band Gap

Higher Carrier Mobility
High Electrical Conductivity
High Thermal Conductivity
High Power Capability

High Frequency
Low Conduction Drop
High Junction Temperature
Switch Requirements
High Input Impedance
Low on-state drop
Infinite off resistance
Fast turn-off & turn-on
Ability to withstand high V & I
High current density
High temperature Capability
Ideal Switch is still a dream !!

Integrated gave driver
Minimize conduction loss
Zero leakage
Minimize switching losses
Snubber-less operation
Reduced size
Reduced heat-sink
Less device count
Figure 6-7
Requirements for the Next Generation HV Semiconductor Switches and Diodes
The Unique Requirement of High-Voltage Low-Current Power Electronics for

Distribution Transformer Application
The existing market driver for HV power electronics is led primarily by high-power applications
in the multi-megawatt range. For distribution transformers, the requirement is high-voltage but
low-power devices (5 to 10 A at 6 kV). There is no technical hurdle, however, in designing HV,
low-power power electronics. However, there is no market application for such devices. Because
there are no significant application drivers for low-current, HV IGBTs, the manufacturers have
to custom package single discrete IGBT units (see Figure 6-8) for the purpose of IUT prototype.
While HV, HP power semiconductor devices can certainly be used in IUT applications,
development and use in the IUT of a HV, LP power semiconductor switch offers significant cost
advantage that is critical for successful market entry of IUTs. Significant cost reduction for
distribution transformer application using HV, low-current power semiconductors could be
realized due to the following:
Mass market: The potential size of the distribution transformer market could result in an
order of magnitude price decrease for HV power electronics than the current market price. It
is noteworthy that the distribution market is much larger than that required for traction
application and FACTS devices. As the size and demand of the market grows, the cost of
these devices would be significantly reduced (see Figure 6-9).
6-12

Lower current rating devices than what exists currently: Again, lower current ratings should
also result in a significant reduction in cost of these devices.
Application: High Voltage High Power
(traction, industrial drives,
pulse power)
IGBT Module 4.5kV, 400-1000A (Powerex)
6.5kV, 600A
(Eupec)
Application: High Voltage Low Power

(IUT)
Single Discrete IGBT Unit 4.5kV, 30-80A (Powerex)
3.3kV, 30-80A (IXYS)
Convert to Custom
Packaged Unit for
IUT Development
A 6-pack IGBT can be configured in one single device with 12 devices

in parallel or a 3-phase inverter bridge with 2 in parallel
Terminal
connection
Insulated
Metal
Substrate
IGBT
Diode
Figure 6-8
Are Present HV Semiconductor Devices Suitable for IUT Application?
6-13

Price Projection of HV-IGBT based on price quote supplied by IXYS for a 2.5kV, 32A model
55
Price (cents/kVA)
50
45
40
35
30
25
20
15
10
5
1k-10k
500-999
100-499
50-99
1-49
Quantity
Figure 6-9
Cost Comparison for Off-the-Shelf Insulated Gate Bipolar Transistors (IGBTs) A Direct
Vendor Quote
The next section provides a brief overview, estimated market prices, and possible applications
areas of these devices (note that these illustrations are made only using IGBTs).
Silicon-Based HV-Insulated Gate Bipolar Transistors (IGBTs)
Basic Structure
Figure 6-10(a) shows the basic structure of an IGBT. Without the bottom p-layer, the structure is
similar to a power MOSFET that has an n-channel to connect the current. When a positive
voltage is applied in between the gate and the n-channel, the electric field will create a
conduction channel between n and n layers. Adding a p-layer on the bottom allows the device to
block a higher voltage. The equivalent circuit is shown in Figure 6-10(b). A PNP transistor is
formed by the collector p-layer, the internal n -layer, and the body p-layer form. The metal gate
along with the insulated oxide layer and the emitter n-layer form a power MOSFET. With power
MOSFET shorting the base and collector of the PNP transistor, the voltage drop of the IGBT is
the sum of the PNP emitter-base voltage and the MOSFET resistive voltage. Larger silicon area
allows smaller resistive drop, but the emitter-base voltage drop tends to be constant.
6-14

Metal Gate
Oxide SiO2
Emitter
C
p
IMOS
IC
IE
G
E
Collector
(a)
(b)
Figure 6-10
Insulated Gate Bipolar Transistor (IGBT) Structure and Symbol: (a) Basic IGBT Structure,
(b) IGBT Equivalent Circuit and Symbol
High-Voltage Insulated Gate Bipolar Transistors
A new punch-through (PT) technology was introduced to show that HV blocking could be
achieved with the addition of an n+ buffer along with the local lifetime control, the optimization
of p-collector layer, and an improved wafer processing in [25]. With the improved PT
technology, high-voltage IGBT (HV-IGBT) is now available at 3.3 kV, 4.5 kV, and 6.5 kV [26,
27, 28]. The HV solid-state switch can also be found at 12-kV, 1-A rating [26, 27, 28].
Figure 6-11 compares the discrete LV IGBT and HV-IGBT module. Figure 6-11(a) shows a
discrete TO-247 plastic package. The size of the plastic part is 16 mm 21 mm (0.63 inches
0.83 inches). The picture in Figure 6-11(b) shows the package of an HV-IGBT rated 3300 V,
1200 A with a physical size of 140 mm 190 mm (5.5 inches 7.5 inches).
(a)
(b)
Figure 6-11
Ilustrations of Insulated Gate Bipolar Transistors (IGBTs): (a) Discrete TO-247 Package
Rated Up to 1.2 kV and 50 A and (b) HV-IGBT Module Rated Up to 6.5 kV and 600 A
LV-IGBTs are typically very fast, but HV-IGBTs tend to be slow. Figure 6-12 shows test results
of a 2.5-kV, 1.2-kA HV-IGBT operating at 2-kV and 700-A conditions. Measured turn-on and
turn-off energies are 1.88 J and 0.86 J, respectively.
6-15

Figure 6-12
Voltage and Current Waveforms of a High-Voltage Insulated Gate Bipolar Transistor
(HV-IGBT) Switching at 2-kV and 700-A Conditions
The main reason for slow-switching HV-IGBT is simply that it takes time for the voltage and
current to rise or fall. If it were the same voltage but lower current, the speed should be
proportionally lower. Currently, the low-current HV-IGBT is not offered off-the-shelf but is
likely to be obtained from manufacturers [26, 27, 28]. Thus, it is possible to develop solid-state
transformers (where the incoming voltage level could be 7.2 kV) for capacities such as 10 kVA
to 50 kVA using low-current HV-IGBT.
The efficiency of a conventional IGBT-based inverter has been found to be approximately 98%.
The multi-level converter efficiency is typically approximately 99%. The high-frequency
transformer efficiency is also approximately 99%. With combination of a multi-level converter, a
high-frequency transformer, and a low-voltage inverter, the overall system efficiency is expected
to be approximately 96%. With further improvements to minimize switching and conduction
losses through R&D it is possible that the system efficiency may be pushed to 97% or 98%, but
then cost becomes a concern.
Cost Projection for Commercially Available Silicon-Based Insulated Gate Bipolar Transistor
Although the IGBT is not the dominating cost factor in the entire system, it is the enabling
device and should be examined closely for its price trend over the years. Because of variation of
device ratings, manufacturers, and vendors, the price is not unified and is very difficult to give a
solid number to indicate the IGBT price. The approach here is to observe the price at different
current ratings in the recent five years from different vendors for three voltage levels: 600 V,
1200 V, and HV IGBT (typically higher than 2500 V) and make a list for comparison (see
Table 6-4). Some devices are IGBT only, and some are IGBT plus diode. For a quantity more
than 1000, the price is lowered further, but because it is normally negotiable, it is difficult to
compare.
6-16

Table 6-4
Comparison of Price for Silicon Insulated Gate Bipolar Transistor Over the Last Five Years
From Different Vendors
Model Number
(Package Type)
IRG4BC30F (600 V, 31 A, 18.6 kVA)
Quantity of 1
Source
$/kVA
$/kVA
0.16
0.16
0.16
0.20
0.34
0.17
0.17
0.20
0.24
0.21
0.15
0.15
0.16
0.21
0.20
0.41
0.41
0.20
0.20
0.12
2.09
2.09
2.09
2.95
3.40
4.96
4.96
5.88
8.35
6.78
5.08
5.08
6.04
7.99
9.77
10.19
10.19
11.34
11.34
0.11
0.11
0.11
0.16
0.18
0.12
0.12
0.14
0.20
0.16
0.09
0.09
0.11
0.15
0.18
0.20
0.20
0.12
0.12
93.00
0.26
214.2
0.89
KM400GA123D (1200 V, 400 A, 960 kVA)

SKiM100GD063D (600 V, 100 A, 360 kVA)
Digikey
Digikey
Digikey
Newark
Farnell
Digikey
Digikey
Digikey
Newark
Digikey
Digikey
Digikey
Digikey
Digikey
Newark
Digikey
Digikey
Digikey
Digikey
Sales rep
Sales rep
2003
2002
2000
1999
1997
2003
2002
2001
1999
1997
2003
2002
2001
2000
1999
2002
2002
2003
2002
2002
2001
2.98
2.98
2.98
3.63
6.37
7.09
7.09
8.40
10.22
9.01
7.91
7.91
8.62
11.42
10.99
21.00
21.00
18.90
18.90
118.00
SKM100GA123D (1200 V, 100 A, 240 kVA)
Farnell
1997
272.6
IRG4PC50F (600 V, 70 A, 42 kVA)
IRG4PH50U (1200 V, 45 A, 54 kVA)
IRG4PSC71UD (600 V, 85 A, 51 kVA)

IRG4PSH71UD (1200 V, 78 A, 93.6 kVA)
Quantity of 100
Year
1.14
Using the $/kVA as the index, the price for the 600-V IGBT tends to have stabilized in recent
years, especially for small-current devices. For larger-current devices, their price continues to
decline a little bit. The price for the 1200-V IGBT is still declining and is already lower than the
price level of the 600-V device. Using the lowest price in each year for different voltage levels,
the IGBT cost projection can be plotted as shown in Figure 6-13 and Figure 6-14 for siliconbased IGBT and silicon-based IGBT plus diode, respectively. Overall trend for the device cost
reduction is a downwardly sloped exponential curve.
6-17
Price ($)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1990
1200V IGBT
600V IGBT
1992
1994
1996
1998
2000
2002
2004
year
Figure 6-13
Cost Trend for Silicon-Based Insulated Gate Bipolar Transistor
1.4
Price ($)
1.2
1
1200V
IGBT+diode
0.8
0.6
0.4
HV-IGBT
+ diode
600V
IGBT+diode
0.2
0
1990
1995
year
2000
2005
Figure 6-14
Cost Trend and Projection for Silicon-Based Insulated Gate Bipolar Transistor + Diode
Notice that a commercial IGBT was not available until late 1980s. The demand for IGBTs
became strong because of successful applications in the heating, ventilating, and air conditioning
(HVAC) industry. Early devices supplied by manufacturers such as General Electric and Toshiba
were considered very expensive, and the price was not competitive with the GTOs in highpower, bipolar junction transistors (BJTs) in medium power, and power MOSFETs in low
6-18

power. Today, IGBTs have established themselves as the most cost competitive device in
medium-power and, even some, high-power applications. The projection in Figure 6-14 indicates
that the declining rate of the price for the 1200-V IGBT module is faster than that of the 600-V
IGBT.
With maturity of silicon device technology, the yield rate is generally nearly 100%, and thus the
device cost factor is no longer the silicon. Quantity order plays the major role of cost reduction
because the cost involved in setting up the manufacturing process. When the quantity exceeds a
million per month, the device cost can be easily negotiated down to near the raw material cost.
For example, a power MOSFET with voltage-current rating of 12.5 kVA in TO-220 package can
be negotiated down to 25 each. This translates to 2/kVA, four times less than the projected
low-voltage IGBT cost shown in Figure 6-14. Notice that the price estimate in Figure 6-14 is
based on quantity of 100 purchases. In large quantity order, 2/kVA is not difficult to meet. The
projection for HV-IGBT for 2003 price is in fact accurately reflected in the following price quote
for a 2500-V, 32-A HV IGBT, model IXLF19N250A made by IXYS (shown in Figure 6-9). The
price for quantity of 100 is calculated to be 31/kVA, which matches the curve shown in Figure
6-13 fairly well.
With technology getting mature in HV IGBT, it can be projected that the price for the HV IGBT
will drop to the same level or even below that of the 600-V IGBT in the next few years. It can be
seen from the above IGBT cost history and projection results, all of the IGBT module prices
should eventually drop to approximately $0.10/kVA, even in a small-quantity purchase.
Moving Beyond HV IGBT Why Wide-Band-Gap Semiconductor Materials and Why
Not
What are Wide Band Gap Materials?
The question one may then ask, Why not consider wide-band-gap technology for the
development of the proposed HV multi-level converter-based IUT? In general, HV power
devices made with wide band gap materials are better for use in designing the primary side of a
solid-state distribution transformer. Materials that have received the most interest for the
development of power semiconductors include, but are not limited to gallium-arsenide (GaAs),
gallium-nitride (GaN), aluminum-nitride (AlN), silicon carbide (SiC), and diamond. Three types
of SiC prototypes have been studied: 3C, 4H, and 6H. The 3C-form has a cubic lattice structure
while the others are hexagonal. The number indicates how many basic layers of 0.251 nm
spacing from the elementary cell. The cubic form has isotropic properties, whereas the hexagonal
forms have anisotropic properties. This means that material properties like carrier mobility and
electrical permitivity take the form of tensors, and the carrier drift velocity and the dielectric
polarization may take up directions that differ from that of the applied electric field. Table 6-5
compares physical properties of silicon and wide band-gap materials [29-30]. Figure 6-15 shows
the decrease in volume that can be achieved through the utilization of SiC material.
6-19

Table 6-5
Key Properties of Wide-Band Gap Semiconductor Materials
Si
GaAs
GaN
3C-SiC
6H-SiC
4H-SiC
Diamond
1.12
1.42
3.4
2.2
2.9
3.2
5.5
Electron saturation
velocity (107cm/s)
2.5
2.5
2.7
2.7
Dielectric constant
11.8
12.9
10
9.7
10
9.7
5.5
Breakdown field
(MV/cm)
0.3
0.4
3.3
1.5
2.2
3.0
5.6
Thermal conductivity
(W/cm/K)
1.5
0.46
1.3
5.0
4.9
22
Electron mobility n
(cm2/Vs)
1350
8500
900
100
460
800
1900
Electron mobility p
(cm2/Vs)
470
90
150
50
50
120
1200
Band gap (eV)
T fin = 55C
Baseplate Power
Density ~ 105 W/m2
Baseplate Power
Density ~ 105 W/m2
Silicon Power
Density = 106 W/m2
T fin >200C
Silicon
Tj ~125-150 C
SiC Power
Density = 106 W/m2
Silicon Carbide
Tj ~300 - 350 C
Smaller,
hotter
heatsink
feasible
with SiC
(Q=hAT)
Heatsink Power
Density ~ 103 W/m2
Courtesy:
Figure 6-15
Decrease in System Volume Through Utilization of SiC
6-20
Heatsink Power
Density ~ 104 W/m2

Band Gap and Operating Temperature
The fundamental limitation on devices made with silicon is its poor high temperature capability.
When the intrinsic carrier concentration exceeds the doping of the blocking layer, the device
becomes a conductor and fails. The practical maximum operation temperature of silicon devices
is between 150 and 200 C. As the intrinsic concentration depends on eEg/2kT, materials with wider
band-gap (Eg) reach this limit at higher temperatures and so have potential advantages [31].
In general, the major advantage of using wide band-gap power semiconductors is to increase the
maximum operating junction temperature Tjmax, maximum breakdown voltage, VBV, and the
dynamic switching characteristics. Silicon drives normally have Tjmax about 150 C. By
comparing the band gap values in Table 6-5, Tjmax of other materials can be projected as:
GaAs: 200C
SiC: 400C
GaN: 500C
Diamond 700C
The increase in Tjmax also results in a considerable increase in the maximum allowable steady-state
power loss within the device and hence its operating current density. However, it may be offset
if the semiconductor has a low thermal conductivity. Thus, GaAs with poorer thermal
conductivity is not a good choice for high power device application. On the other hand, SiC not
only has wider band gap, but also has better thermal conductivity, and thus is considered very
attractive material for high power devices.
Diamond has an even larger band gap and thermal conductivity to SiC, but the problem is the
availability of large area wafers with low defect densities, and its very low expansion coefficient
that can cause serious mismatch problems. In addition, diamond is most difficult to process for
device fabrication. It is also difficult to achieve good adherence to metallization. Thus the
progress on diamond research has been slow.
The nitride materials such as gallium nitride (GaN, EG = 3.4 eV) and aluminum nitride (AlN, EG
= 6.2 eV) are showing very impressive band gaps. Presently, large area, low defect density GaN
and AlN are not available. They also offer incremental improvements over a much more mature
material technology of SiC. For power device applications, GaN epi-layers are normally grown
on the 4H-SiC or 6H-SiC wafer. Hence, the cost of nitride family materials remains a major
obstacle.
Power Device Figure of Merit
Although the band gap is the dominant property that determines the operating temperature, it is
worthwhile to examine what is the impact of other material properties on device capability. In
other words, what are the key properties to look at? J. Baliga [32] suggested that for highfrequency power switching applications, the material should have a large mobility and large
critical electric breakdown field. His definition of the specific on resistance Rsp-on at a breakdown
6-21

voltage level VBV has been widely used as the device figure of merit. Equation 6.1 expresses the
commonly accepted figure of merit (FOM).
2
FOM =
VBV
3
= S N EC
Rsp on
Eq. 6-1
The fundamental relationship between specific on-resistance Ron-sp and blocking voltage or
breakdown voltage VBV can be expressed in Equation 6-2. The FOM formula, shown in Equation
6.1, is derived from Equation 6.2 with omission of the constant.
2
Rsp on
3.375VBV
=
N S EC 3
Eq. 6-2
where
Rsp-on = specific resistance in cm2

N = electron mobility perpendicular to the surface
S = permittivity of the semiconductor,

EC = critical field for avalanche breakdown perpendicular to the surface
The breakdown field voltage is indeed playing much more important role than the mobility.
From Table 6-5 list, the GaAs band gap is the same order as that of silicon, and the thermal
conductivity is significantly worse. The question then is why GaAs is considered as a candidate
of silicon replacement. The answer can be found from the FOM. Among all the materials listed,
GaAs has highest mobility, which is about 6 times that of silicon. This translates to 6 times
reduction on its on-drop resistance. The die area can be proportionally reduced. As a result, the
RC time constant is also reduced significantly. Making a Schottky diode out of GaAs would have
much less reverse recovery related loss.
SiC Device Figure of Merit
On the other hand, SiC has poorer mobility, but its critical breakdown electric field is one order
of magnitude higher than Si. This makes its overall FOM three orders of magnitude better than
silicon. Thus SiC not only shows advantage on junction temperature, but also on the overall
FOM.
Table 6-6 reiterates the basic material properties of Si and 4H-SiC, which is the most commonly
used polytype for power devices. The first two parameters Eg and thermal conductivity indicate
that SiC can operate at a much higher device junction temperature. The third parameter EBR
translates the VBV to be 10 times higher than that of Si materials. The fourth parameter N
indicates that SiC electron mobility is worse than that of Si. Thus the overall FOM needs to be
6-22

discounted proportionally. However, the final SiC material FOM remains 500 times better than
Si material for high-frequency PWM applications.
Table 6-6
Basic Material Properties of Si and SiC
Si
SiC
Band gap (eV)
1.12
Thermal conductivity (W/cm-K)
1.5
Breakdown field (MV/cm)
0.3
Electron mobility (cm2/Vs)
1500
Breakdown voltage limit (kV)
10
Operating temperature limit (C)
175
3.2
4.9
3.5
800
100
>350
Table 6-7 translates SiC material properties into power device figure of merit. The theoretical
value can be derived based on the material property. With the same die size, SiC device
conduction voltage drop is 2000 times less. This allows smaller chip to achieve the same current
handling capability. The leakage current is four orders of magnitude less. This allows SiC device
to be used for much higher voltage application.
Table 6-7
Figure of Merit Comparing Si and SiC Devices
Si
SiC
Conduction voltage drop
Leakage current
Thermal conductivity
Blocking voltage
Power density
2103
1104
3
10
5
Technical Potential of SiC Power Devices as Compared to Limits of Si

Device Voltage
5 to 10 times higher
Current Density
10 to 100 times higher
Switching Losses
1/10th to 1/100th as of today
Working Temperature
Up to 500C
6-23

Power devices with a 6.5 kV rating are commercially available for a 10 kV theoretical
breakdown voltage limit for Si, Similarly, with 10 times higher blocking voltage capability than
Si, SiC can be easily made to have blocking voltage level higher than 10 kV or 20 kV for an
immediate application in the IUT. However, the material defect and degree of difficulty of
making them are high, and thus the SiC devices are not yet made available for the voltage level
we need.
Cost Projection for SiC Devices
HV SiC devices are not mass-produced yet. Currently only alpha-version devices are available
for high-voltage applications and some beta-version diodes are available for low-voltage
applications. SiC Schottky diodes, showing zero reverse recovery characteristic, are available by
Cree and in quantity by Infineon. The quantity availability is only up to 1200 V rating. The price
for quantity of 100 is $10.93 for Infineon SDT12S60, rated 600 V, 12 A. This translates to
$1.52/kVA, at least one order of magnitude higher than its Si counterpart.
For high-voltage SiC devices, the cost is expected to be higher due to limited yield rate. Due to
the lack of commercial SiC power device product offerings to date, the following cost
projections are based upon projected cost of material and processing. Assuming the production
quantity is 100,000 per month and the SiC wafer diameter is 3 inches, the SiC material and
processing cost can be estimated as follows:
Wafer cost: $1,000
Epitaxial cost: $500
Processing cost: $1,000
Total material and processing cost for a 3 SiC wafer is $2,500. The usable chip area for the 3
wafer is approximately 20 cm2. By factoring the yield rate and device chip area requirement, the
device cost can be calculated according to Equation (6-3).
Device cost =
Total material and processing cost

Usable wafer area
yield rate
Chip area
Eq. 6-1
The device chip area consists of the field termination area required to prevent breakdown at the
edges of the active area. In SiC, the termination requires approximately 0.3 mm, 0.5 mm, and 1
mm on each edge for 6 kV, 12 kV, and 25 kV respectively. The active area of the chip needed
for the application is determined by the on-state loss and switching loss that can be dissipated for
2
a typical 200 W/cm power device package. As an example for a 12 kV, 6 A continuous current
requirement, a 0.3 cm2 active area would be required for 30 W switching loss plus 30 W
conduction loss, and 0.1 cm2 would be required for the termination. The switching energy of 30
W corresponds to a 2mJ total turn-on plus turn-off switching energy for 15 kHz operations. The
2 mJ would correspond to a 100 ns turn-on and turn-off time for 6 A continuous current and a 6.5
kV buss. Assuming an on-resistance of twice the ideal specific on-resistance for a 12 kV 4H-SiC
2
2
material (250 m-cm ) and a 50 % duty cycle, the 0.3 cm chip would result in 30 W loss for 6 A
continuous current. This is a conservative estimate and the chip area will likely be smaller for the
6-24

15-kVA IUT applications. Overall cost and performance comparison among different devices are
summarized in Table 6-8.
Table 6-8
SiC Device Cost and Performance Comparison
Yield
rate
Vds-on or Vce-on
chip area
(cm2)
25C
Price
each
125C
6 kV MOSFET
50%
0.2
2.5
$ 50
6 kV VJFET
75%
0.2
1.5
$ 33
12 kV MOSFET
35%
0.4
10
$ 143
12 kV VJFET
45%
0.4
$ 111
25 kV BJT
15%
$ 833
With todays estimate for HV SiC VJFET, the price is estimated as $1.83/kVA in quantity
production. This is to assume that the device can be successfully manufactured without many
defects. As compared to mature HV Si IGBT, the HV SiC VFET is approximately one order of
magnitude more expensive. Notice that there is no history of SiC device cost. It is not possible to
plot the cost projection curves that previously done for silicon IGBTs. However, the cost
estimate shown in Table 6-8 serves as a reference point today.
IUT Development with Wide-Band Gap Material
Although the basic properties of the wide band-gap semiconductor materials can be used to show
the figure of merits for making power semiconductors, the degree of difficulty of making them
commercially available is indeed the most crucial factor to consider. For IUT development,
possible use of the wide band gap materials can be summarized as follows.
Silicon material is simple to make, and with 50 years experience of making them, but Si
power semiconductor devices have approached their theoretical performance limit.
The wide band-gap semiconductors, especially the well-known silicon carbide (SiC) and
Galliom Nitride (GaN) are showing significantly better material properties. With 10 times
blocking voltage capability, SiC can be easily made to have blocking voltage level higher
than 10 kV or 20 kV for immediate application in distribution voltage level. However, the
material defect and degree of difficulty of making them are relatively high, and thus the SiC
devices are not yet commercially available for the voltage level we need. Nevertheless, SiC
devices are most likely to appear in first generation wide band gap based IUTs.
GaN and diamond are much more difficult materials to process than SiC. Theoretically, GaN
and diamond have better material properties than SiC. However, the degree of difficulty of
using even SiC is several orders of magnitude higher than that of making Si devices. GaN
devices have been traditionally developed for RF applications with small die size. Recent
progress in GaN power device development shed a light for this material to be a feasible
device for power electronics applications, as well.
6-25

SiC devices have not been mass-produced. Currently, only alpha-version devices are
available for high-voltage applications, and some beta-version diodes are available for lowvoltage applications. SiC Schottky diodes, showing zero reverse-recovery characteristic, are
available in beta version by Cree and in quantity by Infineon. The quantity availability is
only up to 600-V rating. How long the technology will take to mature is difficult to predict,
and with this uncertainty, its use is limited.
The price for a quantity of 100 SiC devices is $10.93 for Infineon SDT12S60, rated 600 V,
12 A. This translates to $1.52/kVA, at least one order of magnitude higher than its silicon
counterpart. For high-voltage SiC devices, the cost is expected to be higher due to limited
yield rate.
How long the technology can be matured is difficult to predict and with this uncertainty it is
prudent to move with 1st generation IUT development using HV IGBT technology while
closely following the development of wide band gap technologies. Currently the SiC FET
devices have been reported to have 600-V with 30-A and 10-kV with a few ampere current
capability. Using an average of 75% per year on blocking voltage improvement, the SiC FET
devices will reach 10-kV, 30 A, as well as 15 kV, 10 A within 3 years.
Critical Technology Areas

The 2002 report [11] determined that an all-solid-state design for a distribution transformer could
provide a fundamentally different and more complete approach in transformer design. Also, it
was identified that use of high-voltage power electronics in designing the primary side of an allsolid-state transformer offers significant advantage in reliability and cost over low-voltage
designs.
However, all new products face barriers to entry, particularly when competing with entrenched,
mature technologies. As mentioned in the preceding sections, quantity order plays the major role
of cost reduction because the cost involved in setting up the manufacturing process. When the
quantity exceeds a million per month, the device cost can be easily negotiated down to near the
raw material cost. Therefore, although the cost of the needed semiconductor device (HV, lower
power) can come down to an acceptable range, there are some other major cost items that need to
be further reduced. The question is, What else needs to be done to bring the solid-state
transformer to the market? Thus, the critical technology areas that need to be invested in the
near future are as follows:
High-voltage IGBT at different current and voltage levels: The HV IGBT was originally
developed for high-speed, rail traction drive applications. The off-the-shelf devices are all
rated in the mega-watt level. For a wide range of power levels in distribution transformers, it
is necessary to also have a wide range of IGBT current ratings, ranging from ten to hundreds
of amperes.
Multi-level, HV IGBT-based, and solid-state transformer design optimization: Once the HV

IGBTs are lined up for selection, the solid-state transformer designs can then be optimized
with proper levels, phases, and minimum amount of components. Computer simulation
should be performed to compare the performance with different design options.
6-26

Digital signal processing (DSP) controller for multi-level, solid-state transformer: Although
the hardware cost of a DSP controller is not the major cost item (with $10, we can get very
powerful DSP for most of the converter plus inverter systems), the software is the key and
the major intellectual property. Perhaps more than 50 percent of the development cost will be
in the DSP controller and its related interface and communication.
Low-cost, high-voltage gate drivers: The HV gate driver is indeed the major cost item in
hardware. Conventional, low-cost gate drivers (such as the charge-pump circuit and isolation
transformer method) are not appropriate. With the isolation voltage requirement, the most
reliable gate driver is through fiber optic link, and that is why the gate driver cost is very
difficult to reduce. However, one still needs to look into other options to further reduce the
HV gate drivers.
High-voltage bus bar and interconnects: HV power electronics has been traditionally
implemented with thyristor-based devices, and the experience with HV multi-level bus bars
is still lacking. For an HV IGBT busbar, it is possible to find other applications on the
technology itself, but the experience of usage and reliability has not been reported. So far,
most designs use an ordinary method that sandwiches thick insulation and copper without
proper sealing. It is necessary to develop the technology related to HV bus bars and
interconnects to ensure reliable operation for a long period. However, it is noteworthy to
mention that this technology is relatively trivial compared to DSP and device.
High-frequency, high-voltage transformers for high-power applications: With highfrequency switching, the size of the transformer would come down dramatically as compared
to the conventional, low-frequency transformer. However, the high-frequency transformer for
HV, high-power application has not been explored and is not readily available from a
manufacturer. Technologies for designing and making high-frequency transformer for HV,
low-power applications need to be developed to further drop the overall cost of these devices.
EPRIs Long-Term Roadmap for the Proposed HV Multilevel ConverterBased Intelligent Universal Transformer
The overall objective of this years activity was to leverage previous years research and provide
a comprehensive design analysis to verify the functionality that can be achieved with the
conceptual high-voltage multilevel converter-based IUT design and estimation of efficiency,
cost, and reliability of such a proposed design. This preliminary research is the first step before
embarking on development of the hardware and associated controls for a prototype universal
transformer. This is the most critical stage because the commitment to a certain design topology
will ultimately lead to hardware and controller development and lab prototype. Critical issues
that are addressed as a part of this years research activity include:
6-27

Determination of design packaging and thermal-management systems
This section adopts the traditional stage-gate approach discussed earlier and provides a detailed
description of the possible phases (shown in Figure 6-16) for design and development of the
proposed HV multi-converter-based IUT technology along with more refined schedules (see
Figure 6-17), important milestones, and budgets estimates (see Figure 6-18) for the development
work in 20042007. The four possible phases identified for the development work in 20032010
include:
Phase I: Intelligent universal transformer prototype development and testing
Phase II: Intelligent universal transformer field prototype development and testing
Phase III: Intelligent universal transformer field deployment, field unit data collection, and
functionality verification
Phase IV: Intelligent universal transformer technology commercialization
6-28

Figure 6-16
Projections of Possible Phases and Individual Tasks for Design and Development (2004
2007) of the Proposed HV Multilevel Converter-Based IUT Design
BENCH MODEL
FIELD PROTOTYPE
FIELD Deployment Schedule
10/06 - 05/07
13.8kV, 5 IUT Beta Models
Field Prototype
- Completed
4/04 - 6/05
4.16kV IUT Bench Model
- Completed
1/04 - 4/ 04
Initiate forum to select
potential vendors
Jan 2005
Jan 2004
1/06 - 12/ 06
13.8kV IUT Alpha Model
Field Prototype
- Completed
1/06
13.8kV IUT
Field Prototype
- Start
Jan 2006
11/07 - 08/08
IUT Field Data Collection
& Analysis
05/07 - 11/07
IUT Field Installation &
Commissioning
Field Data Collection
- Start
1/07 - 05/07
Site Selection & Investigation
Field Demonstration
- Start
Jan 2007
Jan 2008
Sep 2008
Figure 6-17
Development Schedules and Important Milestones
6-29

Figure 6-18
Detailed Budget Estimate for Development Work in 20042007
Phase I: Intelligent Universal Transformer Prototype Development, Testing, and

Functionality Verification
The first phase of the research will proceed after selection of the preferred design topology based
on this years design analysis. The phase I research will lead to development of the hardware,
controller, and packaging of the system for a bench model of an intelligent universal transformer.
The two possible options for the bench model include: 1) 4.16-kV IUT model or 2) 15-kV IUT
model. It is suggested that the initial bench model be based on 4.16-kV system so that the
existing device can be used and high-voltage experience can be gained. The successful rate of
concept proofing is much higher. Once the controller is fully designed and proven to be working,
the high-voltage SiC device or an HV-IGBT (6.5 kV, which is presently not available) can be
used to move the voltage level higher. Table 6-9 and Table 6-10 provide an overview of the
projected tasks and schedules for the development of the 4.16-kV and 15-kV bench model,
respectively.
6-30

Table 6-9
IUT 4.16-kV Projected Bench Model Development Schedule (Assumes Funding Availability)
6-31

Table 6-10
IUT 15-kV Projected Bench Model Development Schedule (Assumes Funding Availability)
6-32

Detailed budget estimates for the 4.16-kV and 15-kV bench model are provided in Table 6-11
through Table 6-14. The prototype serves a number of purposes, including determining that the
product will work. The prototype also serves to highlight design flaws and defects that need to be
resolved. Key research tasks that should be accomplished during this phase include:
Design power circuit for proof-of-concept prototype (2004): The complete power stage,
including devices, passive components, heat sink, sensors, and bus bar, should be designed
and packaged for laboratory demonstration. Gate drivers and auxiliary power supplies need
to be designed with proper isolation and minimum noise susceptibility. It is desirable to have
the device protection at the gate-drive level to ensure highly reliable operation. Voltage and
current at various ac and dc locations and heat-sink temperature should be monitored for both
control and protection purposes.
Design controller with basic functions. (2004): The controller will likely be designed with a
DSP for digital control. Hardware should include sufficient PWM and analog-to-digital
(A/D) and digital-to-analog (D/A) channels. The interface from PWM channels to the gate
drivers would preferably be isolated by optical fibers. Software should be designed to
perform basic control functions such as voltage balance and power transfer.
Integrate and test the laboratory prototype (20042005): The entire power circuit and
controller should be integrated for laboratory testing. Scalable testing with rated voltage and
reduced current or with rated current but reduced voltage are acceptable at initial testing. If
full load under real power is not tested, the full kVA under reactive power testing is
necessary for laboratory demonstration.
Evaluate the performance of the proof-of-concept prototype (2005): The performance such as
system efficiency over entire power range, heat-sink temperature, total harmonic distortion
(THD) of voltage and current, power factor, and so forth need to be evaluated.
Refine prototype design based on test results (2005): Based on initial test results, the
prototype design should be modified and retested in order to verify the performance of the
proof-of-concept prototype. The results from the lab testing should be compared with phase I
design analysis results, and any discrepancies should be accounted for before moving to the
next stage of field demonstration.
6-33

Table 6-11
Budget Estimate Summary for 4.16-kV Bench Model Development
Table 6-12
Budget Estimate Summary for 15-kV Bench Model Development
6-34

Table 6-13
Budget Estimate by Task and Labor Category for 4.16-kV Bench Model Development
6-35

Table 6-14
Budget Estimate by Task and Labor Category for 15-kV Bench Model Development
Major Deliverables for the Phase I

Major deliverables for phase I include a complete multilevel IUT hardware design information
and bench model, including the control algorithms and documented software codes. Critical
technologies for the 4.16-kV bench model include:
High-frequency, high-voltage transformer with 2-kV input
Three-level active front end control design and voltage balancing
Three-level dc/dc converter control design
High-voltage gate drive and IGBT protection
6-36

High-voltage interconnects and interface
DC/AC inverter control design
Critical technologies for the 15-kV bench model includes:
High-frequency, high-voltage transformer with 6.6 kV across the terminals
Five-level active front end control design and voltage balancing
Five-level dc/dc converter control design
Phase II: Intelligent Universal Transformer Field Prototype Development, Testing,

and Functionality Verification
The second phase of the research will lead to development of five field demonstration units.
Unlike controlled laboratory environment, the field demonstration units need to be designed and
packaged to address the entire range of environmental and operational scenarios that may be
encountered in a distribution system. Refinement of the lab prototype should address these
operational and environmental issues before developing field prototypes. Table 6-15 provides an
overview of the projected tasks and schedules for the development of the 15-kV field prototype
model. Detailed budget estimates for 15-kV field prototype are provided in Table 6-16. Key
issues that needs to be addressed during this stage of the development effort include:
Package the power circuit and component (2006): The complete power stage, including
devices, passive components, heat sink, sensors, bus bar, gate drive circuitry, auxiliary power
supplies, and power interfaces, should be designed and packaged for field demonstration.
The power bus bar needs to have proper insulation and current-carrying capability. Design
considerations should include a wide ambient temperature range, moisture and dirt
environment, vibration during shipping, system interconnection, and protection. A bill of
materials should be established with costs and sources identified. The sources of these
components should be secured for quantity production.
Design controller with advanced functions (20062007): The advanced functions include
harmonic compensation, voltage-sag compensation, system protection and coordination,
provisions for dc output bus (24/48 V), provisions for high-frequency ac, provisions for
monitoring and advanced distribution automation functionalities, and so forth need to be
included in the controller design. The controller should be hardened to withstand the
electrical transient environment in actual distribution system through fiber optic isolation
between the hardware and controller stages. The interface and communication between the
solid-state distribution transformer and the power system need to be defined and included.
The controller should be able to accept user commands for different functionality testing.
Integrate and test the field demonstration prototype (20062007): The entire system,
including power stage and controller, needs to be integrated and tested under full-load and
power-transfer conditions. System performance and advanced functions need to be tested and
evaluated with the complete prototype. The breakdown insulation level needs to be tested
under a proper impulse voltage level.
Develop multi-field prototype units (2007): A number of field demonstration prototypes will
be built and delivered to the selected demonstration sites for field-testing.
6-37

Table 6-15
Projected IUT 15-kV Field Prototype Model Development Schedule
6-38

Table 6-16
Budget Estimate Summary for 15-kV Field Prototype Development
Phase III: Intelligent Universal Transformer Field Deployment, Field Unit Data
Collection, and Functionality Verification
The third phase of the research will involve site identification, deployment, monitoring,
testing, and analyzing the five field demonstration units at various locations in distribution
systems to obtain real life field experience and verification of the performance in actual
distribution systems. Utility demonstration sites will be selected and identified through
competitive bids. A number of field demonstration prototypes will be delivered to the
selected demonstration sites for field-testing. Reliability and performance information will be
recorded during the demonstration period for product improvement. The field demonstration
units will be further refined to address the entire range of environmental and operational
scenarios that may be encountered in a distribution system. Table 6-17 provides an overview
of the projected tasks and schedules for field deployment, field unit data collection, and
functionality verification. Detailed budget estimates for this phase are provided in
Table 6-18.
6-39

Table 6-17
Projected IUT Development Schedule During Field Deployment, Field Unit Data Collection,
and Functionality Verification
Table 6-18
Budget Estimate Summary During Field Deployment, Field Unit Data Collection, and
Functionality Verification
6-40

Phase IV: Intelligent Universal Transformer Technology Commercialization (20082010)

The final phase of the intelligent universal transformer research project is technology
commercialization. EPRI will work with the developer, manufacturer, and utilities for largequantity manufacturing and commercialization. Development of a commercialization plan will
be the initial step in this phase. The commercialization plan will address the strategies for
transferring this technology to the marketplace and development of a business plan centered on
specific applications for the intelligent universal transformer. The commercialization plan will
also identify the important characteristics required for successful commercialization. For
example, the commercialization plan will identify essential manufacturing capabilities required
to build the transformer and optimal channels to market and distribution strategies. It is
anticipated that the initial phases of the research will be conducted by EPRI with cost-sharing
from organizations involved in the development of the hardware and field demonstration units.
These organizations will also play a key role with EPRI and member utilities in identifying the
best strategy for commercialization of the intelligent universal transformer.
EPRI long-term research plan outlined in the preceding sections are targeted towards an HV
multilevel converter-based intelligent universal transformer that can meet the requirements
described in the following paragraphs.
Development of Comprehensive Functional Specifications for the Proposed

HV Multilevel Converter-Based Intelligent Universal Transformer
The functional specifications provided below are intended to provide designers with a set of
functionalities that are desirable in the context of a universal transformer, including an
exhaustive list of requirements. These specifications are written in a technology-neutral manner
so as to provide designers with maximum flexibility in achieving the desired functionalities. At a
minimum, the functionality of the proposed design should meet the basic functionality of a
conventional distribution transformer in terms of its capability for voltage transformation and
provide operational benefits in terms of standardization of distribution transformer with respect
to input/output voltage and kVA rating.
Design Guideline for Proposed IUT Based on Conventional Dry-Type Distribution
Transformer Standards
The proposed IUT design should adhere to the relevant requirements for operating environment,
structural design, insulation level, short-circuit protection, surge withstand, and other issues for
distribution transformers that are described in the C57 series of ANSI/IEEE standard for
transformers. Specific C57 series standards that are relevant to distribution transformers are:
ANSI/IEEE C57.12.01 General Requirements for Dry-Type Distribution and Power

Transformers
ANSI/IEEE C57.109 Guide for Transformer Through-Fault-Current Duration.
ANSI C57.96-1959, Guide for Loading Dry-Type Distribution and Power Transformers
6-41

ANSI/IEEE C57.12.31 Pole-Mounted Equipment -- Enclosure Integrity
ANSI C57.12.28 - Pad-Mounted Equipment--Enclosure Integrity
IEEE Std C57.12.91-1995 IEEE Standard Test Code for Dry-Type Distribution and Power
Transformers
IEEE Std C57.98-1993 IEEE Guide for Transformer Impulse Tests
ANSI/IEEE C57.94-1982 IEEE Recommended Practice for Installation, Application,

Operation, and Maintenance of Dry-Type General Purpose Distribution and Power
Transformers
ANSI/IEEE C57.12.56-1986 IEEE Standard Test Procedure for Thermal Evaluation of

Insulation Systems for Ventilated Dry-Type Power and Distribution Transformers
Usual Service Condition

The service conditions of the IUT are expected to be equal or better than those of conventional
dry-type distribution transformers. The following guideline is summarized from ANSI/IEEE
C57.12-1979, General Requirements for Dry-Type Distribution and Power Transformers
section 4. Usual service condition (section 4. Service Condition-4.1 of C57.12) is defined as
follows:
Temperature:
The temperature of the ambient shall not exceed 40C (104F), and the average
temperature for any 24-hour period shall not exceed 30C (86F).
The minimum ambient temperature must not be less than -30C (-22F).
The supply-voltage waveform shall be approximately sinusoidal, and the phase voltages
supplying a polyphase transformer shall be approximately equal in magnitude and of
approximately equal time phase displacement.
Load current shall be approximately sinusoidal. The harmonic factor shall not exceed 0.05
per unit.
Operation above rated voltage:
Transformers shall be capable of delivering rated output in kVA at 5% above rated

secondary voltage without exceeding the limiting temperature rise, when the power
factor of the load is 80% or higher.
Transformers shall be capable of operating at 10% above rated secondary voltage at
no load without exceeding the limiting temperature rise.
Overload Requirement for IUT
The overload capability of the IUT is expected to be equal to or greater than that of conventional
dry-type distribution transformers. The following guideline is summarized from ANSI C57.961959, Guide for Loading Dry-Type Distribution and Power Transformers. Based on C57.966-42

01.251, the permissible load on dry-type transformers may be increased above rated load for
short times by the multipliers shown in Table 96-01.250, provided that:
The short-time peak load occurs not more than once in any 24-hour period.
The short-time peak load follows and is followed by either a constant load or an equivalent
constant load calculated by means of 96-05.500- Method for Converting Actual Load Cycle
to Equivalent Constant Load.
The limitations of 96.00.020 and the basic conditions of 96-01.100 are met (for more
information, see C57.96).
The values given in Table 96-01.250 are conservative and, based on the information in 96-05,
will give approximately the same life expectancy as if the transformers had been operated at
rated load for the 24-hour period.
Generic Specification
It is feasible that many of the functionalities listed below can be programmed into the intelligent
transformer in different modes of operation. For example, harmonic filtering and voltage-sag
compensation could be two different modes of operation that can be integrated within the same
hardware platform, and depending on the controller operating mode, any one of the features
could be activated.
Standardization
The design of the universal transformer should lend itself to standardization of distribution
transformers. The design should be able to accommodate multiple primary and secondary
voltages and reduce (to the extent possible) the existing range of kVA sizes of distribution
transformer inventory that has to be kept by a utility. The proposed transformer design clearly
illustrates how such standardization can be accomplished.
Power Quality and Reliability
The design of the universal transformer should lend itself to expand the capabilities of a
conventional distribution transformer from primarily a voltage-transformation device to an
integrated electrical customer interface that has the capability to meet the customers
requirements and is therefore a viable market opportunity. This pioneering approach has
tremendous market advantages for the industry in that utilities can provide not only the
traditional ac serviced but also virtually create new service opportunities by providing whatever
service the customer desires (dc power, high-frequency ac power, sag protection, harmonic
filtering, and so on). The prospective transformer designs should clearly illustrate the specific
functional requirements that will be required to achieve voltage-sag compensation, harmonic
compensation, instantaneous voltage regulation, flicker mitigation, outage compensation,
capacitor-switching protection, single-phase protection, provisions of dc output, and provisions
for high-frequency ac output. The proposed transformer design clearly illustrates how these
requirements can be fulfilled.
6-43

Reactive Compensation
Reactive compensation using power electronics inverters serves as the basis for dynamic reactive
compensation system such as DSTATCOM. It is feasible to apply the same concept in a solid
state transformer design so as to control not only the load power factor but also to provide
reactive compensation to the system. This is a revolutionary concept in terms of functionality for
a transformer. The proposed design for the universal transformer identifies how reactive
compensation can be achieved.
Communications
As the distribution system becomes more automated, opportunities exist to improve the
utilization of distribution transformers. More sophisticated automation integrated with the
intelligent universal transformer can serve as an outage-notification and outage-management
device, remotely control the different modes of the functionality of the transformer, and monitor
conditions of the transformer in real time. The proposed design should evaluate centralized
control, decentralized control, and combination approaches for automation. Realizing the full
potential of an intelligent universal transformer will require more sophisticated communication
architectures. A promising platform is the IEC 61850 architecture, which is an open industry
standard developed from EPRIs utility communications architecture (UCA). A wide variety of
equipment can plug into this architecture. The proposed design should provide the flexibility to
integrate the IEC 61859 architecture within the intelligent universal transformer.
Efficiency
Unlike a conventional transformer where the efficiency increases with loading, for a solid-state
transformer, the efficiency is likely to be much higher at reduced loading because of the
significant reduction in core losses or in some cases depending on the design absence of core
loss. This is desirable because in most cases, distribution transformers are significantly
oversized, and higher efficiency at reduced loading will result in reducing distribution losses.
Most likely the efficiency impact for a solid-state-based universal transformer under practical
loading condition will be advantageous over traditional transformers, even though the full load
loss may be several percentage points below conventional transformers. The proposed design
should evaluate the efficiency of the transformer under different loading condition and should
strive to maintain a >95% efficiency at 50% load and a >99% efficiency under no load or light
load condition.
Reliability
Existing distribution transformers are extremely reliable. Life expectancy can exceed 30 years
with minimal maintenance. It will be a challenge for the solid-state universal transformer to
achieve such level of reliability. Design considerations should attempt to minimize the parts
count, which dictates the efficiency of any power electronics system. The proposed design
should provide information about mean time between failure (MTBF) using industry-established
methods such as MIL-HDBK-217F Reliability Prediction of Electronic Equipment. The
reliability study must include more than a quantification of the anticipated failure rate; it must
6-44

also include a failure mode and effect analysis (FMEA) to estimate the degree of risk to the
transformer in the event of a component failure. An in-depth reliability assessment of the
proposed IUT system using an industry standard reliability calculation method was performed
with the proposed design.
Environment
One of the main advantages of a solid-state design over a hybrid design is that the solid-state
approach can lead to an oil-free transformer, which would be more environmentally friendly.
The proposed design should take into account the cooling requirement of different power
electronics components and provide design analysis to show how through application of proper
heat sinks and air cooling, the oil-free benefits of the universal transformer can be realized.
Cost
Cost is the most influential parameter that will dictate the market acceptance of the intelligent
universal transformer. For such a transformer to be considered as a replacement of traditional
transformer, the cost target should be comparable to existing transformers. Based on discussion
with utility members, it appears that a 20% cost increase can be justified based on the operational
benefits that can be realized by the standardized design and oil-free environment. Additional
functionalities, such as power quality, dc output, and reactive compensation, will be applicationspecific, and for these applications, the cost target is dictated by existing products that meet such
requirements. The initial design analysis should provide an indication of the system first cost
based on component costs and reasonable estimate for other peripherals. The proposed design
should also provide market-penetration data for components used for the design in order to
estimate how mass application potential of the distribution transformer can reduce the overall
cost of the components based on similar experience in other areas. If components used in the
design already have mass-market application, then significant reduction from current cost level
may not be realized. Standard cost curves for power electronics components that provide
indication of how the cost reduces with market entry can be used to estimate mature pricing of
the universal transformer with assumptions regarding different degree of market penetration.
Technical Specifications
A thorough design and performance analysis was conducted on the proposed IUT design in order
to evaluate which one of the functional specifications can be achieved and what will be tradeoffs
in cost, efficiency, and reliability to achieve additional functionalities. Detailed technical
specification of the proposed IUT design (shown in Figure 6-19) is provided next.
6-45

6.6 kV
Lf
Sr11
Sr21
Si1
Sr12
Sr22
Si2
Sr13
Sr23
Si3
Sr14
Sr24
Si4
Sr11
Sr21
Si1
Sr12
Sr22
Si2
Sr13
Sr23
Si3
Sr14
Sr24
Si4
1r
-6.6 kV
OUTPUT 2
120/240 V
60 Hz
OUTPUT 1
+
48 Vdc
_
OUTPUT 3
8 kV
16.6 kVA
120V
400 Hz
5
3
4
Isolated
DC/DC
converter
1i
Figure 6-19
Schematic of the Proposed IUT Design
System
Rated kVA (kW) capability
20 kVA
16.6 kW
Input
Rated input voltage
8 kV, 1 phase/ 2 wires
Rated input current
2.1 A
Rate input frequency
60 Hz
Input power factor
>0.99
Input current THD
<3% at 100% load

<6% at 25% load
Output 1
Rated output voltage
240/120 V, ac, 1 phase/3 wires
Rate output current
83.3 A
Rate output frequency
60 Hz
Voltage regulation
0.5%
Voltage THD
<2% with 100% linear load

<3% with 50% nonlinear load
6-46

Overload capacity
125% for 10 minutes,

150% for 1 minute
200% for 20 seconds
300% for 10 cycles
600% for 1 cycle
Output 2
Short-circuit capability
1000% for 10 s
Transient voltage regulation
<5% with 100% load step
Transient voltage recovery
<15ms with 100% load step
110 V fixed and variable 0-120V, ac
Rated output current
36.4 A
Rate output frequency
400 Hz fixed and variable 0-500 Hz
Voltage regulation
0.5%
Voltage THD
<2% with 100% linear load

<3% with 50% nonlinear load
Overload capacity

150% for 1 minute
200% for 20 seconds
300% for 10 cycles
600% for 1 cycle
Output 3
9
1000% for 10 s
Transient voltage regulation
<5% with 100% load step
Transient voltage recovery
<15ms with 100% load step
48 V, dc
Adopted from UPS specifications
6-47

Rated output current
83.3 A
Voltage regulation
0.5%
Overload capacity

150% for 1 minute
200% for 20 seconds
300% for 10 cycles
600% for 1 cycle
Environment Audible noise
1000% for 10 s
65 dB at 1 meter
EMC
FCC Class A and EN50091-2
Operating temperature
30 to 45C (22 to 113F)
Storage temperature
30 to 70C (22 to 158F)
Operating humidity
3095% RH
MTBF
>100,000 hours
Efficiency
>95%
Voltage and Current Waveforms Under Transient Conditions

Simulation results are used to justify some key technical specifications. Examples are voltage
regulation under transient load steps, overload capability and overload withstand length, and
short circuit capability.
A. Load Step
Under load-step conditions, output voltage tends to fluctuate. However, if the inverter is well
controlled with a closed-loop system, then the voltage fluctuation should be negligible.
Simulation results in Figure 6-20 show that the output voltage has glitches during load transient,
but the magnitude remains constant. The simulation study is to have 50% load step, and the
voltage regulation is practically zero. In our specification, we give 5% for 100% load step. It
should not be difficult to achieve those criteria with a reasonable control-loop design.
6-48

Vpk
0.2k
Vac1
0.1k
50
0
-50
-0.1k
IRL
-0.2k
0.1k 0
50
20m
40m
60m
80m
0.1
60m
80m
0.1 t
IRL
ILf
0
-50
-0.1k
20m
40m
load step
load dump
Time (s)
Figure 6-20
Output Voltage Shows Glitches Under Load Transient, but the Magnitude Remains
Constant
B. Voltage Sag
The inverter needs to continuously operate under voltage-sag conditions. With input voltage
reduced, in order to maintain the same output, the input current must be increased. Figure 6-21
shows the simulation results during a 50% voltage sag. Under rated load conditions, the input
current actually increases to three times the rated current. If the 50% voltage sag lasts for 10
cycles, then the converter must be able to handle 300% overload current for at least 10 cycles.
This is equivalent to having output overload conditions, although the disturbance is coming from
the input. The output-side inverter should have the same overload capability as that of the AFE
converter. Thus, our overload current is specified with 300% for 10 cycles.
6-49

50% voltage sag

12k
Input
voltage
vin
0
-12k
Input
current
Output
voltage
90
4
0
10m
20m
30m
iin
-4
-9
0.35k 0
0.15k
0
10m
20m
10m
20m
vac1
-0.15k
-0.35k
0
vac2
3 50m
40m
60m
70m
80m
90m
0.1 t
v30m
ac
40m
50m
60m
70m
80m
90m
0.1 t
30m
40m
50m
60m
70m
80m
90m
0.1 t
Time (s)
Figure 6-21
Input Current Increases by Three Times During 50% Voltage Sag, but the Output Voltage Is
Not Affected
C. Outage
Without sufficient energy backup, the converter simply needs to shut down under outage
conditions. However, the dc bus capacitors can be used for short-term outage backup. In our
design, two cycles of outage is allowed. Figure 6-22 shows the simulation voltages and currents
during a two-cycle outage. The input current increases to five times the rated current after the
outage. However, this overshoot current lasts less than 1 cycle. In other words, the converter
needs to have at least five times overload capability for 1 cycle to handle transient condition. The
output inverter should also have the same or better capability for output overload. Thus, our
1-cycle overload is specified with 800%.
6-50

Outage period
12k
Input
voltage
vin
0
-12k
16 0
Input
current
10m
20m
30m
40m
50m
60m
70m
80m
90m
0.1
40m
50m
60m
70m
80m
90m
0.1
40m
50m
60m
70m
80m
90m
0.1 t
iin
0
-6
-16
Output
voltage
0.35k 0
0.15k
0
10m
v
20m
10m
20m
ac1
-0.15k
-0.35k
0
30m
vac
vac2
30m
Time (s)
Figure 6-22
Input Current Increases by Five Times, and the Output Voltage Sees 2% Dip After a 2-Cycle
Outage
D. Nonlinear Load
Under nonlinear load conditions, the output voltage tends to be distorted, especially with a
conventional transformer system. With the IUT, the output voltage can be regulated very well
and disregard the linearity of the load current. The conventional system may see about 2.5%
voltage THD when the nonlinear load draws a current with 100% THD. The simulation results
shown in Figure 6-23 indicate that the output voltage can be well regulated with a nearly perfect
sinusoidal waveform. In general, a system should not have a high percentage of nonlinear loads.
Thus, our specification is to have voltage well regulated under 50% nonlinear load conditions,
and the voltage THD is less than 3%.
6-51

Vpk = 170 V
0.2k
200
Cf.V
Cf1
0.1k
100
50
00
-50
-0.1k
100
-0.2k
200
0
Output voltage
20m
50
50
40
20
20
00
20
-20
40
-50
50
0
0
40m
60m
20m
20
40m
60m
40
0.1 t [s]
LL
Lw
Load current
60
Time (ms)
Figure 6-23
Inverter Output Voltage Under Nonlinear Load Conditions
6-52
80m
80m
80
0.1t [s
100
7
REFERENCES
1. N. Mohan, T. Undeland, and W. Robbins, Power Electronics, John Wiley and Sons, 2nd ed.,
New York, 1995.
2. P. Barnes, J. Van Dyke, B. McConnell, and S. Das, Determination Analysis Of Energy
Conservation Standards For Distribution Transformers, ORNL 6847, Oak Ridge, TN, July
1996.
3. J. Van Dyke, P. Barnes, B. McConnell, and S. Das, Supplement to the Determination
Analysis of Energy Conservation Standards for Distribution Transformers, ORNL 6925, Oak
Ridge, TN, Sept. 1997.
4. B. Howe, Selecting Dry-Type Transformers Getting the Most Energy Efficiency for the
Dollar, E Source Inc., Boulder, Colorado1995.
5. J. Brooks, Solid-State Transformer Concept Development, in Naval Material Command,
U.S. Navy, Naval Construction Battalion Center, Port Hueneme, CA, 1980.
6. Proof of the Principle of the Solid-State Transformer and the AC/AC Switch-Mode
Regulator, EPRI, Palo Alto, CA: 1995. 105067.
7. S. Sudhoff, Solid-State Transformer, U.S. Government Printing Office, Aug. 24, 1999. U.S.
Patent No. 5943229.
8. W. McMurray, Power Converter Circuits Having a High-Frequency Link, U.S. Government
Printing Office, Washington, DC, June 23, 1970. U.S. Patent 3 517 300.
9. M. Kang, P. Enjeti, and I. Pitel, Analysis and Design of Electronic Transformers for Electric
Power Distribution System, IEEE Transactions on Power Electronics, IEEE, Nov. 1999.
10. E. Ronan, Jr., S. Sudhoff, S. Glover, and D. Galloway, Application of Power Electronics to
the Distribution Transformer, in Conference Record: Applied Power Electronics Conference
and Exposition, New Orleans, LA, Feb. 2000, pp. 861867.
11. Feasibility Assessment for Intelligent Universal Transformer, EPRI, Palo Alto, CA: 2002.
1001698.
12. Distribution System Cost Structure, EPRI, Palo Alto, CA: 1998. 109178.
7-1

References
13. E. Ronan, Jr., S. Sudhoff, S. Glover, and D. Galloway, A Power Electronic-Based

Distribution Transformer, IEEE Transactions on Power Delivery, IEEE, April 2002,
pp. 537543.
14. J. Lai and F. Peng, Multilevel Converters? A New Breed of Power Converters, IEEE
Transactions on Industry Applications, IEEE, May/June 1996, pp. 509517.
15. J. Rodriguez, J. Lai, and F. Peng, Multilevel Inverters: A Survey of Topologies, Controls,
and Applications, IEEE Transactions on Industrial Electronics, IEEE, Aug. 2002, pp. 724
738.
16. R. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed., Kluwer
Academic Publishers, 2001.
17. N. M. Abdel-Rahim and J. E. Quaicoe, Analysis and Design of a Multiple Feedback Loop
Control Strategy for Single-Phase Voltage-Source UPS Inverters, IEEE Transactions on
Power Electronics, vol. 11, no. 4, July 1996, IEEE, pp. 532541.
18. J. F. Chen, L. Y. Chiang, C. L. Chu, Y. L. Lee, and T. J. Liang, Study and Implementation
of the Single-Phase Three-Wire Photovoltaic Energy Conversion System, in Proc. IEEE
International Conference on Power Electronics and Drive Systems, 1999, pp. 692695.
19. A. Kawamura and T. Yokoyama, Comparison of Five Control Methods for Digitally
Feedback Controlled PWM Inverters, in Proc. EPE, vol. 2, 1991, pp. 035040.
20. M. J. Ryan, W. E. Brumisckle, and R. D. Lorenz, Control Topology Options for SinglePhase UPS Inverters, IEEE Transactions of Industry Applications, vol. 33, no. 2,
March/April 1997, IEEE, pp. 493501.
21. M. J. Ryan and R. D. Lorenz, A Synchronous-Frame Controller for a Single-Phase Sine
Wave Inverter, in Proc. IEEE Applied Power Electronics Conference, vol. 2, 1997, pp. 813
819.
22. E. A. Elsayed, Reliability Engineering, Addison Wesley Longman, Inc., 1996.
23. IEEE Recommended Practice for the Design of Reliable Industrial and Commercial Power
Systems (IEEE Gold Book), IEEE Press, 1997. IEEE Standard 493-1997.
24. Strategic Science and Technology Development: Feasibility Study Development of High
Voltage, Low Current Power Semiconductor Devices, EPRI, Palo Alto, CA: 2004.
25. J. Donlon, E. Motto, K. Ishii, and T. Iida, Application Advantages of High-Voltage
High-Current IGBTs With Punch Through Technology, in Conference Record: IEEE
Industry Applications Annual Meeting, Oct. 1997, pp. 955960.
26. Powerex Corporation, http://www.pwrx.com/, October 2002.
27. Eupec Corporation, http://www.eupec.com/navi/ie321-1.html, October 2002.
7-2

References
28. Sensitron Corporation, http://www.sensitron.com/hv/DATASHEET1137.pdf, October 2002.

29. S. J. et al., Power Semiconductor Materials and Devices, Materials Research Society
Symposium Proceedings, Dec. 1997, Boston, MA.
30. S.J.Pearton el. al, Power Semiconductor Materials and Devices, Materials Research Society
Symposium Proceedings, Dec. 1997, Boston, MA.
31. V. Benda, J. Gower, and D. A. Grant, Power Semiconductor Devices Theory and
Applications, John Wiley & Sons.
32. B.J. Baliga, Power Semiconductor Device Figure of Merit for High-Frequency
Applications, IEEE Electron Device Letters, vol. 10, no. 10, Oct. 1989, pp. 455 457.
7-3
Program:
Overhead Distribution Systems
SINGLE USER LICENSE AGREEMENT

THIS IS A LEGALLY BINDING AGREEMENT BETWEEN YOU AND THE ELECTRIC POWER RESEARCH INSTITUTE, INC. (EPRI). PLEASE READ IT CAREFULLY BEFORE REMOVING THE WRAPPING MATERIAL.
BY OPENING THIS SEALED PACKAGE YOU ARE AGREEING TO THE TERMS OF THIS AGREEMENT. IF YOU DO NOT AGREE TO
THE TERMS OF THIS AGREEMENT,PROMPTLY RETURN THE UNOPENED PACKAGE TO EPRI AND THE PURCHASE PRICE WILL
BE REFUNDED.
1. GRANT OF LICENSE
EPRI grants you the nonexclusive and nontransferable right during the term of this agreement to use this package only for your own
benefit and the benefit of your organization.This means that the following may use this package: (I) your company (at any site owned
or operated by your company); (II) its subsidiaries or other related entities; and (III) a consultant to your company or related entities,
if the consultant has entered into a contract agreeing not to disclose the package outside of its organization or to use the package for
its own benefit or the benefit of any party other than your company.
This shrink-wrap license agreement is subordinate to the terms of the Master Utility License Agreement between most U.S.EPRI member utilities and EPRI.Any EPRI member utility that does not have a Master Utility License Agreement may get one on request.
About EPRI
EPRI creates science and technology solutions for
the global energy and energy services industry. U.S.
electric utilities established the Electric Power
Research Institute in 1973 as a nonprofit research
consortium for the benefit of utility members, their
customers, and society. Now known simply as EPRI,
the company provides a wide range of innovative
products and services to more than 1000 energyrelated organizations in 40 countries. EPRIs
multidisciplinary team of scientists and engineers
draws on a worldwide network of technical and
business expertise to help solve todays toughest
energy and environmental problems.
EPRI. Electrify the World
2. COPYRIGHT
This package, including the information contained in it, is either licensed to EPRI or owned by EPRI and is protected by United States
and international copyright laws.You may not, without the prior written permission of EPRI, reproduce, translate or modify this package, in any form, in whole or in part, or prepare any derivative work based on this package.
3. RESTRICTIONS
You may not rent, lease, license, disclose or give this package to any person or organization, or use the information contained in this
package, for the benefit of any third party or for any purpose other than as specified above unless such use is with the prior written
permission of EPRI.You agree to take all reasonable steps to prevent unauthorized disclosure or use of this package. Except as specified above, this agreement does not grant you any right to patents, copyrights, trade secrets, trade names, trademarks or any other
intellectual property, rights or licenses in respect of this package.
4.TERM AND TERMINATION
This license and this agreement are effective until terminated.You may terminate them at any time by destroying this package. EPRI has
the right to terminate the license and this agreement immediately if you fail to comply with any term or condition of this agreement.
Upon any termination you may destroy this package, but all obligations of nondisclosure will remain in effect.
5. DISCLAIMER OF WARRANTIES AND LIMITATION OF LIABILITIES
NEITHER EPRI,ANY MEMBER OF EPRI,ANY COSPONSOR, NOR ANY PERSON OR ORGANIZATION ACTING ON BEHALF
OF ANY OF THEM:
(A) MAKES ANY WARRANTY OR REPRESENTATION WHATSOEVER, EXPRESS OR IMPLIED, (I) WITH RESPECT TO THE USE
OF ANY INFORMATION,APPARATUS, METHOD, PROCESS OR SIMILAR ITEM DISCLOSED IN THIS PACKAGE, INCLUDING
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, OR (II) THAT SUCH USE DOES NOT INFRINGE ON OR
INTERFERE WITH PRIVATELY OWNED RIGHTS, INCLUDING ANY PARTYS INTELLECTUAL PROPERTY, OR (III) THAT THIS
PACKAGE IS SUITABLE TO ANY PARTICULAR USERS CIRCUMSTANCE; OR
(B) ASSUMES RESPONSIBILITY FOR ANY DAMAGES OR OTHER LIABILITY WHATSOEVER (INCLUDING ANY CONSEQUENTIAL DAMAGES, EVEN IF EPRI OR ANY EPRI REPRESENTATIVE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
DAMAGES) RESULTING FROM YOUR SELECTION OR USE OF THIS PACKAGE OR ANY INFORMATION, APPARATUS,
METHOD, PROCESS OR SIMILAR ITEM DISCLOSED IN THIS PACKAGE.
6. EXPORT
The laws and regulations of the United States restrict the export and re-export of any portion of this package, and you agree not to
export or re-export this package or any related technical data in any form without the appropriate United States and foreign government approvals.
7. CHOICE OF LAW
This agreement will be governed by the laws of the State of California as applied to transactions taking place entirely in California
between California residents.
8. INTEGRATION
You have read and understand this agreement, and acknowledge that it is the final, complete and exclusive agreement between you
and EPRI concerning its subject matter, superseding any prior related understanding or agreement. No waiver, variation or different
terms of this agreement will be enforceable against EPRI unless EPRI gives its prior written consent, signed by an officer of EPRI.
2004 Electric Power Research Institute (EPRI), Inc. All rights

reserved. Electric Power Research Institute and EPRI are registered
service marks of the Electric Power Research Institute, Inc.
EPRI. ELECTRIFY THE WORLD is a service mark of the Electric
Power Research Institute, Inc.
Printed on recycled paper in the United States of America
1002159
EPRI 3412 Hillview Avenue, Palo Alto, California 94304 PO Box 10412, Palo Alto, California 94303 USA
800.313.3774 650.855.2121 askepri@epri.com www.epri.com

Epri TR1002159

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Epri TR1002159

Caricato da

Copyright:

Formati disponibili

Development of a New Multilevel

Converter-Based Intelligent Universal

Development of a New Multilevel

Final Report, March 2004

EPRI Project Manager

DISCLAIMER OF WARRANTIES AND LIMITATION OF LIABILITIES

To estimate the efficiency, cost, and reliability of the proposed design

EPRI Licensed Material

Low-voltage IGBT based inverter

EPRI Licensed Material

Identifying Opportunities to Add Value Using All-Solid-State Transformer

EPRI Licensed Material

EPRI Licensed Material

aid in real-time voltage regulation; and a provider of advanced distribution automation

Need suitable high-voltage, low-power IGBT or alternate device to be competitive with

Lower efficiency than the conventional transformer.

Requires power electronics on the high-voltage side.

Higher EMI than conventional transformer.

Lack of customer acceptance and willingness to try new untested technologies

EPRI Licensed Material

Selection of the circuit topology for the power stage

Determination of design packaging and thermal management systems

EPRI Licensed Material

EPRI Licensed Material

FIELD Deployment Schedule

Total Cost of Design

Cost estimate for the 5-level 15-kV IUT

Heat sink and packing

3-level power circuit

EPRI Licensed Material

EPRI Licensed Material

EPRI Licensed Material

EPRI Licensed Material

2 DESIGN OF THE POWER STAGE ........................................................................................2-1

EPRI Licensed Material

A. Behavior Circuit Modeling ..........................................................................................3-16

EPRI Licensed Material

ABB Power Electronics-Based Distributed Transformer .....................................................4-23

EPRI Licensed Material

Critical Technology Areas...............................................................................................6-27

EPRI Licensed Material

EPRI Licensed Material

EPRI Licensed Material

EPRI Licensed Material

EPRI Licensed Material

EPRI Licensed Material

Table 6-6 Basic Material Properties of Si and SiC...................................................................6-24

EPRI Licensed Material

EPRI Licensed Material

Selection of the circuit topology for the power stage

EPRI Licensed Material

Determination of design packaging and thermal management systems

Subsequent sections provide a brief overview of present-day distribution transformers based on

The Good Old Distribution Transformer

EPRI Licensed Material

PAD MOUNTED TRANSFORMERS

EPRI Licensed Material

34.5 and below

600 and below

34.5 and below

600 and below

34.5 and below

600 and below