Frequency Response of Amplifiers and 3-Db Bandwidth

(3349) - 2004
Frequency Response of Amplifiers
Ching-Yuan Yang
National Chung-Hsing University
Department of Electrical Engineering
Overview
z Reading
B. Razavi Chapter 6.
z Introduction
In this lecture, we study the response of single-stage and differential
amplifiers in the frequency domain. Following a review of basic concepts, we
analyze the high-frequency behavior of common-source and common-gate
stages and source followers. Next, we deal with cascode and differential
amplifiers. Finally, we consider the effect of active current mirrors on the
frequency response of differential pairs.
Analog-Circuit Design
6-1
Ching-Yuan Yang / EE, NCHU
Miller effect
z Application of Miller effect to a floating impedance
That is,
Z1 =
V
1 Y
VX
Z 2 = Z
V
1 X
VY
V X VY V X
=
Z
Z1
VY V X = VY
Z2
Z
6-2
Association of poles with nodes

z Cascade of amplifiers
The overall transfer function can be written as
A2
1
Vout
A1
(s ) =
1 + RSCin s 1 + R1CN s 1 + R2C P s

Vin
We may say each node in the circuit contributes one pole to the transfer function.
The pole is determined by the total capacitance seen from each node to ground
multiplied by the total resistance seen at the node to ground.
In general, the transfer function is given as
A
Vout
(s ) = js = Av 1 s
j
j
Vin
1+
1+
1
where each pole with one node of the circuit, i.e., j = j , where j is the product
of the capacitance and resistance seen at node j to ground.
6-3
Common-source stage
z High-frequency model of a CS stage
(Assume = 0 and M1 operates in saturation)
At the input node, the total capacitance seen
from X to ground is equal to
Cin = CGS + (1 Av)CGD,
where Av = gmRD.
The input pole is in =
RS [CGS
(Miller multiplication)
1
+ (1 + gm RD )CGD ]
At the output node, the total capacitance seen to ground is equal to

Cout = CDB + (1 Av1)CGD CDB + CGD
The input pole is
out =
1
RD (C DB + CGD )
6-4
Common-source stage (contd)

z Model for calculation of output impedance
(If RS is relative large, the effect of RS is neglected.)
The output pole: Z X =
where Ceq =
C + CGS 1
1
|| GD
Ceq s CGD
gm1
CGDCGS
CGD + CGS
Thus, the output pole is roughly equal to out =
Finally, we surmise that the transfer function is
6-5
RD
1
CGD + CGS 1
(Ceq + C DB )
gm1
CGD
Vout
gm RD
(s ) =
Vin
s
s
1 +
1 +
in
out

z Equivalent circuit of CS stage
V X Vin
+ V X CGS s + (V X Vout )CGD s = 0
RS
(V V )C s + g V + V 1 + C s = 0
X
GD
m X
out
DB
out
RD
zero
(CGD s gm )RD
Vout
(s ) =
Vin
RS RDs 2 + [RS (1 + gm RD )CGD + RSCGS + RD (CGD + C DB )]s + 1
poles
where = CGSCGD + CGSCDB + CGDCDB.
Note the transfer function is of second order even through the circuit contains three
capacitors. While the denominator appears rather complicated, it can yield intuitive
expressions for the two poles, p1 and p2, if we assume |p1|<< |p2|. Writing the
denominator as
s
s
1
1
s2
D =
+ 1
+ 1 =
+
+
s + 1
p1 p 2
p2
p1
p 2
p1
6-6

If p2 is much farther from p1 (i.e., |p1| << |p2|), then
D=
s2
p1 p 2
s2
p1 p 2
1
1
+
+
s + 1
p
1
p2
1
+
s +1
p1
We obtain
p1 =
p2 =
1
RS (1 + gm RD )CGD + RSCGS + RD (CGD + C DB )
1
p1 RS RD (CGSCGD + CGSC DB + CGDC DB )
If RD(CGD + CDG) is negligible, then
p1
RS (1 + gm RD )CGD + RSCGS + RD (CGD + C DB )

RS RD (CGSCGD + CGSCDB + CGDC DB )
1
= in
RS [CGS + (1 + gm RD )CGD ]
If CGS >> (1 + gmRD)CGD + RD(CGD + CDB)/RS ,

then p 2
1
RSCGS
=
= out
RS RD (CGSCGD + CGSC DB ) RD (CGD + C DB )
6-7

z Feedforward path through CGD
The transfer function exhibits a zero given by z = +gm/CGD. Located in

the right half plane, the zero arises from direct coupling of the input to the
output through CGD at very high frequency. Note that a zero in the right
half plane introduces stability issues in feedback amplifiers
6-8

z Calculation of the zero in a CS stage
Zero:
Vout
(s )
=0
s = sz
Vin
For a finite Vin, this means that Vout(sz) = 0 and hence the output can
be shorted to ground at the frequency with no current. Therefore, the
currents through CGD and M1 are equal and opposite:
V1CGD sz = gmV1.
That is , sz = +gm/CGD.
6-9

z Input impedance
At high frequency, the effect of the output node must be
taken into account.
I
RD
(I X gmV X )
+ X = VX
1 + RDC DB s CGD s
ZX =
1 + RD (CGD + C DB )s
VX
=
I X CGD s (1 + gm RD + RDC DB s )
1
CGS s
At frequencies where |RD(CGD + CDB)s| << 1 and
|RDCDBs| << 1 + gmRD,
1
ZX =
, indicating that the input
(1 + gm RD )CGD s
hence Z in = Z X
impedance is primarily capacitive.

In fact, if CGD is large, it provides a low-impedance path
between the gate and drain of M1, yielding the equivalent
circuit that 1/gm1 and RD appear in parallel with the input.
6-10
Source followers
z Source follower
V1CGS s + gmV1 = VoutC L s

Vin = RS [V1CGS s + (V1 + Vout )CGD s ] + V1 + Vout
Transfer function:
Vout
gm + CGS s
(s ) =
Vin
RS (CGSC L + CGSCGD + CGDC L )s 2 + (gm RSCGD + C L + CGS )s + gm
Zero: The transfer function contains a zero in the left half plane. This is because
the signal conducted by CGS at high frequencies adds with the same polarity to the
signal produced by the intrinsic transistor.
Poles: If the two poles of the transfer function are assumed far apart, then the
domain pole is
1
gm
p1
=
gm RSCGD + C L + CGS R C + C L + CGS
S GD
gm
Also, if RS = 0, then p1 = gm / (CL + CGS ) .
6-11
Source followers (contd)

z Input impedance
CGD is ignored, we have
VX =
1
IX
g I 1
+ I X + m X
CGS s
CGS s gmb C L s
Z in =
1
1
VX
g
=
+ 1 + m
I X CGS s
CGS s gmb + C L s
At relative low frequencies, gmb >> |CLs| and
1
g
1
1
1
1 + m +
=
+
CGS s
gmb gmb gmb
gmb
CGS s
gm + gmb
indicating that the equivalent input capacitance is equal to CGSgmb / (gm + gmb ).
By Miller approximation: The low-frequency gain Av = gm / (gm + gmb )
Z in
Thus, Ceq = CGS (1 Av ) = CGSgmb / (gm + gmb ), and Cin ,total = CGD +
At high-frequencies, gmb << |CLs| and Z in
1
1
gm
+
+
CGS s C L s CGSC L s 2
6-12
CGS gmb
gm + gmb
Negative resistor

z Output impedance
CGD is neglected,
V1CGS s + gmV1 = I X
V1CGS sRS + V1 = V X
Z out =
V X RSCGS s + 1
=
IX
gm + CGS s
At low frequencies, Zout 1/gm.

At very high frequencies, Zout RS, because CGS shorts the gate and source.
1
> RS
gm
1
< RS
gm
6-13

z Equivalent output impedance of a source follower
If Z1 = Zout, find R1, R2 and L:
Take R2 = 1/gm, R1 = RS 1/gm, then
Z out
=
gm
Z out
CGS s RS
gm
gm + CGS s
L=
1
gm
CGS
gm
1
RS
1
gm
1
1
1
=
+
CGS s
1 R1 Ls
RS
gm
gm
1
RS
gm
That is, the dependence of L upon RS implies that if a source follower is driven by a
large resistance, then it exhibits substantial inductive behavior.
6-14
Common-gate stage
z CG stage at high frequencies
in = CS RS
1
, where C = C + C
S
GS
SB
gm + gmb
out = ( RDCD )1, where CD = CDG + CDB

At low frequency, Av =
(gm + gmb )RD

1 + (gm + gmb )RS
(gm + gmb )RD

1
Thus, Vout (s ) = Av
=
Vin
s
s 1 + (gm + gmb )RS
1 +
1 +
in out
CS
1 +
s (1 + RDC D s )
gm + gmb + RS1
An important property of CG stage is that it exhibits no Miller multiplication of

capacitances, potentially achieving a wide band.
z Input impedance Z in
ZL
(gm + gmb )ro
1
1
, where Z L = RD
CDs
gm + gmb
Since Zin now depends on ZL, it is difficult to associate a pole with the input node.
6-15
Common-gate stage (contd)

z CG stage
Transfer function:
( VoutC L s + V1Cin s )RS
+ Vin = V1
ro ( VoutC L s gmV1 ) V1 = Vout
Vout
1 + gmro
(s ) =
Vin
roC LCin RS s 2 + [roC L + Cin RS + (1 + gmro )C L RS ]s + 1
The gain at low frequencies is equal to 1 + gmro.

Input impedance:
1
1
1
Z in =
+
gm + gmb C L s (gm + gmb )ro

As CL or s increases, Zin approaches
1/(gm + gmb ) and hence the input pole
can be defined as
p ,in =
1
Cin
RS
gm + gmb
6-16
Cascode stage
z High-frequency model of a cascode stage
Cascode stage = CS stage (input impedance) + CG stage (suppressing the miller
effect)
Gain:
VX
gm1
VA
gm 2 + gmb
g m1
CGD1
RS CGS1 + 1 +
gm 2 + gmb
Node A: p ,A =
Node X: p,X =
gm 2 + gmb2
gm 2 + gmb2
CGD1 + CDB1 + CSB 2 + CGS 2
1 +
gm1
Node Y: p ,Y =
1
RD (C DB 2 + C L + CGD 2 )
In actual design, p,X is typically chosen to be farther from the origin than the other
two. This choice plays an important role in the stability of op amps.
6-17
Cascode stage (contd)

z Simplified model of a cascode stage with a current source
VX = (VoutCY s + Iin) / (CX s)
ID2 = gmVGS2 = gm2VX = gm2 (VoutCY s + Iin) / (CX s)
g
1
ro 2 (VoutCY s + I in ) m 2 + VoutCY s (VoutCY s + I in )
= Vout
C
s
C
X
Xs
Vout
g r +1
1
= m2 o2
C
I in
CXs
1 + (1 + gm 2ro 2 ) Y + CY ro 2s
CX
for gm2ro2 >> 1 and gm2ro2CY /CX >> 1 (i.e., CY > CX ),
g
1
Vout
m2
C X s CY g + C s
I in
m2
Y
CX
hence
g g
Vout I in Vout
1
=
m1 m 2
Vin Vin I in
CY C X s gm 2 /C X + s
We can find that the pole at node X is given by gm2 / CX .

Neglecting CGD1 and CY, we have Zout = (1 + gmro2)ZX + ro2, where ZX = ro1||(CX s)1.
6-18
Differential pair
z Half-circuit equivalent
z Differential pair
z Equivalent circuit for common-mode input
Av ,CM
gm RD
C L s
(gm1 + gm 2 ) ro 3 1 + 1
CP s
If the output pole is much farther from the origin than

is the pole at node P, the common-mode rejection of
the circuit degrades considerably at high frequencies.
6-19
10
Differential pair (contd)

z Effect of high-frequency supply noise in differential pair
If the supply voltage contains high-frequency noise and the circuit exhibits
mismatches, the resulting common-mode distance at node P leads to a differential
noise component at the output.
A trade-off between voltage headroom and CMRR: To minimize the headroom

consumed by M3, its width is maximized, introducing substantial capacitance at the
sources of M1 and M2 and degrading the high-frequency CMRR. The issue
becomes more serious at low supply voltages.
6-20

z Differential pair with current-source loads
Node G is an ac ground.
The output pole is given by out =

(ro1 ro 3 )C L
6-21
, the dominant pole.

11

z High-frequency behavior of differential pair with active current mirror
Mirror pole: p ,E =
gm 3
, where CE denotes the total capacitance at E to ground.
CE
CE: CGS3, CGS4, CDB3, CDB1, and the miller effect of CGD1 and CGD4.
6-22

z High-frequency model of differential pair with active current mirror
Thevenin equivalent: VX = gmN roN Vin, RX = 2roN.
Assumed 1/gmP << roP ,
VE = (Vout
1
C E s + gmP
VX )
1
+ RX
C E s + gmP
and gm 4VE I X = Vout C L s + roP1 , we have
Vout
gmN roN (2gmP + CE s )
=
Vin
2roP roN CEC L s 2 + [(2roN + roP )C E + roP (1 + 2gmProN )C L ]s + 2gmP (roN + roP )
Since the miller pole is typical quite higher in magnitude than the output pole, we get
p1
(2roN
and p 2
2gmP (roN + roP )

1
(roN roP )C L for 2gmProN >> 1

+ roP )CE + roP (1 + 2gmProN )CL
gmP
.
CE
6-23
12

In addition, there is a zero with a
2gmP
in the left half
CE
magnitude of
plane. The appearance of such a zero

is that the circuit consists of a slow
path (M1, M3 and M4) in parallel with
a fast path (M1 and M2).
Representing the two paths, we have
Vout
A0
A0
=
+
(1 + s / p1 )(1 + s / p 2 ) 1 + s / p1
Vin
=
A0 (2 + s / p 2 )
(1 + s / p1 )(1 + s / p 2 )
That is, the system exhibits a zero at

2p2.
6-24

z Determine the zero (method)
ID4
IL
For zero frequency, IL = 0 and ID4 = IX.

We have
ID4 = gmPVE
IX = VE (gmP + CE s)
Thus, gmPVE = VE (gmP + CE s)
z =
2gmP
CE
6-25
13
Small-signal analysis applies when transistors can be adequately characterized by their

operating points and small linear changes about the points.
The use of this technique has led to application of frequency-domain techniques to the
analysis of the linear equivalent circuits derived from small-signal models.
The transfer function of analog circuits to be discussed can be written in rational form
with real-valued coefficients, that is as a ratio of polynomials in Laplace Transform
variable s,
4.1.2 First order circuits
It is a first-order low-pass transfer function.

It arises naturally when a resistance and capacitance are combined.
It is often used as a simple model of more complex circuits, such as OpAmp.
Step response of first order circuits

Another common means of characterizing linear circuits is to excite the with step inputs
(such a square waveform).
4.1.3 second order low-pass H(s) with real

poles
Here, w0 is the resonant or pole frequency and Q the quality factor, K the DC gain of H(s).
Equating yields
7
wp1, wp2 are widely-spaced real poles
The step response consists of two first-order terms, and when wp1 <<wp2, the
second settles fast and for t >>1/wp2, the first term dominates.
4.1.4 Bode plot
Chapter 4 Figure 04
4.1.5 Second-order low-pass H(s) with

complex poles
Recall
Subt. In
10
4.1.5 Second-order low-pass H(s) with

complex poles
1. The step response in this case has sinusoidal term whose envelope
exponentially decays with a time constant equal to the inverse of real parts of
poles, 1/wr=2Q/w0.
2. A system with high Q factor will have oscillation and ringing for some time. The
oscillation frequency is determined by the imaginary parts of the poles.
3. In summary, when Q<0.5, the poles are real-valued and there is no overshoot.
The borderline case Q=0.5 is called maximally-damped response. When Q>0,5,
there are overshoot and ringing.
t
Chapter 4 Figure 10
Chapter 4 Figure 09
11
4.2. Frequency response of elementary

circuits
Small-signal analysis is implicitly assumed as only linear circuits can have well-defined
frequency response.
The procedure for small-signal analysis remains the same as that in Chapter 3 for
single-stage amplifiers, however parasitic capacitance are now included.
12
4.2.1 High frequency small-signal model
Chapter 4 Figure 11
Chapter 4 Figure 12
13
4.2.2 Common-source amplfier

Note: assumed that Q1, Q2 are in active mode.
Chapter 4 Figure 13
Chapter 4 Figure 14
14
If
15
One more reason why analog design is tough.
16
4.2.3 Miller effect
Chapter 4 Figure 15
17
Chapter 4 Figure 17
18
Miller effect applied to CS amplifier

Miller effect allows one to quickly estimate the 3dB bandwidth in many cases.
Chapter 4 Figure 14
Chapter 4 Figure 18
19
4.2.4 Zero-value time constant method

Except Miller effect, the most common and powerful technique for frequency response
analysis of complex circuits is the zero-value time constant analysis method.
It is very powerful in estimating a circuits 3dB bandwidth with minimal complication and
also in determine which nodes are most important.
Generally, the approach is to calculate a time-constant for each capacitor in the circuit by
assuming all other capacitors are zero, then sum all time constants to estimate the 3dB
bandwidth.
Detailed procedure:
20
Example 4.9 (page 174)
Chapter 4 Figure 14
The same as obtained previously
21
Design example 4.11 (page 177)
Chapter 4 Figure 13
In this example, the load capacitance is modest and source resistance is high, so Cgd1 may
become a major limitation of the bandwidth.
This means that W1 should be small.
So, given a current, Veff1 has to be relatively large: choose Veff1 to be 0.3V
Then suppose L1<<L2 so that rds2>>rds1 so R2=rds1 and A0=-gm1rds1
22

Then solve L1 to be
Then note that increasing drain current of Q1 while keeping Veff1=0.3V will increase gm1
and reduce rds1 roughly in proportion, which results in about the same gain, but a smaller
R2 is achieved which increase 3db bandwidth. So, bandwidth is maximized by maximizing
the drain current of Q1.
Then, we can compute the required gate width
To ensure L2>>L1, we can take L2=3L1=0.72m

Then, we can arbitrarily and conveniently set W2=3W1
Finally, Q3 is sized to provide the desired current mirror ratio
Then, need to make sure that all transistors are in active region
23
Chapter 4 Figure 13
In this example, the load capacitance is very large and source resistance is small, so C2
may become a major limitation of the bandwidth, so
24
rds=2rds1
Chapter 4 Figure 13
25
Comments
The above two design examples illustrate the manual analysis to provide an initial design
solution, which thereafter needs to be refined iteratively using simulation. A number of
challenges here:
1. there is no guarantee that the initial solution is valid or good;
2. the refinement may take many many iterations until a good design is achieved;
3. at each iteration, what are not working or good in the circuit, what parameters to
modify, and how to modify them requires in depth understanding of analog circuits.
What about those cases when it is hard to decide which capacitance dominates?
Experience counts here, after you had many designs and were aware of the biasing
conditions, capacitance conditions?
The time domain response of common-source amplifier? (two widely spaced poles)
26
4.2.6 Common-gate amplifier
Chapter 3 Figure 09
Chapter 4 Figure 20
27
We estimate the time constant associated with Cgs (note that Cgs is connected between
source and ground therefore may need to include Csb).
Superior 3dB bandwidth, but input impedance is too small.

28
Chapter 4 Figure 21
4.3 Cascode gain stage

Compared to CS amplifier, CG amplifier has much better 3dB bandwidth, but much
smaller input impedance.
To achieve a good tradeoff, we can combine a CG amplifier with a CS amplifier.
rin2
Chapter 4 Figure 22
Telescopic
Folded-cascode
29
Small-signal model for the cascode
rin2
Chapter 4 Figure 23
Using zero-value time constant method
Cout=Cgd2+Cdb2+ CL+Cbias
Cs2=Cdb1+Csb2+Cgs2
Please derive Rout

See slides 30 (Ch3)
The total resistance seen at the drain of Q1 is
See Slide 21
Miller effect
30
On the Miller effect on Cgd1
Chapter 4 Figure 24
31
Example 4.13, 4.14 (page 184-185)
This approximation is valid since Rs is the same order as rds
Recall that a large gain of the cascode amplifier requires the Ibias to have an
output resistance on the order of
In this case, and especially when
there is also a large load capacitance CL, the output time constant
would dominate.
32
4.3 Source follower amplifier

The SF amplifier may have complex poles and therefore ringing and overshoot may
happen for a pulse input.
Q1
Chapter 4 Figure 26
Norton equivalent circuit

33
Chapter 4 Figure 27
Chapter 4 Figure 28
Cs=CL+Csb1
34
Next we find the admittance Yg looking into the gate of Q1 (but not
including Cgd1 as it is already combined into Cin).
Recall Q<0.5 if no overshoot
35
If load capacitor Cs is very large compared to other capacitors such that
then
Note Cs = Cs * Rs, where Rs
| || rds2
The resistance looking into the source of Q1

As RL = 0 in this case
36
4.5 Differential pair

When using T model for differential pair, the analysis may be simpler compared to the
hybird-pi model.
CL
Vs
Chapter 4 Figure 32
37
4.5.2 Symmetric differential pair

In the small-signal model, half circuit is analyzed to allow simpler analysis.
Also note that the Vs node is small-signal ground due to symmetry, so Csb1 and Csb2 can
be neglected.
The half circuit corresponds to that of a CS amplifier, so the 3dB bandwidth is either
Where R2 = RD||rds1
or
1/[R2 * (Cgd1 + Cdb1 + CL)]
Which one is the 3dB bandwidth depends on the CL.
38
Active loaded differential pair

Again note that Vs is at small-signal ground, so half circuit can be used for analysis.
Again the load capacitor will determine which one is the 3dB bandwidth.
Vs
f b1
fb2
1
2 (ro1 // ro 3 )[C L C gd1 C gd 3 Cdb1 Cdb3 ]
1
2 Rs [(1 g m1 (ro1 // ro 3 ))C gd1 C gs1 ]
39
Current-mirror loaded differential pair

Capacitance at input node of the current mirror:
Capacitance at the output node:
From Miller effect
Note that Q1 will conduct an current of gmVid/2

flowing through Q3 (the parallel of 1/gm3 and Cm),
where we neglected the effect of rds1 and rds2, so
Chapter 3 Figure 19
Va

Va
-Ix4
Cm
Va
-Ix4
Io
RL
CL
-Ix4-Ix3
41

Cm
We can them multiply Gm with the total load

impedance to obtain the voltage Vo
Io
RL CL
Compared to the fully differential version, the current-mirror differential amplifier

adds one more pole to the transfer function, therefore may significantly affect the
frequency response.
42
Simplified small-signal model for

If output load capacitance is dominated, then the following simple model can be used.
Chapter 4 Figure 37
43
Chapter 4 Figure 34
44
Chapter 4 Figure 35
45
Chapter 4 Figure 36
46
(3349) - 2004
Stability and Frequency Compensation
Ching-Yuan Yang
National Chung-Hsing University
Department of Electrical Engineering
Overview
z Reading
B. Razavi Chapter 10.
z Introduction
In this lecture, we deal with the stability and frequency compensation of
linear feedback systems to the extent necessary to understand design
issues of analog feedback circuits. Beginning with a review of stability
criteria and the concept of phase margin, we study frequency compensation,
introducing various techniques suited to different op amp topologies. We
also analyze the impact of frequency compensation on the slew rate of twostage op amps.
10-1
Basic negative-feedback system

z General considerations
Y
H (s)
Close-loop transfer function: X (s ) = 1 + H ( s)

if H(s = j1) = 1, the gain goes to infinity,
and the circuit can amplify is own noise until
it eventually begins to oscillate at frequency
1.
Barkhausens Criteria:
|H(s = j1)| = 1
H(s = j1) = 180o .
The total phase shift around the loop at 1 is 360o because negative
feedback itself introduces 180o of phase shift. The 360o phase shift is
necessary for oscillation since the feedback must add in phase to the
original noise to allow oscillation buildup. By the same token, a loop
gain of unity (or greater) is also required to enable growth of the
oscillation amplitude.
10-2
Bode diagram of loop gain

z A negative feedback system may oscillate at 1 if
(1) the phase shift around the loop at this frequency is so much that the
feedback becomes positive.
(2) the loop gain is still enough to allow signal buildup.
Unstable system
Stable system
10-3
Time-domain response
Pole frequency sP = jP + P
Root locus:
P > 0, unstable with growing

amplitude
(a)
P = 0, unstable with constantamplitude oscillation

(b)
P < 0, stable
(c)
10-4
Bode plots of one-pole system

z Assuming H(s) = A0/(1 + s/0), is less than or equal to unity and does
not depend on the frequency, we have
A0
Y
H (s)
1 + A0
(s ) =
=
s
X
1 + H ( s ) 1 +
0 (1 + A0 )
Root locus: sP = 0(1 + A0)
z Bode plots of loop gain:
20dB/dec
0.10
A single pole cannot contribute a

phase shift greater than 90o and
the system is unconditionally
stable for all non-negative
valuesof .
100
10-5
Bodes plots of two-pole system

z Assuming the open-loop transfer function
H ( s) =
A0
1 + s 1 + s

p1
p2
The system is stable because |H| drops to below

unity at a frequency for which H < 180o.
To reduce the amount of feedback, we decrease
, obtaining the gray magnitude plot in the figure.
For a logarithmic vertical axis, a change in
translates the magnitude plot vertically. Note that
the phase plot does not change.
The stability is obtained at the cost of weaker
feedback.
10-6
Bodes plots of three-pole system

z Assuming the open-loop transfer function
A0
H ( s) =
s
s
s
1 +
1 + 1 +
p1
p 2
p3
If the feedback factor decreases, the

circuit becomes more stable because the
gain crossover moves toward the origin
while the phase crossover remains
constant.
10-7
Phase margin
z Close-loop frequency and time response
Small margin
Large margin
10-8
Phase margin (contd)

z Phase margin (PM) is defined as
PM = 180o + H( = 1)
where 1 is the gain crossover frequency.
z Example
A two-pole feedback system is designed such that | H( = P2)| = 1 and
| P1| << | P2|.
Since H reaches 135o at
= P2, the phase margin is

equal to 45o.
10-9
How much phase margin is adequate?

z For PM = 45o, at the gain crossover frequency H(1) = 135o and
H ( j1 )
H ( j1 )
|H(1)| = 1, yielding Y =
=
X
1 + 1 exp( j135)
1
0.29 0.71 j
1.3
It follows that X = 0.29 0.71 j
The frequency response of the feedback

system suffers from a 30% peak at = 1.
z Close-loop frequency response for 45o
phase margin:
10-10
How much phase margin is adequate? (contd)

z Close-loop time response for 45o, 60o, and 90o phase margin:
z For PM = 60o, Y(j1)/X(j1) = 1/, suggesting a negligible frequency peaking.

This typically means that the step response of the feedback system exhibits
little ringing, providing a fast settling. For greater phase margins, the system
is more stable but the time response slows down. Thus, PM = 60o is typically
considered the optimum value.
z The concept of phase margin is well-suited to the design of circuits that
process small signals. In practice, the large-signal step response of
feedback amplifiers does not follow the illustration of the above figure. For
large-signal applications, time-domain simulations of the close-loop system
prove more relevant and useful than small-signal ac computations of the
open-loop amplifier.
10-11
How much phase margin is adequate? (contd)

z Example:
Unity-gain buffer: PM 65o, unity-gain frequency = 150 MHz.
However, the large-signal step response suffers from significant ringing.
z The large-signal step response of feedback amplifiers is not only due to

slewing but also because of the nonlinear behavior resulting from large
excursions in the bias voltages and currents of the amplifier. Such
excursions in fact cause the pole and zero frequencies to vary during the
transient, leading to a complicated time response. Thus, for large-signal
applications, time-domain simulations of the close-loop system prove more
relevant and useful than small-signal ac computations of the open-loop
amplifier.
10-12
Frequency compensation
z Typical op amp circuits contain many poles. For this reason, op amps must
usually be compensated, that is, the open-loop transfer function must be
modified such that the closed-loop circuit is stable and the time response is
well-behaved.
z Stability can be achieved by minimizing the
overall phase shift, thus pushing the phase
crossover out.
Moving PX out
Discussion:
This approach requires that we attempt
to minimize the number of poles in the
signal path by proper design.
Since each additional stage contributes
at least one pole, this means the number
of stages must be minimized, a remedy
that yields low voltage gain and/or limited
output swings.
10-13
Frequency compensation (contd)
z Stability can be achieved by dropping

the gain thereby pushing the gain
crossover in.
Discussion:
Moving GX in
This approach retains the low

frequency gain and the output
swings but it reduces the
bandwidth by forcing the gain
to fall at lower frequencies.
10-14
Telescopic op amp with single-ended output

Determine the poles of the circuit:
We identify a number of poles in the signal paths:
path 1 contains a high-frequency pole at the source
of M3, a mirror pole at node A, and another
high-frequency pole at the source of M7, whereas
path 2 contains a high-frequency pole at the source
of M4. The two paths share a pole at the output.
Dominant pole: the closest to the origin.
p,out = 1/(RoutCL), usually sets the open-loop
3-dB bandwidth.
Nondominant poles:
p,A = gm5/CA, the closest pole to the origin after p,out.
Pole locations:
(mirror pole) where CA = CGS5 + CGS6 + CDB5 + 2CGD6 + CDB3 + CGD3.
p,N = gm7/CN, p,X = gm3/CX = gm4/CY = p,Y.
Since gm = 2ID/|VGS VTH|, if M4 and M7 are
designed to have the same overdrive, they exhibit
the same transconductance. From square-law characteristics, we have
W4/W7 = p/n 1/3. Thus, nodes N and X(Y) see roughly equal small-signal
resistances but node N suffers from much more capacitance.
z
10-15
Telescopic op amp with single-ended output (contd)

z Bode plots of loop gain for op amp: using = 1 for the worst case.
The mirror pole p,A typically limits the phase margin because its phase
contribution occurs at lower frequencies than that other nondominant
poles.
10-16

z Translating the dominant pole toward origin to compensate the op amp:
Assuming p,A > 10 p,out, we must force
the loop gain crossover point moves
toward the origin. We can simply lower
the frequency of the dominant pole
( p,out) by increasing the load capacitance.
The key point is that the phase contribution
of the dominant pole in the vicinity of the
gain or phase crossover points is close to
90o and relatively independent of the
location of the pole. That is, translating
the dominant pole toward the origin affects
the magnitude plot but not the critical part
of the phase plot.
10-17

z
How much the dominant pole must be

shift down?
Assume (1) the 2nd nondominant pole
(p,N) is quite higher than the mirror
pole so that the phase shift at = p,A
is equal to 135o, and (2) PM = 45o.
CL (p,out/p,out)CL. The load
capacitance must be increased
by a factor of p,out/p,out.
The unity-gain bandwidth of the
compensated op amp is equal to the
frequency of the nondominant pole.
To achieve a wideband in a
feedback system employing an
op amp, the first nondominant
pole must be as far as possible.
Although p,out = (RoutCL)1, increasing
Rout does not compensate the op amp.
A higher Rout results in a greater gain,
only affecting the low-frequency
portion of the characteristics.
10-18
Fully differential telescopic op amp
CN = CGS5 + CSB5 + + CGD7 + CDB7

ZN = ro7 || (CN s)1, where body effect is neglected. We have
(1 + g m5 ro5 )ro 7
1
ro 7
Z out
=
Z out = (1 + g m5 ro5 )Z N + ro 5 (1 + g m5 ro 5 )
C
s
[
1
+
g
r
(
ro 7 C N s + 1 ,and
L
m 5 o 5 )ro 7 C L + ro 7 C N ]s + 1
z A pole with = (1 + gm5ro5)ro7CL + ro7CN, where (1 + gm5ro5)ro7CL is simply due to the
low-frequency output resistance of the cascode. The pole in the PMOS cascode is
merged with the output pole, thus creating no addition pole. It merely lowers the
dominant pole by a slight amount.
z For gmro >> 1 and CL > CN, then gm5ro5ro7CL.
z
10-19
10
Compensation of two-stage op amps
z We identify three poles at X(orY), E(orF) and A(orB).

A pole at X(orY) lies at relatively high frequencies. Since the small-signal
resistance seen at E is quite high, even the capacitances of M3, M5 and M9
can create a pole relatively close to the origin. At node A, the small-signal
resistance is lower but the value of CL may be quite high. Consequently, the
circuit exhibits two dominant poles.
z One of the dominant poles must be moved toward the origin so as to place
the gain crossover well below the phase crossover. If the magnitude of p,E
is to be reduced, the available bandwidth is limited to approximately p,A, a
low value. Furthermore, this required dominant pole translates to a very
large compensation capacitor.
10-20
Miller compensation of a two-stage op amp
z In a two-stage amp as shown in Fig.(a), the first stage exhibits a high output
impedance and the second stage provides a moderate gain, thereby
providing a suitable environment for Miller multiplication of capacitors.
1
z In Fig.(b), we create a large capacitance at E, the pole is p , E = R [C + (1 + A )C ]

out 1
E
v2
C
As a result, a low-frequency pole can be established with a moderate
capacitor value, saving considerable chip area.
z In addition to lowering the required capacitor value, Miller compensation
entails a very important property: it moves the output pole away from the
origin. (pole splitting)
10-21
11
Miller compensation of a two-stage op amp (contd)

z
z
z
Pole splitting as a result of Miller compensation.
Discussion
Two poles: (based on the assumption |p,1| << |p,2|)
1
Simplified circuit of a two-stage op amp:
p1
RS [(1 + g m9 RL )(CC + CGD 9 ) + C E ] + RL (CC + CGD 9 + C L )
RS = the output resistance of 1st stage.
p2
RS [(1 + g m9 RL )(CC + CGD 9 ) + C E ] + RL (CC + CGD9 + C L )

RS RL [(CC + CGD 9 )C E + (CC + CGD9 )C L + C E C L ]
RL = ro9 || ro11
For CC = 0 and relatively large CL, p,2 1/(RLCL).

For CC 0 and CC + CGD9 >> CE, p,2 gm9/(CE + CL).
Typically CE << CL, we conclude that Miller
compensation increases the magnitude of the output
pole (p,2) by a factor of gm9RL, a relatively large value.
Miller compensation moves the interstage pole toward the origin and the output pole
away from the origin, allowing a much greater bandwidth than that obtained by merely
connect the compensation capacitor from one node to ground.
10-22

z Effect of right half plane zero
The circuit contains a right-half-plane zero at
z = gm9/(CC + CGD9) because CC + CGD9
forms a parasitic signal path from the input
to the output.
A zero in the right hand plane contributes
more phase shift, thus moving the phase
crossover toward the origin. Furthermore,
from Bode approximations, the zero slows
down the drop of the magnitude, thereby
pushing the gain crossover away from the
origin. As a result, the stability degrades considerably.
For two-stage op amps, typically |p1| < |z| < |p2|,
the zero introduces significant phase shift while
preventing the gain from falling sufficiently.
The right-half-plane zero is a serious issue
because gm is relatively small and CC is chosen
large enough to position the dominant pole properly.
10-23
12
z Addition of Rz to move the right hand plane zero.
The zero is given by .

If Rz g m19 , then z 0.
We may move the zero well into the left plane so as to cancel the first
nondominant pole. That is
C + C E + CC C L + CC
1
g m9
, because CE << CL + CC .
=
Rz = L
1
CC ( g m9 Rz )
CL + CE
g m9CC
g m9CC
Drawbacks:
1. It is difficult to guarantee the relationship of the above equation,
especially if CL is unknown or variable.
2. The actual implementation of Rz is variable. Rz is typically
realized by a MOS transistor in the triode region.
10-24

z Generation of Vb for proper temperature and process tracking.
If I1 is chosen with respect to ID9 such that

VGS13 = VGS9, then VGS15 = VGS14.
Since gm14 = pCox(W/L)14(VGS14 VTH14)
and Ron15 = [pCox(W/L)15(VGS15 VTH15)]1,
we have Ron15 =
(W / L)14
g m14 (W / L)15
(W / L)14
For pole-zero cancellation to occur, g m14 (W / L)15

and hence (W / L)15 = (W / L)14 (W / L)9
C L + CC
g m9CC
I D9
CC
I D14 CC + C L
If CL is constant, it can be established with reasonable accuracy

because it contains only the ratio of quantities.
10-25
13

z Method of defining gm9 with respect to RS.
Goal:
Rz =
C L + CC
g m 9 C C (A)
The technique incorporates Mb1-Mb4

along with RS to generate I b RS2
Thus, g m 9
I D 9 I D11 RS1
Proper ratioing of RZ and RS therefore

ensures (A) is valid even with temperature
and process variations
10-26
Effect of increased load capacitance on step response

Two-stage op amps:
One-stage op amps:
z In one-stage op amps, a higher load capacitance brings the dominant pole

closer to the origin, improving the phase margin (albeit making the feedback
system more overdamped).
z In two-stage op amps, since Miller compensation establishes the dominant
pole at the output of the first stage, a higher load capacitance presented to
the second stage moves the second pole toward the origin, degrading the
phase margin.
z Illustrated in the figure is the step response of a unity-gain feedback
amplifier, suggesting that the response approaches an oscillatory behavior if
the load capacitance seen by the two-stage op amp increases.
10-27
14
Slewing in two-stage op amps

Positive slewing:
negative slewing:
z The positive slew rate equals ISS /CC. During slewing, M5 must provide two
currents: ISS and I1. If M5 is not wide enough to sustain ISS + I1 in saturation,
then VX drops significantly, possibly driving M1 into the triode region.
z During negative slew rate, I1 must support both ISS and ID5. For example,
if I1 = ISS, then VX rises so as to turn off M5. If I1 < ISS, then M3 enters the
triode region and the slew rate is given by ID3 /CC.
10-28
Compensation technique using a source follower

z Two-stage op amp with right half plane zero due to CC:
z Addition of a source follower to remove zero:
Equivalent circuit:
Source follower
Since CGS of M2 is typically much less than CC, we

expect the right frequencies.
Vout
1
(1 + RLC L s )
gm1V1 = Vout (R L + C L s ) V1 =
gm1R L
Vout V1
V
and
+ I in = 1 , then
1
1
RS
+
Zero in the left hand plane
gm 2 CC s
Vout
gm1RLRS (gm2 + CCs)
=
Vin RLCLCC (1 + gm2RS )s2 + [(1 + gm1gm2RLRS )CC + gm2RLCL ]s + gm2
Assume p1 << p2, since typically 1 + gm2RS >> 1,

(1 + gm1gm2RLRS)CC >> gm2RLCL, we have
1
g
1
g
p1
m1 )
and p 2 m1 (Note p2:
gm1R L RSCC
RLCL
CL
CL
10-29
15
Compensation technique using a CG stage

Equivalent circuit:
z The primary issue is that the source follower limits the lower end of the
output voltage to VGS2 + VI2. In the CG topology, CC and the CG stage M2
convert the output voltage swing to a current, returning the result to the
gate of M1.
V1
1
+ g m 2V2 , we obtain
+ C L s = g m 2V2 and I in =
RS
RL
z Vout + g m 2V2 = V2 , g m1V1 + Vout

CC s
Vout
g m1 RS RL ( g m 2 + CS s )
=
I in RL CL CC s 2 + [(1 + g m1RS )g m 2 RLCC + CC + g m 2 RL CL ]s + g m 2
Using approximations, p1
1
g m1 RL RS CC
and p 2
10-30
g m 2 RS g m1
.
CL
Compensation technique using a CG stage (contd)

Positive slewing:
z
For positive slewing, M2 and I1 must support ISS,

requiring I1 ISS + ID1. If I1 is less, then VP drops,
turning M1 off, and if I1 < ISS, M0 and its tail
current source must enter the triode region,
yielding a slew rate equal to I1/CC.
For negative slewing, I2 must support both ISS

and ID2. As ISS flows into node P, VP tends to rise,
increasing ID1. Thus, M1 absorbs the current
Negative slewing:
produced by I3 through CC, tuning off M2 and

opposing the increase in VP. We can therefore
consider P a virtual ground node.
z
For equal positive and negative slew rates, I3

(and hence I2) must be as large as ISS, raising the
power dissipation.
10-31
16
Alternative method of compensation two-stage op amps
10-32
17

Frequency Response of Amplifiers and 3-Db Bandwidth

Caricato da

Informazioni sul documento

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Frequency Response of Amplifiers and 3-Db Bandwidth

Caricato da

Copyright:

Formati disponibili

(3349) - 2004

Frequency Response of Amplifiers

Ching-Yuan Yang / EE, NCHU

Ching-Yuan Yang / EE, NCHU

Association of poles with nodes

The overall transfer function can be written as

1 + RSCin s 1 + R1CN s 1 + R2C P s

Ching-Yuan Yang / EE, NCHU

At the output node, the total capacitance seen to ground is equal to

Ching-Yuan Yang / EE, NCHU

Common-source stage (contd)

Thus, the output pole is roughly equal to out =

Finally, we surmise that the transfer function is

Common-source stage (contd)

+ V X CGS s + (V X Vout )CGD s = 0

where = CGSCGD + CGSCDB + CGDCDB.

Ching-Yuan Yang / EE, NCHU

Common-source stage (contd)

p1 RS RD (CGSCGD + CGSC DB + CGDC DB )

If RD(CGD + CDG) is negligible, then

RS (1 + gm RD )CGD + RSCGS + RD (CGD + C DB )

If CGS >> (1 + gmRD)CGD + RD(CGD + CDB)/RS ,

Ching-Yuan Yang / EE, NCHU

Common-source stage (contd)

The transfer function exhibits a zero given by z = +gm/CGD. Located in

Ching-Yuan Yang / EE, NCHU

Common-source stage (contd)

Ching-Yuan Yang / EE, NCHU

Common-source stage (contd)

impedance is primarily capacitive.

Ching-Yuan Yang / EE, NCHU

V1CGS s + gmV1 = VoutC L s

Ching-Yuan Yang / EE, NCHU

Source followers (contd)

At relative low frequencies, gmb >> |CLs| and

Ching-Yuan Yang / EE, NCHU

Source followers (contd)

At low frequencies, Zout 1/gm.

Ching-Yuan Yang / EE, NCHU

Source followers (contd)

Ching-Yuan Yang / EE, NCHU

out = ( RDCD )1, where CD = CDG + CDB

(gm + gmb )RD

(gm + gmb )RD

An important property of CG stage is that it exhibits no Miller multiplication of

(gm + gmb )ro

Ching-Yuan Yang / EE, NCHU

Common-gate stage (contd)

( VoutC L s + V1Cin s )RS

ro ( VoutC L s gmV1 ) V1 = Vout

The gain at low frequencies is equal to 1 + gmro.

gm + gmb C L s (gm + gmb )ro

Ching-Yuan Yang / EE, NCHU

Ching-Yuan Yang / EE, NCHU

Cascode stage (contd)

We can find that the pole at node X is given by gm2 / CX .

Ching-Yuan Yang / EE, NCHU

z Equivalent circuit for common-mode input

If the output pole is much farther from the origin than

Ching-Yuan Yang / EE, NCHU

Differential pair (contd)

A trade-off between voltage headroom and CMRR: To minimize the headroom

Ching-Yuan Yang / EE, NCHU

Differential pair (contd)