Low Temperature Polycrystalline Si Nanowire

Devices with Gate-All-Around Al2O3/TiN Structure

Using An Implant-Free Technique
T. I. Tsai, T. S. Chao
Dept. of Electrophysics
National Chiao Tung University
1001 Ta Hsueh Road, Hsinchu, Taiwan 300, ROC

C. J. Su2, H. C. Lin1, 2, T. Y. Huang1

1

Dept. of Electronics Engineering and Institute of

Electronics
2
Nano Facility Center

AbstractIn this work, for the first time, we propose and

demonstrate an implant-free gate-all-around (GAA) lowtemperature poly-Si (LTPS) nanowire (NW) device with Al2O3
dielectric and TiN gate. Since the channel and source/drain (S/D)
regions are sharing one in-situ phosphorous-doped poly-Si
material, the process cost could be efficiently reduced. Such novel
scheme appears to be promising for both system-on-panel (SOP)
and three dimensional IC applications. High on-off current ratio
and on-state performance are demonstrated for the new device.
Keywords- gate-all-around (GAA); Si nanowire (Si NW); insitu doped channel; low temperature poly-Si (LTPS)

I.

INTRODUCTION

Lately, numerous researches focusing on nano-scale

structures, especially nanowire (NW)-based scheme, have been
widely explored [1-3]. The inherent tiny volume and high
surface-to-volume ratio of NW Field-effect transistors (FETs)
enable better gate controllability and immunity to the short
channel effects (SCEs) over the planar MOSFETs.
Concurrently, the control on junction doping profiles of S/Dto-channel regions becomes extremely difficult in nano-scale
regimes. In line with this, junctionless devices [4] have been
proposed to overcome the doping profile issue. In this work,
we demonstrate the feasibility of fabricating GAA NW devices
with high on-off current ratio and on-state performance, using
one in-situ doped poly-Si material for both the channel and S/D
regions. Owing to the inherently tiny body of NW, the gate of
the new device is capable of depleting the heavily-doped
channel thoroughly for switching off the device.
II.

DEVICE FABRICATION

The main process flow of the proposed NWFET is briefly

illustrated in Fig. 1. First, a 200 nm wet oxide was capped on a
bare Si substrate, followed by the deposition of
nitride/TEOS/nitride stack layers. After lithographic and
anisotropic etching steps, dummy pattern of the stack was
formed, followed by the formation of sub-100 nm space by

National Chiao Tung University

1001 Ta Hsueh Road, Hsinchu, Taiwan 300, ROC

H. C. Lin, Y. J. Wei
National Nano Device Laboratories
National Applied Research Laboratories
No.26, Prosperity Road I, Hsinchu Science Park, Hsinchu,
Taiwan 300, ROC
E-mail: hclin@faculty.nctu.edu.tw

carefully-controlled lateral-etching of the TEOS oxide layer as

shown in Fig. 1(a). Deposition of the doped poly-Si as NW
channels (denoted as doped channel (DC)) and S/D regions, as
shown in Fig. 1(b), was executed using 0.49 slm SiH4 and 15
sccm PH3 in a LPCVD system, followed by an anisotropic
etching to define NW channels and S/D regions
simultaneously, as illustrated in Fig. 1(c). Note that control
devices (denoted as undoped channel (UC)) were also
processed along side with a similar flow, except the using of
undoped poly-Si as the channel with the S/D regions doped
later by ion implantation. To implement GAA structure, the
nitride/TEOS/nitride stack layers were sequentially removed,
followed by the depositions of 10 nm Al2O3 and 150 nm TiN
films to serve as gate dielectric and electrode, respectively, as
shown in Figs. 1(d), (e). The cross-sectional TEM image of the
DC split is shown in Fig. 2 with thickness of 10 nm and width
of 15 nm.
III.

RESULTS AND DISCUSSION

Fig. 3 presents the characteristics of both DC and UC

devices with tiny NW channels (Fig. 2). The DC device
displays a superior on/off current ratio of 1.26 x 107 and
subthreshold swing (SS) of 210 mV/dec. Furthermore, it shows
approximately 2.5 times peak transconductance (Gm) value
and 1.75 times output current value over the UC one. The Gm
enhancement is attributed to the much larger cross section for
carrier flow in the DC device. The threshold voltage (Vth) as a
function of gate length is illustrated in Fig. 4, indicating the
accumulation-mode operation of the DC devices. The ION,
extracted from the two types of devices at VG Vth = 2 V and
VD = 0.5 V, as a function of gate length is plotted in Fig. 5. The
ION is evidently promoted in the DC devices, especially as the
gate length is long, owing to the reduction in channel resistance
with the heavily-doped material. Fig. 6 shows the Gm as a
function of gate length. The results show that the difference in
Gm between the two splits increases with decreasing gate
length, implying the impact of parasitic S/D resistance is
diminished in the DC devices. One plausible reason for such
findings is the elimination of S/D junctions in the new scheme.

IV.

CONCLUSION

From the TEM and electrical characterizations, we

confirmed the successful operation of GAA NWFETs with
heavily-doped poly-Si channels, Al2O3 dielectric, and TiN gate
as the NW channels are sufficiently small. The fabricated
devices deliver superior on-off current ratio and on-state
performance over conventional devices with undoped channel.
ACKNOWLEDGMENT

(NDL) for their assistance in device fabrication. This work was

supported in part by the National Science Council under
contract No. NSC 99-2221-E-009-172-.
REFERENCES
[1]
[2]
[3]
[4]

C. J. Su et al., IEEE Electron Device Letters, vol. 27, pp. 582-584, 2006.
X. Duan et al., Nano Lett., vol. 2, pp. 487-490, 2002.
Y. Cui et al., Science, vol. 293, pp.1289-1292, 2001.
C. W. Lee et al., Appl. Phys. Lett., vol. 94, pp. 053511-053513, 2009.

The authors would like to thank the staff at Nano Facility

Center of the NCTU and National Nano Device Laboratories
(a)

(b)

(c)

SiN
TEOS
SiN
Thermal Oxide

Thermal Oxide

Thermal Oxide

Si Substrate

Si Substrate

Si Substrate

(e)

(d)

Source

Source

Drain

Gate

Drain
Poly-Si
NW Channel

Thermal Oxide

Thermal Oxide

Si Substrate

Si Substrate

Fig. 2 Cross-sectional TEM images of DC device with a tiny NW.

10-5
Doped channel
Undoped channel

Drain Current (A)

10-6
10-7
10-8

Transconductance Gm (nS)

Fig. 1 Schematic process flow of the new device.

(a)
(b)
3000

L=0.4m
VD=0.5 V

2000

10-9
10-10

1000

~ 2.5 times

10-11
10-12
10-13

0
-2

Gate Voltage (V)

Fig. 3 (a) Transfer and (b) output characteristics of 15 nm-width DC and

UC NWFETs.

Fig. 5 ION as a function of gate length for DC and UC devices.

Fig. 4 Vth versus gate length for DC

and UC devices.
.

Fig. 6 Gm versus gate length for DC and UC devices.

.