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LTC1418

Low Power, 14-Bit, 200ksps


ADC with Serial and Parallel I/O

FEATURES

DESCRIPTION

Single Supply 5V or 5V Operation


Sample Rate: 200ksps
1.25LSB INL and 1LSB DNL Max
Power Dissipation: 15mW (Typ)
Parallel or Serial Data Output
No Missing Codes Over Temperature
Power Shutdown: Nap and Sleep
External or Internal Reference
Differential High Impedance Analog Input
Input Range: 0V to 4.096V or 2.048V
81.5dB S/(N + D) and 94dB THD at Nyquist
28-Pin Narrow PDIP and SSOP Packages

The LTC 1418 is a low power, 200ksps, 14-bit A/D


converter. Data output is selectable for 14-bit parallel or
serial format. This versatile device can operate from a
single 5V or 5V supply. An onboard high performance
sample-and-hold, a precision reference and internal timing minimize external circuitry requirements. The low
15mW power dissipation is made even more attractive
with two user selectable power shutdown modes.
The LTC1418 converts 0V to 4.096V unipolar inputs from
a single 5V supply and 2.048V bipolar inputs from 5V
supplies. DC specs include 1.25LSB INL, 1LSB DNL
and no missing codes over temperature. Outstanding AC
performance includes 82dB S/(N + D) and 94dB THD at the
Nyquist input frequency of 100kHz.

U
APPLICATIONS

The flexible output format allows either parallel or serial I/O.


The SPI/MICROWIRETM compatible serial I/O port can operate as either master or slave and can support clock frequencies from DC to 10MHz. A separate convert start input and
a data ready signal (BUSY) allow easy control of conversion
start and data transfer.

Remote Data Acquisition


Battery Operated Systems
Digital Signal Processing
Isolated Data Acquisition Systems
Audio and Telecom Processing
Medical Instrumentation

, LTC and LT are registered trademarks of Linear Technology Corporation.


MICROWIRE is a trademark of National Semiconductor Corporation.

TYPICAL APPLICATION
Low Power, 200kHz, 14-Bit Sampling A/D Converter
5V

Typical INL Curve

10F
VDD

1.0

SER/PAR

LTC1418

D13
AIN+
14-BIT ADC

14

4.096V
REFCOMP
10F

SELECTABLE
SERIAL/
PARALLEL
PORT

BUFFER

D5
D4 (EXTCLKIN)
D3 (SCLK)
D2 (CLKOUT)
D1 (DOUT)
D0 (EXT/INT)

0.5
INL (LSBs)

S/H
AIN

0.5
8k
VREF

TIMING AND
LOGIC

2.5V
REFERENCE

1F

BUSY
CS
RD
CONVST
SHDN

1.0
0

4096

8192

12288

16384

OUTPUT CODE
AGND

VSS
(0V OR 5V)

DGND
1418 TA02
1418 TA01

LTC1418

W W

Supply Voltage (VDD) ................................................. 6V


Negative Supply Voltage (VSS)
Bipolar Operation Only ........................... 6V to GND
Total Supply Voltage (VDD to VSS)
Bipolar Operation Only ....................................... 12V
Analog Input Voltage (Note 3)
Unipolar Operation .................. 0.3V to (VDD + 0.3V)
Bipolar Operation........... (VSS 0.3V) to (VDD + 0.3V)
Digital Input Voltage (Note 4)
Unipolar Operation ................................ 0.3V to 10V
Bipolar Operation.........................(VSS 0.3V) to 10V
Digital Output Voltage
Unipolar Operation .................. 0.3V to (VDD + 0.3V)
Bipolar Operation........... (VSS 0.3V) to (VDD + 0.3V)
Power Dissipation.............................................. 500mW
Operation Temperature Range
LTC1418C................................................ 0C to 70C
LTC1418I............................................ 40C to 85C
Storage Temperature Range ................. 65C to 150C
Lead Temperature (Soldering, 10 sec).................. 300C

PARAMETER

28 VDD

27 VSS

VREF

26 BUSY

REFCOMP

25 CS

AGND

24 CONVST

D13 (MSB)

23 RD

D12

22 SHDN

D11

21 SER/PAR

D10

20 D0 (EXT/INT)

D9 10

19 D1 (DOUT)

D8 11

18 D2 (CLKOUT)

D7 12

17 D3 (SCLK)

D6 13

16 D4 (EXTCLKIN)

DGND 14

15 D5

G PACKAGE
28-LEAD PLASTIC SSOP

N PACKAGE
28-LEAD NARROW PDIP

TJMAX = 110C, JA = 95C/ W (G)


TJMAX = 110C, JA = 100C/ W (N)

Consult factory for Military grade parts.

MIN

(Note 7)

Differential Linearity Error


Offset Error

(Note 8)

Full-Scale Error

Internal Reference
External Reference = 2.5V

Full-Scale Tempco

IOUT(REF) = 0, Internal Reference, Commercial


IOUT(REF) = 0, Internal Reference, Industrial
IOUT(REF) = 0, External Reference

LTC1418
TYP
MAX

MIN

13

LTC1418A
TYP
MAX

14

UNITS
Bits

0.8

0.5

0.7

1.5

0.35

LSB

20

10

LSB

10
5

60
30

20
5

60
15

LSB
LSB

10
20
1

45

ppm/C
ppm/C
ppm/C

MAX

UNITS

15
5

1.25

LSB

(Note 5)

SYMBOL PARAMETER

CONDITIONS

VIN

Analog Input Range (Note 9)

4.75V VDD 5.25V (Unipolar)


4.75V VDD 5.25V, 5.25V VSS 4.75V (Bipolar)

IIN

Analog Input Leakage Current

CS = High

CIN

Analog Input Capacitance

Between Conversions (Sample Mode)


During Conversions (Hold Mode)

tACQ

Sample-and-Hold Acquisition Time

Commercial
Industrial

LTC1418ACG
LTC1418ACN
LTC1418AIG
LTC1418AIN
LTC1418CG
LTC1418CN
LTC1418IG
LTC1418IN

With internal reference (Notes 5, 6) unless otherwise noted.

Resolution (No Missing Codes)

A ALOG I PUT

ORDER PART
NUMBER

TOP VIEW
AIN+
AIN

CONDITIONS

Integral Linearity Error

PACKAGE/ORDER INFORMATION

(Notes 1, 2)

CO VERTER CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

MIN

TYP
0 to 4.096
2.048

V
V
1

25
5

300
300

A
pF
pF

1000
1000

ns
ns

LTC1418

W U

DY A IC ACCURACY

(Note 5)

SYMBOL PARAMETER

CONDITIONS

S/(N + D) Signal-to-Noise Plus Distortion Ratio

97.5kHz Input Signal

THD

Total Harmonic Distortion

100kHz Input Signal, First 5 Harmonics

SFDR

Spurious Free Dynamic Range

100kHz Input Signal

IMD

Intermodulation Distortion

fIN1 = 97.7kHz, fIN2 = 104.2kHz

MIN

TYP

79

81.5
94

86

Full Power Bandwidth


S/(N + D) 77dB

Full Linear Bandwidth

U
U
U
I TER AL REFERE CE CHARACTERISTICS

MAX

UNITS
dB

86

dB

95

dB

90

dB

MHz

0.5

MHz

(Note 5)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

VREF Output Voltage

IOUT = 0

2.480

2.500

2.520

VREF Output Tempco

IOUT = 0, Commercial
IOUT = 0, Industrial

10
20

45

VREF Line Regulation

4.75V VDD 5.25V


5.25V VSS 4.75V

0.05
0.05

VREF Output Resistance

0.1mA IOUT 0.1mA

DIGITAL I PUTS AND OUTPUTS


SYMBOL PARAMETER

CONDITIONS

MIN

High Level Input Voltage

VDD = 5.25V

VIL

Low Level Input Voltage

VDD = 4.75V

IIN

Digital Input Current

VIN = 0V to VDD

CIN

Digital Input Capacitance

VOH

High Level Output Voltage


Low Level Output Voltage

LSB/ V
LSB/ V
k

(Note 5)

VIH

VOL

ppm/C
ppm/C

VDD = 4.75V, IO = 10A


VDD = 4.75V, IO = 200A

VDD = 4.75V, IO = 160A


VDD = 4.75V, IO = 1.6mA

TYP

MAX

2.4

UNITS
V

0.8

10

1.4

pF

4.74

V
V

4.0
0.05
0.10

0.4

V
V

10

IOZ

Hi-Z Output Leakage D13 to D0

VOUT = 0V to VDD, CS High

COZ

Hi-Z Output Capacitance D13 to D0

CS High (Note 9)

ISOURCE

Output Source Current

VOUT = 0V

10

mA

ISINK

Output Sink Current

VOUT = VDD

10

mA

UW

POWER REQUIRE E TS

15

pF

(Note 5)

SYMBOL PARAMETER

CONDITIONS

MAX

UNITS

4.75

MIN

TYP

5.25

4.75

5.25

VDD

Positive Supply Voltage (Notes 10, 11)

VSS

Negative Supply Voltage (Note 10)

Bipolar Only (VSS = 0V for Unipolar)

IDD

Positive Supply Current

3.0
3.9
570
2

4.3
4.5

Nap Mode
Sleep Mode

Unipolar, RD High (Note 5)


Bipolar, RD High (Note 5)
SHDN = 0V, CS = 0V (Note 12)
SHDN = 0V, CS = 5V (Note 12)

mA
mA
A
A

Bipolar, RD High (Note 5)


SHDN = 0V, CS = 0V (Note 12)
SHDN = 0V, CS = 5V (Note 12)

1.4
0.1
0.1

1.8

Nap Mode
Sleep Mode

mA
A
A

Unipolar
Bipolar

15.0
26.5

21.5
31.5

mW
mW

ISS

PDIS

Negative Supply Current

Power Dissipation

LTC1418
WU
TI I G CHARACTERISTICS

(Note 5)

SYMBOL

PARAMETER

TYP

MAX

fSAMPLE(MAX)

Maximum Sampling Frequency

tCONV

Conversion Time

3.4

tACQ
tACQ + tCONV

Acquisition Time

0.3

Acquisition Plus Conversion Time

3.7

t1

CS to RD Setup Time

(Notes 9, 10)

ns

t2

CS to CONVST Setup Time

(Notes 9, 10)

40

ns

t3

CS to SHDN Setup Time to Ensure Nap Mode

(Notes 9, 10)

40

t4

SHDN to CONVST Wake-Up Time from Nap Mode

(Note 10)

t5

CONVST Low Time

(Notes 10, 11)

t6

CONVST to BUSY Delay

CL = 25pF

t7

Data Ready Before BUSY

t8

Delay Between Conversions

t9

Wait Time RD After BUSY

t10

Data Access Time After RD

CONDITIONS

(Note 10)

MIN
200

kHz

ns
500

ns
35

20
15

500

CL = 25pF
CL = 100pF

Bus Relinquish Time

70

ns

35

ns
ns
ns
ns

15

30
40

ns
ns

20

40
55

ns
ns

20
25
30

ns
ns
ns

Commercial
Industrial

ns

40

t11

UNITS

t12

RD Low Time

t13

CONVST High Time

t14

Delay Time, SCLK to DOUT Valid

CL = 25pF (Note 9)

t15

Time from Previous Data Remain Valid After SCLK

CL = 25pF (Note 9)

fSCLK

Shift Clock Frequency

(Notes 9, 10)

12.5

MHz

fEXTCLKIN

External Conversion Clock Frequency

(Notes 9, 10)

0.03

4.5

MHz

tdEXTCLKIN

Delay Time, CONVST to External Conversion Clock Input

(Notes 9, 10)

533

tH SCLK

SCLK High Time

(Notes 9, 10)

10

tL SCLK

SCLK Low Time

(Notes 9, 10)

20

tH EXTCLKIN

EXTCLKIN High Time

(Notes 9, 10)

250

ns

tL EXTCLKIN

EXTCLKIN Low Time

(Notes 9, 10)

250

ns

The denotes specifications which apply over the full operating


temperature range; all other limits and typicals TA = 25C.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and
AGND wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VCC without latchup.
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = 0V or 5V, fSAMPLE = 200kHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a singleended input with AIN grounded.

t10

ns

40

ns
35

15

70

ns

25

ns

ns
ns

Note 7: Integral nonlinearity is defined as the deviation of a code from a


straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from 0.5LSB
when the output code flickers between 0000 0000 0000 00 and
1111 1111 1111 11.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling edge of CONVST starts a conversion. If CONVST
returns high at a critical point during the conversion, it can create small
errors. For best performance ensure that CONVST returns high either
within 2.1s after the conversion starts or after BUSY rises.
Note 12: Pins 16 (D4/EXTCLKIN), 17 (D3/SCLK) and 20 (DO/EXT/INT) at
0V or 5V. See Power Shutdown.

LTC1418
U W

TYPICAL PERFORMANCE CHARACTERISTICS


Differential Nonlinearity
vs Output Code

Typical INL Curve

90

1.0

0.5
DNL ERROR (LSBs)

0.5

0.5

0.5

4096

8192

12288

4096

OUTPUT CODE

12288
8192
OUTPUT CODE

Signal-to-Noise Ratio
vs Input Frequency
AMPLITUDE (dB BELOW THE FUNDAMENTAL)

SIGNAL-TO -NOISE RATIO (dB)

40
30

70
60
50
40
30
20
10
0
1k

10k
100k
INPUT FREQUENCY (Hz)

1M

10

16384

1k

40
60
3RD

80

THD
2ND

100
120

1k

10k
100k
INPUT FREQUENCY (Hz)

1M

20
40
60
80
100
120
10k

Intermodulation Distortion Plot


0

0
fSAMPLE = 200kHz
fIN = 9.9609375kHz
SFDR = 99.32
SINAD = 82.4

fSAMPLE = 200kHz
fIN = 97.509765kHz
SFDR = 94.29
SINAD = 81.4

40
60
80

120
0

10 20

30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02a

40
60
80

100

100

100

fSAMPLE = 200kHz
fIN1 = 97.65625kHz
fIN2 = 104.248046kHz

20
AMPLITUDE (dB)

20
AMPLITUDE (dB)

80

1M
1418 G04

Nonaveraged, 4096 Point FFT,


Input Frequency = 100kHz

60

100k
INPUT FREQUENCY (Hz)

1418 G03

1M

Spurious-Free Dynamic Range


vs Input Frequency

20

Nonaveraged, 4096 Point FFT,


Input Frequency = 10kHz

40

100k
10k
INPUT FREQUENCY (Hz)

1418 G01

1418 G02

20

VIN = 60dB

20

Distortion vs Input Frequency

80

AMPLITUDE (dB)

50

1418 G06

1418 TA02

90

VIN = 20dB

60

16384

SPURIOUS-FREE DYNAMIC RANGE (dB)

VIN = 0dB

70

1.0

1.0

120

80

SIGNAL/(NOISE + DISTORTION) (dB)

1.0

INL (LSBs)

S/(N + D) vs Input Frequency


and Amplitude

120
0

10 20

30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02b

10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 G05

LTC1418
U W

TYPICAL PERFORMANCE CHARACTERISTICS


Power Supply Feedthrough
vs Ripple Frequency

COMMON MODE REJECTION (dB)

DISTORTION (dB)

20
40
VSS
VDD

80

DGND

100

90

10

80

CHANGE IN OFFSET VOLTAGE (LSB)

60

Input Offset Voltage Shift


vs Source Resistance

Input Common Mode Rejection


vs Input Frequency

70
60
50
40
30
20
10

120
1k

10k

100k
1M
FREQUENCY (Hz)

7
6
5
4
3
2
1
0

10M

10

100
1k
10k 100k
INPUT FREQUENCY (Hz)

1418 G08

1M

10

100
100k
1k
10k
INPUT SOURCE RESISTANCE ()

1M
1418 G10

1418 G09

VDD Supply Current vs


Temperature (Bipolar Mode)

VDD Supply Current vs


Temperature (Unipolar Mode)
5

VSS Supply Current vs


Temperature (Bipolar Mode)
2.0

VSS SUPPLY CURRENT (mA)

VDD SUPPLY CURRENT (mA)

VDD SUPPLY CURRENT (mA)

1.8

1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2

0
75 50 25

0 25 50 75 100 125 150


TEMPERATURE (C)

75 50 25

0
75 50 25

0 25 50 75 100 125 150


TEMPERATURE (C)
1418 G12

1418 G11

1418 G13

VDD Supply Current vs Sampling


Frequency (Bipolar Mode)

VDD Supply Current vs Sampling


Frequency (Unipolar Mode)
5

0 25 50 75 100 125 150


TEMPERATURE (C)

VSS Supply Current vs Sampling


Frequency (Bipolar Mode)
2.0

VSS SUPPLY CURRENT (mA)

VDD SUPPLY CURRENT (mA)

VDD SUPPLY CURRENT (mA)

1.8

1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2

0
0

100
150
200
250
50
SAMPLING FREQUENCY (kHz)

300

1418 G14

0
0

50
150
200
250
100
SAMPLING FREQUENCY (kHz)

300

1418 G15

50
150
200
250
100
SAMPLING FREQUENCY (kHz)

300

1418 G16

LTC1418
U

PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input.
AIN (Pin 2): Negative Analog Input.
VREF (Pin 3): 2.50V Reference Output. Bypass to AGND
with 1F.
REFCOMP (Pin 4): 4.096V Reference Bypass Pin.
Bypass to AGND with 10F tantalum in parallel with 0.1F
ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs
(Parallel). D13 is the most significant bit.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 (Pin 15): Three-State Data Output (Parallel).
D4 (EXTCLKIN) (Pin 16): Three-State Data Output
(Parallel). Conversion clock input (serial) when Pin 20
(EXT/INT) is tied high.
D3 (SCLK) (Pin 17): Three-State Data Output (Parallel).
Data clock input (serial).
D2 (CLKOUT) (Pin 18): Three-State Data Output (Parallel).
Conversion clock output (serial).
D1 (DOUT) (Pin 19): Three-State Data Output (Parallel).
Serial data output (serial).
D0 (EXT/INT) (Pin 20): Three-State Data Output (Parallel).
Conversion clock selector (serial). An input low enables

the internal conversion clock. An input high indicates an


external conversion clock will be assigned to Pin 16
(EXTCLKIN).
SER/PAR (Pin 21): Data Output Mode.
SHDN (Pin 22): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for nap
mode and CS = 1 for sleep mode.
RD (Pin 23): Read Input. This enables the output drivers
when CS is low.
CONVST (Pin 24): Conversion Start Signal. This active low
signal starts a conversion on its falling edge.
CS (Pin 25): Chip Select. This input must be low for the
ADC to recognize the CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and SHDN
low select the quick wake-up nap mode. CS high and
SHDN low select sleep mode.
BUSY (Pin 26): The BUSY Output Shows the Converter
Status. It is low when a conversion is in progress.
VSS (Pin 27): Negative Supply, 5V for Bipolar Operation.
Bypass to AGND with 10F tantalum in parallel with 0.1F
ceramic. Analog ground for unipolar operation.
VDD (Pin 28): 5V Positive Supply. Bypass to AGND with
10F tantalum in parallel with 0.1F ceramic.

TEST CIRCUITS
Load Circuits for Access Timing

Load Circuits for Output Float Delay


5V

5V
1k

DBN

1k

DBN
1k

CL
DGND

A) HI-Z TO VOH AND VOL TO VOH

DBN
CL

DBN
1k

30pF

30pF

DGND
B) HI-Z TO VOL AND VOH TO VOL
1418 TC01

A) VOH TO HI-Z

B) VOL TO HI-Z
1418 TC02

LTC1418

W
FUNCTIONAL BLOCK DIAGRA
U

CSAMPLE
AIN+
VDD: 5V

CSAMPLE

VSS: 0V FOR UNIPOLAR MODE


5V FOR BIPOLAR MODE

AIN
VREF

2.5V

8k

ZEROING SWITCHES

2.5V REF

+
REF AMP

COMP

14-BIT CAPACITIVE DAC

REFCOMP

4.096V

AGND
DGND

14

SUCCESSIVE APPROXIMATION
REGISTER

SHIFT
REGISTER

D13

D0
D3/(SCLK)

INTERNAL
CLOCK

CONTROL LOGIC

MUX

D1/(DOUT)
1418 BD

D4 (EXTCLKIN)

D0 (EXT/INT) SHDN CONVST RD CS SER/PAR D2/(CLKOUT) BUSY

NOTE: PIN NAMES IN PARENTHESES


REFER TO SERIAL MODE

APPLICATIONS INFORMATION
CONVERSION DETAILS
The LTC1418 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit parallel or serial output. The ADC
is complete with a precision reference and an internal
clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface
section for the data format).
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).

AIN+

CSAMPLE+

SAMPLE

ZEROING SWITCHES

HOLD

CSAMPLE

SAMPLE

AIN

HOLD

HOLD

HOLD
CDAC+

+
CDAC

VDAC+

COMP

VDAC

14
SAR

OUTPUT
LATCH

D13
D0
1418 F01

Figure 1. Simplified Block Diagram

LTC1418

APPLICATIONS INFORMATION

DYNAMIC PERFORMANCE
The LTC1418 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used
to test the ADCs frequency response, distortion and noise
at the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using an FFT algorithm, the ADCs spectral content can be examined for
frequencies outside the fundamental. Figure 2 shows a
typical LTC1418 FFT plot.

0
fSAMPLE = 200kHz
fIN = 9.9609375kHz
SFDR = 99.32
SINAD = 82.4

AMPLITUDE (dB)

20
40
60
80

100
120

10 20

30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02a

Figure 2a. LTC1418 Nonaveraged, 4096 Point FFT,


Input Frequency = 10kHz
0
fSAMPLE = 200kHz
fIN = 97.509765kHz
SFDR = 94.29
SINAD = 81.4

20
AMPLITUDE (dB)

Referring to Figure 1, the AIN+ and AIN inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 1s will provide enough time for the sample-andhold capacitors to acquire the analog signal. During the
convert phase the comparator zeroing switches open,
putting the comparator into compare mode. The input
switches the CSAMPLE capacitors to ground, transferring
the differential analog input charge onto the summing
junction. This input charge is successively compared with
the binary weighted charges supplied by the differential
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the differential
DAC output balances the AIN+ and AIN input charges. The
SAR contents (a 14-bit data word) which represent the
difference of AIN+ and AIN are loaded into the 14-bit
output latches.

40
60
80

100
120

10 20

30 40 50 60 70 80 90 100
FREQUENCY (kHz)
1418 F02b

Figure 2b. LTC1418 Nonaveraged, 4096 Point FFT,


Input Frequency = 97.5kHz

Signal-to-Noise Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 2a shows a typical spectral content with
a 200kHz sampling rate and a 10kHz input. The dynamic
performance is excellent for input frequencies up to and
beyond the Nyquist limit of 100kHz.

Effective Number of Bits


The effective number of bits (ENOBs) is a measurement of
the resolution of an ADC and is directly related to the
S/(N + D) by the equation:
N = [S/(N + D) 1.76]/6.02
where N is the effective number of bits of resolution and
S/(N + D) is expressed in dB. At the maximum sampling
rate of 200kHz the LTC1418 maintains near ideal ENOBs
up to the Nyquist input frequency of 100kHz (refer to
Figure 3).

LTC1418
U

APPLICATIONS INFORMATION
14

shown in Figure 4. The LTC1418 has good distortion


performance up to the Nyquist frequency and beyond.

13
12

EFECTIVE BITS

11

Intermodulation Distortion

10
9

If the ADC input signal consists of more than one spectral


component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.

8
7
6
5
4
3
2

10k
100k
INPUT FREQUENCY (Hz)

1k

1M
1418 F03

Figure 3. Effective Bits and Signal/(Noise + Distortion)


vs Input Frequency

Total Harmonic Distortion


Total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD is
expressed as:

V22 + V32 + V42 + ...Vn2


V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD vs Input Frequency is

If two pure sine waves of frequencies fa and fb are applied


to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3,
etc. For example, the 2nd order IMD terms include
(fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products
can be expressed by the following formula:

IMD fa + fb = 20Log

AMPLITUDE (dB BELOW THE FUNDAMENTAL)

THD = 20Log

40
60
80

100

40

120
0

10 20 30 40 50 60 70 80 90 100
FREQUENCY (kHz)

60

1418 G05

3RD

80

Figure 5. Intermodulation Distortion Plot

THD
2ND

100

1k

10k
100k
INPUT FREQUENCY (Hz)

1M
1418 G03

Figure 4. Distortion vs Input Frequency

10

Amplitude at fa

fSAMPLE = 200kHz
fIN1 = 97.65625kHz
fIN2 = 104.248046kHz

20

20

120

AMPLITUDE (dB)

Amplitude at fa + fb

Peak Harmonic or Spurious Noise


The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This
value is expressed in decibels relative to the RMS value of
a full-scale input signal.

LTC1418
U

APPLICATIONS INFORMATION
The full-power bandwidth is that input frequency at which
the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input signal.
The full-linear bandwidth is the input frequency at which
the S/(N + D) has dropped to 77dB (12.5 effective bits).
The LTC1418 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with
frequencies above the converters Nyquist Frequency. The
noise floor stays very low at high frequencies; S/(N + D)
becomes dominated by distortion at frequencies far
beyond Nyquist.
DRIVING THE ANALOG INPUT
The differential analog inputs of the LTC1418 are easy to
drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN input is grounded). The AIN+ and
A IN inputs are sampled at the same instant. Any
unwanted signal that is common mode to both inputs will
be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low then the LTC1418
inputs can be driven directly. As source impedance
increases so will acquisition time (see Figure 6). For
minimum acquisition time, with high source impedance, a
buffer amplifier must be used. The only requirement is that
the amplifier driving the analog input(s) must settle after
the small current spike before the next conversion starts
1s for full throughput rate.
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, choose an amplifier that
has a low output impedance (<100) at the closed-loop
bandwidth frequency. For example, if an amplifier is used
in a gain of 1 and has a closed-loop bandwidth of 10MHz,
then the output impedance at 10MHz must be less than
100. The second requirement is that the closed-loop
bandwidth must be greater than 5MHz to ensure adequate

small-signal settling for full throughput rate. If slower op


amps are used, more settling time can be provided by
increasing the time between conversions.
The best choice for an op amp to drive the LTC1418 will
depend on the application. Generally, applications fall into
two categories: AC applications where dynamic specifications are most critical and time domain applications where
DC accuracy and settling time are most critical. The
following list is a summary of the op amps that are suitable
for driving the LTC1418. More detailed information is
available in the Linear Technology Databooks and on the
LinearViewTM CD-ROM.
LT 1354: 12MHz, 400V/s Op Amp. 1.25mA maximum
supply current. Good AC and DC specifications. Suitable
for dual supply application.
LT1357: 25MHz, 600V/s Op Amp. 2.5mA maximum
supply current. Good AC and DC specifications. Suitable
for dual supply application.
LT1366/LT1367: Dual/Quad Precision Rail-to-Rail Input
and Output Op Amps. 375A supply current per amplifier.
1.8V to 15V supplies. Low input offset voltage: 150V.
Good for low power and single supply applications with
sampling rates of 20ksps and under.
LT1498/LT1499: 10MHz, 6V/s, Dual/Quad Rail-to-Rail
Input and Output Op Amps. 1.7mA supply current per
100

ACQUISITION TIME (s)

Full-Power and Full-Linear Bandwidth

10

0.1
1

10
100
1k
10k
SOURCE RESISTANCE ()

100k
1418 F06

Figure 6. tACQ vs Source Resistance

LinearView is a trademark of Linear Technology Corporation.

11

LTC1418
U

APPLICATIONS INFORMATION
amplifier. 2.2V to 15V supplies. Good AC performance,
input noise voltage = 12nV/Hz (typ).
LT1630/LT1631: 30MHz, 10V/s, Dual/Quad Rail-to-Rail
Input and Output Precision Op Amps. 3.5mA supply
current per amplifier. 2.7V to 15V supplies. Best AC
performance, input noise voltage = 6nV/Hz (typ),
THD = 86dB at 100kHz.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1418 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 5MHz. Any noise or
distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications. For example, Figure 7 shows a 2000pF
capacitor from + AIN to ground and a 100 source resistor
to limit the input bandwidth to 800kHz. The 2000pF
capacitor also acts as a charge reservoir for the input
sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and
resistors should be used since these components can add
distortion. NPO and silver mica type dielectric capacitors
have excellent linearity. Carbon surface mount resistors can
also generate distortion from self heating and from damage
that may occur during soldering. Metal film surface mount
resistors are much less susceptible to both problems.
100
ANALOG INPUT
2000pF

AIN+

AIN

4
10F

The 2.048V and 0V to 4.096V input ranges of the


LTC1418 are optimized for low noise and low distortion.
Most op amps also perform well over these ranges,
allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry.
Some applications may require other input ranges. The
LTC1418 differential inputs and reference circuitry can
accommodate other input ranges often with little or no
additional circuitry. The following sections describe the
reference and input circuitry and how they affect the input
range.
INTERNAL REFERENCE
The LTC1418 has an on-chip, temperature compensated,
curvature corrected, bandgap reference which is factory
trimmed to 2.500V. It is internally connected to a reference
amplifier and is available at Pin 3. A 8k resistor is in series
with the output so that it can be easily overdriven in
applications where an external reference is required, see
Figure 8. The reference amplifier compensation pin
(REFCOMP, Pin 4) must be connected to a capacitor to
ground. The reference is stable with capacitors of 1F or
greater. For the best noise performance, a 10F in parallel
with a 0.1F ceramic is recommended.
The VREF pin can be driven with a DAC or other means
to provide input span adjustment. The reference should
be kept in the range of 2.25V to 2.75V for specified
linearity.
5V

Input Range

VREF

5V

ANALOG
INPUT

LTC1418

VIN
LT1460

AIN

AGND
1418 F07

AIN+

VOUT

REFCOMP

10F

0.1F
5

VREF

VDD

LTC1418

REFCOMP
AGND
1418 F08

Figure 7. RC Input Filter


Figure 8. Using the LT1460 as an External Reference

12

LTC1418
U

APPLICATIONS INFORMATION
UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT
Figure 9a shows the ideal input/output characteristics for
the LTC1418. The code transitions occur midway between
successive integer LSB values (i.e., 0.5LSB, 1.5LSB,
2.5LSB, FS 1.5LSB). The output code is natural binary
with 1LSB = FS/16384 = 4.096V/16384 = 250V. Figure 9b
shows the input/output transfer characteristics for the
bipolar mode in twos complement format.
Unipolar Offset and Full-Scale Error Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figures
10a and 10b show the extra components required for full-

1LSB =

111...111

scale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN input. For zero offset
error apply 125V (i.e., 0.5LSB) at the input and adjust
the offset at the AIN input until the output code flickers
between 0000 0000 0000 00 and 0000 0000 0000 01. For
full-scale adjustment, an input voltage of 4.095625V
(FS 1.5LSBs) is applied to AIN+ and R2 is adjusted until
the output code flickers between 1111 1111 1111 10 and
1111 1111 1111 11.
Bipolar Offset and Full-Scale Error Adjustment
Bipolar offset and full-scale errors are adjusted in a similar
fashion to the unipolar case. Again, bipolar offset error
must be adjusted before full-scale error. Bipolar offset

FS = 4.096V
16384 16384

111...110

5V

ANALOG INPUT

111...101
OUTPUT CODE

R7
48k

R8
100
R1
50k

111...100

R3
24k

AIN+

AIN

R5 R2
47k 50k

UNIPOLAR
ZERO

000...011

R4
100

R6
24k

000...010

5
0.1F

10F

000...001

VDD

VREF

LTC1418

REFCOMP
AGND V
SS
1418 F10a

000...000
0V

1
LSB

FS 1LSB
INPUT VOLTAGE (V)
1418 F9a

Figure 9a. LTC1418 Unipolar Transfer Characteristics

5V

011...111

5V
ANALOG INPUT

BIPOLAR
ZERO

011...110

OUTPUT CODE

Figure 10a. Offset and Full-Scale Adjust Circuit


If 5V Is Not Available

R1
50k

R3
24k

000...001
000...000

R4
100

R6
24k

111...110

AIN+

AIN

R5 R2
47k 50k

111...111

4
5

100...001

FS = 4.096V
1LSB = FS/16384

100...000
FS/2

1 0V 1
LSB
LSB
INPUT VOLTAGE (V)

FS/2 1LSB
1418 F9b

Figure 9b. LTC1418 Bipolar Transfer Characteristics

10F

0.1F

VDD

LTC1418

VREF

REFCOMP
AGND V
SS
*

*ONLY NEEDED IF VSS GOES


ABOVE GROUND

1418 F10b

1N5817 5V

Figure 10b. Offset and Full-Scale Adjust Circuit


If 5V Is Available

13

LTC1418

APPLICATIONS INFORMATION
error adjustment is achieved by adjusting the offset
applied to the AIN input. For zero offset error apply
125V (i.e., 0.5LSB) at AIN+ and adjust the offset
at the AIN input until the output code flickers between
0000 0000 0000 00 and 1111 1111 1111 11. For
full-scale adjustment, an input voltage of 2.047625V
(FS 1.5LSBs) is applied to AIN+ and R2 is adjusted until
the output code flickers between 0111 1111 1111 10 and
0111 1111 1111 11.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best
performance from the LTC1418, a printed circuit board
with ground plane is required. The ground plane under the
ADC area should be as free of breaks and holes as
possible, such that a low impedance path between all ADC
grounds and all ADC decoupling capacitors is provided. It
is critical to prevent digital noise from being coupled to the
analog input, reference or analog power supply lines.
Layout should ensure that digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND) and Pin 14 (DGND) and all other analog
grounds should be connected to this single analog ground
plane. The REFCOMP bypass capacitor and the VDD bypass capacitor should also be connected to this analog
ground plane. No other digital grounds should be con-

AIN+
AIN

ANALOG
INPUT
CIRCUITRY

nected to this analog ground plane. Low impedance analog and digital power supply common returns are essential
to low noise operation of the ADC and the foil width for
these tracks should be as wide as possible. In applications
where the ADC data outputs and control signals are
connected to a continuously active microprocessor bus, it
is possible to get errors in the conversion results. These
errors are due to feedthrough from the microprocessor to
the successive approximation comparator. The problem
can be eliminated by forcing the microprocessor into a
wait state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the
pins and bypass capacitors must be kept short and should
be made as wide as possible.
The LTC1418 has differential inputs to minimize noise
coupling. Common mode noise on the AIN+ and AIN leads
will be rejected by the input CMRR. The AIN input can be
used as a ground sense for the AIN+ input; the LTC1418 will
hold and convert the difference voltage between AIN+ and
AIN. The leads to AIN+ (Pin 1) and AIN (Pin 2) should be
kept as short as possible. In applications where this is not
possible, the AIN+ and AIN traces should be run side by
side to equalize coupling.
SUPPLY BYPASSING
High quality, low series resistance ceramic, 10F bypass
capacitors should be used at the VDD and REFCOMP pins.
Surface mount ceramic capacitors such as Murata
GRM235Y5V106Z016 provide excellent bypassing in a
small board space. Alternatively 10F tantalum capacitors
in parallel with 0.1F ceramic capacitors can be used.

DIGITAL
SYSTEM

LTC1418
VREF

REFCOMP

4
1F

AGND
5

10F

VDD

VSS
27
10F

DGND

28

14

10F

ANALOG GROUND PLANE


1418 F11

Figure 11. Power Supply Grounding Practice

14

J7

J5

JP5A

JP5B

SER/PAR

CS

SHDN

HC14

U7A

HC14

U7B

C13
10F
16V

C11
1000pF

R15
51

D15
SS12

R16
51

C8
1F
16V

JP2

JP4

DGND

JP5C

VOUT

GND TABGND
2
4

VIN

R19
51

R18
10k

R17
10k

LT1121-5

R22
1M

VCC

C4
0.1F

C12
0.1F

R14
20
0.125W

HC14

U7C

VCC

C14
0.1F

EN2

EN1

20

VSS

13

U8F

U8B
7

SINGLE

16

20 B00

19 B01

18 B02

17 B03

16 B04

15 B05

13 B06

12 B07

B04

B03

B02

B01

B00

EXTCLKIN

SCLK

CLKOUT

DOUT

14

U8C

12

74HC244

U8H

74HC244
17

18

R23
100k

B06

B07

B08

B09

U8G

DGND

U8D

74HC244

15

74HC244

U8A

74HC244

13

B11

10 B09
B10

B12

B10

9
11 B08

11

B11

VSS

Q6

D6

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

J8-6

J8-2

J8-1

J8-3

J8-4

J8-5

HEADER
6-PIN

HC14

12

GND

U7G
HC14

14
VCC

VLOGIC

D7

D6

D5

D4

D3

D2

D1

D0

0E

U6
74HC574

Q7

Q5

D5
D7

Q4

Q3

Q2

Q1

Q0

D4

D3

D2

D1

D0

0E

D06

D07

D08

D09

D10

D11

D12

D13

D05

D04

D03

D02

D01

D00

C6
15pF

R21
1k

12

13

14

15

16

17

18

19

12

13

14

15

16

17

18

19

C1
22F
10V

U5
74HC574

U7F

B13

B04
B05

B03

B02

B01
4

11

D14
SS12

B00

B12

EXT/INT

VOUT

TAB GND

VIN

U1
LT1175-5

SUPPLY SELECT

DUAL

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

B[00:13]

B13

VIN

J1
7V TO
15V

C15
0.1F

DATA READY

74HC244

U8E

74HC244

1
9

DGND

AGND

VSS

BUSY

VDD

SER/PAR

SHDN

RD

CONVST

CS

74HC244

C5
10F
16V

U4
LTC1418

REFCOMP

VREF

AIN

+AIN

JP6

14

27

26

28

21

22

23

24

25

C10
10F
10V

C7
0.1F

VLOGIC

Figure 12a. Suggested Evaluation Circuit Schematic

19

R20
19k

VLOGIC VLOGIC

C9
10F
16V

C3
VSS
0.1F

U3
LT1363
2 7

6
3 +
8
1
4
V

V+

VOUT

JP7

C2
22F
10V

JP3

VCC

NOTES: UNLESS OTHERWISE SPECIFIED


1. ALL RESISTOR VALUES IN OHMS, 1/10W, 5%
2. ALL CAPACITOR VALUES IN F, 25V, 20% AND IN pF, 50V, 10%

VLOGIC

CLK

A+

AGND

J2

J4

GND

+VIN

U2

11

HC14

U7D

HC14

U7E

D[00:13]

10

D13

RDY

D13

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

D13

D12

D11

J6-12

J6-11

J6-14

DGND
HEADER
18-PIN

DGND
J6-18

RDY

D13

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

J6-17

J6-16

J6-15

J6-2

J6-1

J6-4

J6-3

J6-6

J6-5

J6-8

J6-7

J6-10

J6-9

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D10

J6-13

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

R0, 1k

1418 F12a

JP1

LED

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

U
U
W

J3
7V TO
15V

APPLICATIONS INFORMATION
U

VCC

LTC1418

15

LTC1418
U

APPLICATIONS INFORMATION

1418 F12b

Figure 12b. Suggested Evaluation Circuit Board Component Side Top Silkscreen

1418 F12c

Figure 12c. Suggested Evaluation Circuit BoardTop Layer

16

LTC1418

APPLICATIONS INFORMATION

1418 F12d

Figure 12d. Suggested Evaluation Circuit BoardSolder Side Layout

Bypass capacitors must be located as close to the pins as


possible. The traces connecting the pins and the bypass
capacitors must be kept short and should be made as wide
as possible.
Example Layout
Figures 12a, 12b, 12c and 12d show the schematic and
layout of a suggested evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground
plane with a 2-layer printed circuit board.
DIGITAL INTERFACE
The LTC1418 can operate in serial or parallel mode. In
parallel mode the ADC is designed to interface with microprocessors as a memory mapped device. The CS and RD
control inputs are common to all peripheral memory
interfacing. In serial mode only four digital interface lines
are required, SCLK, CONVST, EXTCLKIN and DOUT. SCLK,
the serial data shift clock can be an external input or
supplied by the LTC1418 internal clock.

Internal Clock
The ADC has an internal clock. In parallel output mode the
internal clock is always used as the conversion clock. In
serial output mode either the internal clock or an external
clock may be used as the conversion clock (see Figure 20).
The internal clock is factory trimmed to achieve a typical
conversion time of 3.4s and a maximum conversion time
over the full operating temperature range of 4s. No external adjustments are required, and with the guaranteed maximum acquisition time of 1s, throughput performance of
200ksps is assured.
Power Shutdown
The LTC1418 provides two power shutdown modes, nap
and sleep, to save power during inactive periods. The nap
mode reduces the power by 80% and leaves only the
digital logic and reference powered up. The wake-up time
from nap to active is 500ns (see Figure 13a). In sleep
mode all bias currents are shut down and only leakage
current remains about 2A. Wake-up time from sleep

17

LTC1418
U

APPLICATIONS INFORMATION
mode is much slower since the reference circuit must
power up and settle to 0.005% for full 14-bit accuracy.
Sleep mode wake-up time is dependent on the value of
the capacitor connected to the REFCOMP (Pin 4). The
wake-up time is 30ms with the recommended 10F
capacitor. Shutdown is controlled by Pin 22 (SHDN); the
ADC is in shutdown when it is low. The shutdown mode
is selected with Pin 25 (CS); low selects nap (see Figure
13b), high selects sleep.
SHDN
t4
CONVST
1418 F13a

Figure 13a. SHDN to CONVST Wake-Up Timing

CS
t2
CONVST
t1
RD
1418 F14

Figure 14. CS to CONVST Set-Up Timing

or serial data formats, outputs will be active only when CS


and RD are low. Any other combination of CS and RD will
three-state the output. In unipolar mode (VSS = 0V) the
data will be in straight binary format (corresponding to the
unipolar input range). In bipolar mode (VSS = 5V), the
data will be in twos complement format (corresponding to
the bipolar input range).
Parallel Output Mode

CS
t3
SHDN
1418 F13b

Figure 13b. CS to SHDN Timing

Conversion Control
Conversion start is controlled by the CS and CONVST
inputs. A falling edge of CONVST pin will start a conversion
after the ADC has been selected (i.e., CS is low, see Figure
14). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the
BUSY output. BUSY is low during a conversion.
Data Output
The data format is controlled by the SER/PAR input pin;
logic low selects parallel output format. In parallel mode
the 14-bit data output word D0 to D13 is updated at the end
of each conversion on Pins 6 to 13 and Pins 15 to 20. A
logic high applied to SER/PAR selects the serial formatted
data output and Pins 16 to 20 assume their serial function,
Pins 6 to 13 and 15 are in the Hi-Z state. In either parallel

18

Parallel mode is selected with a logic 0 applied to the


SER/PAR pin. Figures 15 through 19 show different modes
of parallel output operation. In modes 1a and 1b (Figures
15 and 16) CS and RD are both tied low. The falling edge
of CONVST starts the conversion. The data outputs are
always enabled and data can be latched with the BUSY
rising edge. Mode 1a shows operation with a narrow logic
low CONVST pulse. Mode 1b shows a narrow logic high
CONVST pulse.
In mode 2 (Figure 17) CS is tied low. The falling edge of
CONVST signal again starts the conversion. Data outputs
are in three-state until read by the MPU with the RD signal.
Mode 2 can be used for operation with a shared databus.
In slow memory and ROM modes (Figures 18 and 19), CS
is tied low and CONVST and RD are tied together. The MPU
starts the conversion and reads the output with the RD
signal. Conversions are started by the MPU or DSP (no
external sample clock).
In slow memory mode the processor takes RD (= CONVST)
low and starts the conversion. BUSY goes low forcing the
processor into a wait state. The previous conversion result
appears on the data outputs. When the conversion is
complete, the new conversion results appear on the data

LTC1418
U

APPLICATIONS INFORMATION
CS = RD = 0

tCONV
(SAMPLE N)
t5

CONVST
t6

t8

BUSY
t7
DATA

DATA (N 1)
DB13 TO DB0

DATA N
DB13 TO DB0

DATA (N + 1)
DB13 TO DB0
1418 F15

Figure 15. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled
(CONVST =

CS = RD = 0

t13

tCONV
t5

CONVST
t8

t6

t6

BUSY
t7
DATA

DATA (N 1)
DB13 TO DB0

DATA N
DB13 TO DB0

DATA (N + 1)
DB13 TO DB0
1418 F16

Figure 16. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled

(CONVST =

CS = 0

t12

(SAMPLE N)
tCONV
t5

t8

CONVST
t6
BUSY
t9

t12

t11

RD
t 10
DATA

DATA N
DB13 TO DB0
1418 F17

Figure 17. Mode 2. CONVST Starts a Conversion. Data is Read by RD

19

LTC1418

APPLICATIONS INFORMATION
CS = 0
(SAMPLE N)

t8

tCONV

RD = CONVST
t6

t11

BUSY
t10

t7
DATA (N 1)
DB13 TO DB0

DATA

DATA N
DB13 TO DB0

DATA N
DB13 TO DB0

DATA (N + 1)
DB13 TO DB0
1418 F18

Figure 18. Slow Memory Mode Timing


CS = 0

tCONV

t8

(SAMPLE N)
RD = CONVST
t6

t11

BUSY
t10
DATA

DATA N
DB13 TO DB0

DATA (N 1)
DB13 TO DB0

1418 F19

Figure 19. ROM Mode Timing

outputs; BUSY goes high releasing the processor and the


processor takes RD (= CONVST) back high and reads the
new conversion data.

either before the next conversion starts or it can be clocked


out during the next conversion. To enable the serial data
output buffer and shift clock, CS and RD must be low.

In ROM mode, the processor takes RD (= CONVST) low,


starting a conversion and reading the previous conversion
result. After the conversion is complete, the processor can
read the new result and initiate another conversion.

Figure 20 shows a function block diagram of the LTC1418


in serial mode. There are two pieces to this circuitry: the
conversion clock selection circuit (EXT/INT, EXTCLKIN
and CLKOUT) and the serial port (SCLK, DOUT, CS and RD).

Serial Output Mode

Conversion Clock Selection (Serial Mode)

Serial output mode is selected when the SER/PAR input


pin is high. In this mode, Pins 16 to 20, D0 (EXT/INT), D1
(DOUT), D2 (CLKOUT), D3 (SCLK) and D4 (EXTCLKIN)
assume their serial functions as shown in Figure 20.
(During this discussion these pins will be referred to by
their serial function names: EXT/INT, DOUT, CLKOUT,
SCLK and EXTCLKIN.) As in parallel mode, conversions
are started by a falling CONVST edge with CS low. After a
conversion is completed and the output shift register has
been updated, BUSY will go high and valid data will be
available on DOUT (Pin 19). This data can be clocked out

In Figure 20, the conversion clock controls the internal


ADC operation. The conversion clock can be either internal or external. By connecting EXT/INT low, the internal
clock is selected. This clock generates 16 clock cycles
which feed into the SAR for each conversion.

20

To select an external conversion clock, tie EXT/INT high


and apply an external conversion clock to EXTCLKIN (Pin
16). (When an external shift clock (SCLK) is used during
a conversion, the SCLK should be used as the external
conversion clock to avoid the noise generated by the

LTC1418
U

APPLICATIONS INFORMATION

DATA
IN
14

CLOCK
INPUT
SHIFT
REGISTER

23

DATA
OUT

25
THREE
STATE
BUFFER

SAR

17

19

SCLK*
RD
CS

DOUT*

16 CONVERSION CLOCK CYCLES


THREE
STATE
BUFFER

18

EOC

16
20

CLKOUT*

EXTCLKIN*
EXT/INT*

INTERNAL
CLOCK
26
*PINS 16 TO 20 ARE LABELED WITH THEIR SERIAL FUNCTIONS

BUSY
1418 F20

Figure 20. Functional Block Diagram for Serial Mode (SER/PAR = High)

asynchronous clocks. To maintain accuracy the external


conversion clock frequency must be between 30kHz and
4.5MHz.) The SAR sends an end of conversion signal,
EOC, that gates the external conversion clock so that only
16 clock cycles can go into the SAR, even if the external
clock, EXTCLKIN, contains more than 16 cycles.
When CS and RD are low, these 16 cycles of conversion
clock (whether internally or externally generated) will
appear on CLKOUT during each conversion and then
CLKOUT will remain low until the next conversion. If
desired, CLKOUT can be used as a master clock to drive
the serial port. Because CLKOUT is running during the
conversion, it is important to avoid excessive loading that
can cause large supply transients and create noise. For
the best performance, limit CLKOUT loading to 20pF.
Serial Port
The serial port in Figure 20 is made up of a 16-bit shift
register and a three-state output buffer that are controlled by three inputs: SCLK, RD and CS. The serial port
has one output, DOUT, that provides the serial output
data.

The SCLK is used to clock the shift register. Data may be


clocked out with the internal conversion clock operating
as a master by connecting CLKOUT (Pin 18) to SCLK (Pin
17) or with an external data clock applied to D3 (SCLK).
The minimum number of SCLK cycles required to
transfer a data word is 14. Normally, SCLK contains 16
clock cycles for a word length of 16 bits; 14 bits with MSB
first, followed by two trailing zeros.
A logic high on RD disables SCLK and three-states DOUT.
In case of using a continuous SCLK, RD can be controlled
to limit the number of shift clocks to the desired number
(i.e., 16 cycles) and to three-state DOUT after the data
transfer.
A logic high on CS three-states the DOUT output buffer. It
also inhibits conversion when it is tied high. In power
shutdown mode (SHDN = low), a high CS selects sleep
mode while a low CS selects nap mode. For normal serial
port operation, CS can be grounded.
DOUT outputs the serial data; 14 bits, MSB first, on the
falling edge of each SCLK (see Figures 21 and 22). If 16
SCLKs are provided, the 14 data bits will be followed by

21

LTC1418
U

APPLICATIONS INFORMATION
two zeros. The MSB (D13) will be valid on the first rising
and the first falling edge of the SCLK. D12 will be valid on
the second rising and the second falling edge as will all
the remaining bits. The data may be captured on either
edge. The largest hold time margin is achieved if data is
captured on the rising edge of SCLK.

SCLK

VIL
t14
t15
VOH

DOUT

VOL
1418 F21

BUSY gives the end of conversion indication. When the


LTC1418 is configured as a master serial device, BUSY
can be used as a framing pulse and to three-state the

CONVST

24

CONVST

BUSY
RD
SCLK

Figure 21. SCLK to DOUT Delay

BUSY (= RD)

26
23

LTC1418
CLKOUT
DOUT
EXT/INT

P OR DSP
(CONFIGURED
AS SLAVE)
OR
SHIFT
REGISTER

17

18

CLKOUT ( = SCLK)

19

DOUT

20
1418 F22a

CS
25

(SAMPLE N)
t5

CS = EXT/INT = 0

(SAMPLE N + 1)

CONVST
t13
t6

t8
HOLD

BUSY (= RD)

SAMPLE

HOLD

t10
1

D13

D12

D11

D10

D9

D8

D7

D6

D5

10

11

12

13

14

15

16

D13

D12

D11

CLKOUT (= SCLK)
t7
DOUT

Hi-Z

D4

D3

D2

D1

D0

FILL
ZEROS

D13

Hi-Z

DATA (N 1)
tCONV

DATA N
t11

CLKOUT
(= SCLK)

VIL
t14
t15

DOUT

D13

D12
CAPTURE ON
RISING CLOCK

D11

VOH
VOL

CAPTURE ON
FALLING CLOCK

Figure 22. Internal Conversion Clock Selected. Data Transferred During Conversion Using
the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)

22

1418 F22b

LTC1418

APPLICATIONS INFORMATION
serial port after transferring the serial output data by
tying it to the RD pin.

clock and the SCLK. The internal clock has been optimized
for the fastest conversion time, consequently this mode
can provide the best overall speed performance. To select
an internal conversion clock, tie EXT/INT (Pin 20) low. The
internal clock appears on CLKOUT (Pin 18) which can be
tied to SCLK (Pin 17) to supply the SCLK.

Figures 22 to 25 show several serial modes of operation,


demonstrating the flexibility of the LTC1418 serial port.
Serial Data Output During a Conversion

Using External Clock for Conversion and Data Transfer.


In Figure 23, data from the previous conversion is output
during the conversion with an external clock providing
both the conversion clock and the shift clock. To select an
external conversion clock, tie EXT/INT high and apply the

Using Internal Conversion Clock for Conversion and


Data Transfer. Figure 22 shows data from the previous
conversion being clocked out during the conversion with
the LTC1418 internal clock providing both the conversion

CONVST

24

CONVST

BUSY
RD

EXTCLKIN

BUSY (= RD)

26
23

16 EXTCLKIN ( = SCLK)
P OR DSP

LTC1418
SCLK
DOUT
EXT/INT

17
DOUT

19
20

5V

1418 F23a

CS
25
(SAMPLE N)
t5

CS = 0, EXT/INT = 5

(SAMPLE N + 1)

CONVST
t13
t6

t8
HOLD

BUSY (= RD)

SAMPLE

HOLD

tdEXTCLKIN
1

D13

D12

D11

D10

D9

D8

D7

D6

D5

10

11

12

13

14

15

16

D13

D12

D11

EXTCLKIN (= SCLK)
t10
DOUT

Hi-Z

t7
D4

D3

D2

D1

D0

FILL
ZEROS

D13

Hi-Z

DATA (N 1)
tCONV

DATA N
t11

EXTCLKIN
(= SCLK)

1418 F23b

tLEXTCLKIN
VIL

tHEXTCLKIN
t14
t15

DOUT

D13

D12
CAPTURE ON
RISING CLOCK

D11

VOH
VOL

CAPTURE ON
FALLING CLOCK

Figure 23. External Conversion Clock Selected. Data Transferred During Conversion Using
the External Clock (External Clock Drives Both EXTCLKIN and SCLK)

23

LTC1418
U

APPLICATIONS INFORMATION
clock to EXTCLKIN. The same clock is also applied to SCLK
to provide a data shift clock. To maintain accuracy the
conversion clock frequency must be between 30kHz and
4.5MHz.
It is not recommended to clock data with an external clock
during a conversion that is running on an internal clock
because the asynchronous clocks may create noise.

CONVST

24

CONVST

BUSY
RD
SCLK

Serial Data Output After a Conversion


Using Internal Conversion Clock and External Data Clock.
In this mode, data is output after the end of each conversion but before the next conversion is started (Figure 24).
The internal clock is used as the conversion clock and an
external clock is used for the SCLK. This mode is useful in
applications where the processor acts as a master serial
device. This mode is SPI and MICROWIRE compatible. It

26

INT

23

C0

17

SCK
P OR DSP

LTC1418
DOUT
EXT/INT

19

MISO

20
1418 F24a

CS
25

t5

CS = EXT/INT = 0
CONVST

t13
t6

t8
SAMPLE

HOLD

BUSY

t9
RD
1

9 10 11 12 13 14 15 16

D13 12 11 10 9

SCLK
t10
Hi-Z

DOUT

t11
4

FILL
ZEROS

Hi-Z

(SAMPLE N)
tCONV

DATA N

1418 F24b

t LSCLK

SCLK
VIL

t HSCLK
t14
t15

DOUT

D13

D12
CAPTURE ON
RISING CLOCK

Figure 24. Internal Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY Indicates End of Conversion

24

D11
CAPTURE ON
FALLING CLOCK

VOH
VOL

LTC1418
U

APPLICATIONS INFORMATION
also allows operation when the SCLK frequency is very low
(less than 30kHz). To select the internal conversion clock
tie EXT/INT low. The external SCLK is applied to SCLK. RD
can be used to gate the external SCLK, such that data will
clock only after RD goes low and to three-state DOUT after
data transfer. If more than 16 SCLKs are provided, more
zeros will be filled in after the data word indefinitely.

CONVST

24

Using External Conversion Clock and External Data


Clock. In Figure 25, data is also output after each conversion is completed and before the next conversion is
started. An external clock is used for the conversion clock
and either another or the same external clock is used for
the SCLK. This mode is identical to Figure 24 except that
an external clock is used for the conversion. This mode

16

CONVST EXTCLKIN
BUSY

CLKOUT

26

INT

23

RD

C0
P OR DSP

LTC1418
17

SCLK
DOUT
EXT/INT

SCK

19
20

MISO
5V

1418 F25a

CS
25

CS = 0, EXT/INT = 5

tdEXTCLKIN 1

9 10 11 12 13 14 15 16

EXTCLKIN
t5

t7

CONVST
t13
t6

t8
SAMPLE

HOLD

BUSY

t9
RD
1

9 10 11 12 13 14 15 16

SCLK
t10
Hi-Z

DOUT

t11

D13 12 11 10 9

FILL
ZEROS

Hi-Z

(SAMPLE N)
tCONV

DATA N

1418 F25b

t LSCLK

SCLK
VIL

t HSCLK
t14
t15

DOUT

D12

D13

CAPTURE ON
RISING CLOCK

D11

VOH
VOL

CAPTURE ON
FALLING CLOCK

Figure 25. External Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY Indicates End of Conversion

25

LTC1418
U

APPLICATIONS INFORMATION
allows the user to synchronize the A/D conversion to an
external clock either to have precise control of the internal
bit test timing or to provide a precise conversion time. As in
Figure 24, this mode works when the SCLK frequency is
very low (less than 30kHz). However, the external conversion clock must be between 30kHz and 4.5MHz to maintain

PACKAGE DESCRIPTION

accuracy. If more than 16 SCLKs are provided, more zeros


will be filled in after the data word indefinitely. To select the
external conversion clock tie EXT/INT high. The external
SCLK is applied to SCLK. RD can be used to gate the external
SCLK such that data will clock only after RD goes low.

Dimensions in inches (millimeters) unless otherwise noted.

G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)

0.397 0.407*
(10.07 10.33)
28 27 26 25 24 23 22 21 20 19 18 17 16 15

0.301 0.311
(7.65 7.90)

1 2 3 4 5 6 7 8 9 10 11 12 13 14
0.205 0.212**
(5.20 5.38)

0.068 0.078
(1.73 1.99)

0 8

0.005 0.009
(0.13 0.22)

0.022 0.037
(0.55 0.95)

*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH


SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

26

0.0256
(0.65)
BSC

0.010 0.015
(0.25 0.38)

0.002 0.008
(0.05 0.21)

G28 SSOP 0694

LTC1418
U

PACKAGE DESCRIPTION

Dimensions in inches (millimeters) unless otherwise noted.

N Package
28-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)

1.370*
(34.789)
MAX
28

27

26

25

24

23

22

21

20

19

18

17

16

15

10

11

12

13

14

0.255 0.015*
(6.477 0.381)

0.300 0.325
(7.620 8.255)

0.130 0.005
(3.302 0.127)

0.045 0.065
(1.143 1.651)

0.020
(0.508)
MIN
0.009 0.015
(0.229 0.381)

+0.035
0.325 0.015
8.255

+0.889
0.381

0.125
(3.175)
MIN

0.065
(1.651)
TYP
0.005
(0.127)
MIN
0.100 0.010
(2.540 0.254)

0.018 0.003
(0.457 0.076)
N28 1197

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.


MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.


However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

27

LTC1418
U

TYPICAL APPLICATION
Single 5V Supply, 200kHz, 14-Bit Sampling A/D Converter

VREF
OUTPUT
2.5V
1F

LTC1418
DIFFERENTIAL 1
+
VDD
ANALOG INPUT 2 AIN
(0V TO 4.096V)
AIN
VSS
3
VREF
BUSY
4
REFCOMP
CS
5
10F
AGND
CONVST
6
D13(MSB)
RD
7
D12
SHDN
8
D11
SER/PAR
9
D10
(EXT/INT)D0
10
D9
(DOUT)D1
11
D8
(CLKOUT)D2
14-BIT
12
PARALLEL
D7
(SCLK)D3
BUS
13
D6
(EXTCLKIN )D4
14
DGND
D5

5V
28
27

10F

26
1N5817*

25
24
23

P CONTROL
LINES

22
21
20
19
18

*REQUIRED ONLY IF VSS CAN BECOME


POSITIVE WITH RESPECT TO GROUND

17
16
15

1418 TA03

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28

Linear Technology Corporation

1418f LT/TP 0798 4K PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417


(408)432-1900 FAX: (408) 434-0507 www.linear-tech.com

LINEAR TECHNOLOGY CORPORATION 1998