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Contents
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How Rules Are Organized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Manual Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typographical and Symbol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Getting Leda Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Synopsys Web Site . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 1
Power Coding Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Overview of Low/Multi Power Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Specifying Power Domains with Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . 18
Inferring Power Domains from RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Inferring Power Domains from PG-Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mixing Specifications and Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Mixing Specifications of Power Domains From Tcl and From RTL . . . . . . . . 27
Mixing Specifications of Power Domains and Inference of Power Domains from
Power Nets on a PG-Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Specifying Level Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DB cell
Tcl Command set_level_shifter
Reporting Level Shifters
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Contents
report_power_switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset_isolation_cell_recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
set_operating_conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
set_power_domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
set_power_domain_ctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
set_power_off_value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
set_power_pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
set_power_switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
set_relative_always_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
set_voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Level-Shifters Ruleset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDPAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
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78
Message: Avoid disjoint voltage domains: %s1 and voltage domain: %s2
LSINSALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Message: Missing level shifter from %f1 to %f2: %s1. From pin/signal (voltage %f1): %s2
to pin/signal (voltage %f2): %s3
LSINSL2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Message: Missing level shifter from %f1 to %f2: %s1. From pin/signal (voltage %f1): %s2
to pin/signal (voltage %f2): %s3.
LSINSH2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Message: Missing level shifter from %f1 to %f2: %s1. From pin/signal (voltage %f1): %s2
to pin/signal (voltage %f2): %s3.
LSNONEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Message: Unnecessary level shifter: %s
LSREDSER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Message: Level shifter %s is unnecessary (redundant
with %s1): %s2
LSREDPAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Message: Better split out wires after level shifters than before: %s1. The level shifter: %s2.
The level shifter: %s3
LSLOCALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Message: Level shifter must be located in the lower voltage domain (voltage %f instead of
%f / neutral region) %s
LSLOCL2H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Message: Level shifter (low to high) must be located in the higher voltage domain (voltage
%f instead of %f / neutral region) %s
LSLOCH2L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Message: Level shifter (high to low) must be located in the lower voltage domain (voltage
%f instead of %f / neutral region) %s
LSPOWALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Message: Level shifter must be located outside power domain %s (in a region always
powered-on): %s
LSPINVOLT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Message: Level shifter badly connected: %s. Pin voltage is %f instead of %f: %s
6
Contents
ICINSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Message: Missing isolation cell for power domain %s1: %s2. From pin/signal: %s3 to pin/
signal: %s4
ICINSIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Message: Missing isolation cell for power domain %s1: %s2. From pin/signal: %s3 to pin/
signal: %s4
ICNONEED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Message: Isolation cell %s is unnecessary: %s
ICNONEEDIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Message: Isolation cell %s is unnecessary: %s
ICLOCALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Message: Isolation cell must be located outside power domain %s (in a region always
powered-on): %s
ICNOBUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Message: No buffer is allowed between output port %s of power domain %s and isolation
cell %s
ICPINVOLT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ICOFFVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Message: Isolation cell power off value mismatch with control specification of power
domain %s1: %s2. Power off value is %s3 instead of %s4: %s5. Control signal power on
value %s6: %s7
RTLPOW01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Message: First argument to $power (power domain name) must be a quoted string. Current
$power statement will be ignored by Leda power checks
RTLPOW02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Message: Second argument to $power (power_on net) must be a valid signal name. Current
$power statement will be ignored by Leda power checks
RTLPOW03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Message: Third argument to $power (on_sense expression) must be a valid expression.
Current $power statement will be ignored by Leda power checks
RTLPOW04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Message: Fourth argument to $power (power_on ack net) must be a valid signal name.
Current $power statement will be ignored by Leda power checks
RTLPOW05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Message: Fifth argument to $power statement (ack_sense expression) must be a valid
expression. Current $power statement will be ignored by Leda power checks
Contents
RTLPOW06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Message: Argument must be a valid instance name. Current $power statement will be
ignored by Leda power checks: Argument %d
RTLPOW07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Message: $power must occur in an initial block
RTLPOW08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Message: $power statement must not be nested within any control structure
RTLPOW08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Message: Power procedure call must not be nested within any control structure
RTLPOW09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Message: $power statement must not be preceded by any timing control
RTLPOW09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Message: Power procedure call must not be preceded by any timing control
RTLPOW10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Message: Each instance in a design may be named in a power statement only once. Instance
name will be ignored in enclosing statement: %s
RTLPOW11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Message: Power domains cannot be redefined at different hierarchical levels. Current
statement will be ignored in power domain elaboration
RTLPOW20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Message: Signals passed as arguments to $power must be wires declared in the same module
RTLPOW20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Message: Signals passed as arguments to the power procedure call must be declared in the
same design entity
RTLPOW21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Message: Register initialized by a constant
RTLPOW22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Message: Extra drivers detected for powerup_ack_net signal: %s
RTLPOW23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Message: Non edge-sensitive logic detected on boundary of power-down region.
RTLPOW24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Message: Nested non-contiguous power regions detected
RTLISO00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Message: Wrong number of arguments passed - exactly 4 arguments are expected. Current
$isolate statement will be ignored by Leda power checks
RTLISO01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Message: First argument to $isolate (output net) must be a valid signal name. Current
$isolate statement will be ignored by Leda power checks
RTLISO02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Message: Second argument to $isolate (enable net) must be a valid signal name. Current
$isolate statement will be ignored by Leda power checks
RTLISO03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Message: Third argument to $isolate (input net) must be a valid signal name. Current
$isolate statement will be ignored by Leda power checks
Contents
RTLISO04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Message: Output and input signals must be of the same type. Current $power statement will
be ignored by Leda power checks
RTLISO05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Message: Fourth argument to $isolate statement must have the same type as the output signal
(first argument). Current $isolate statement will be ignored by Leda power checks
RTLISO06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Message: $isolate must be in an always block
RTLISO07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Message: Enclosing always of $isolate must be combinational
RTLISO08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Message: Each signal in $isolate must appear in sensitivity list of enclosing always block
RTLRET00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Message: Wrong number of arguments passed - at least 5 arguments are expected. Current
$retain statement will be ignored by Leda power checks
RTLRET01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Message: First argument to $retain (save_signal net) must be a valid 1 bit signal name.
Current $retain statement will be ignored by Leda power checks
RTLRET02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Message: Second argument to $retain (save_sense expression) must be a valid expression (0
or 1). Current $retain statement will be ignored by Leda power checks
RTLRET03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Message: Third argument to $retain (restore signal) must be a valid, 1-bit signal name.
Current $retain statement will be ignored by Leda power checks
RTLRET04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Message: Fourth argument to $retain statement (restore_sense expression) must be a valid
expression. Current $retain system task will be ignored by Leda power checks
RTLRET05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Message: Fifth argument to $retain statement (type) must be a valid type. Current $retain
statement will be ignored by Leda power checks
RTLRET06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Message: Argument must be a valid instance name. Current $retain statement will be
ignored by Leda power checks: Argument %d
RTLRET07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Message: $retain must occur in a TOP level initial block
RTLRET08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Message: $retain statement must not be nested within any control structure
RTLRET09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Message: $retain statement must not be preceded by any timing control
RTLRET10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Message: Extra drivers detected for powerup_ack_net signal
Contents
10
Preface
Preface
About This Manual
This book contains reference information for prepackaged rules that come with the Leda
Checker tool. This information mirrors the information available in the HTML-based
help files that you access directly from the Leda Checker tools Error Report. The
purpose of this book is to provide a reference that you can view online or print out so
that you can review available prepackaged rules and decide which ones you want to use
before running the Checker tool on your HDL source files. On the other hand, the
HTML-based help system is designed to provide random access to this same
information from the Checker Error Report, so that you can quickly access more
information about a specific rule that was violated, including in some cases, circuit
diagrams and valid and invalid examples of Verilog or VHDL code.
This book is intended for use by hardware design and quality assurance engineers who
are already familiar with VHDL or Verilog.
There is a separate book for each policy (set of prepackaged rules) that Leda
supports.
11
Preface
Related Documents
This manual is part of the Leda document set. To see a complete listing or to navigate to
another online document in the set, refer to the Leda Document Navigator.
Manual Overview
This manual contains the following chapters and appendixes:
Preface
Chapter 1
Power Coding Rules
Bold
Monospace
Italic or Italic
In body text:
In the previous example, prod_dir is the directory where your
product must be installed.
| (Vertical rule)
[ ] (Square brackets)
In this example, you must enter at least one pin name (pin1), but
others are optional ([pin2 pinN]).
12
Preface
13
Preface
14
1
Power Coding Rules
Introduction
This chapter presents reference information for the Power policy. This policy contains
general-purpose rules that cover many aspects of low-power checks, and a list of new
prepackaged netlist checks in this domain.
Attention
15
TOP ( 1. 2V)
TOP. B ( 1. 4V)
TOP. A ( 1. 2V)
A
A
ALS Y
B
A
TOP. LS1
Y
TOP. B. G1
TOP. A. G1
A
TOP. A. G2
TOP. G1
ALS Y
TOP. LS2
TOP. A. G3
16
Y
TOP. B. G2
All cells instantiated in a multi-voltage design must work at the voltage level of the
power domain in which they have been instantiated. This usually means different
technology libraries for each voltage level. It also means that these technology libraries
must include the appropriate level-shifter cells. The common practice is to group all
these libraries into a common target library called a multi-NLDM library where NLDM
stands for Non-Linear Data Model. Library selection is done by setting power contexts.
When dealing with multi-voltage designs, you also need to instantiate isolation cells to
protect the power domains from each other. These must also appear in the technology
libraries.
In most cases, information about power domains, cannot be extracted automatically
from a design, and so you need to provide it. You can do this by:
Using commands such as create_power_domain in the Tcl-shell.
Using the Verilog $power system task call or the VHDL power procedure call in
RTL code.
Scanning source power net trees in the PG-netlist (PG stands for Power-Ground)
Leda accepts all these methods and also allows you to combine them. In addition, the
commands that Leda uses for defining power domains are identical to the commands
used by other Synopsys tools.
The following sections contain details on using each of these methods to define power
domains for Leda and the rules available to check them.
17
Power Domains
This section describes the different ways to infer power domains in Leda. These are:
Using commands such as create_power_domain in the Tcl-shell.
Using the $power and $isolate system calls in RTL code.
Scanning source power net trees in the PG-netlist (PG stands for Power-Ground)
#If no cells are specified, then power domain is associated with TOP
Leda> create_power_domain POW12
Leda> create_power_domain POW14 object_list [get_cells IB]
For complete syntax of these commands, refer section Power Tcl commands on
page 60.
When you create a power domain, Leda can automatically infer level shifters and
isolation cells from DB libraries, if the corresponding cells have the following
attributes:
Level shifter: is_level_shifter
Isolation cell: is_isolation_cell
Leda can also infer the cells if you have specified them explicitly in the Tcl shell using
the following commands:
Leda> set_level_shifter
<cell_name_list>
18
Once this inference is complete, Leda provides many checks for coherence of the power
domains. For example:
LSINSALL - Checks that a level shifter has been inserted on every connectivity
path between logic or wires of two distinct voltage domains (with two different
voltage levels).
LSNONEED - Check that level shifters have not been inserted between voltage
regions/blocks of the same voltage level.
LSPINVOLT - Checks that level shifter pins are connected to the correct voltage
domains, i.e. the voltage levels of the two voltage domains separated by a given
level shifter match the voltage values specified for the two (in and out) pins of the
given level shifter
ICINSALL - Checks that isolation cells are inserted on any connectivity path of any
port of a power domain.
ICNONEED - Checks that isolation cells are inserted on a path that does neither
reaches any power domain input port nor originates from any output port of a power
domain
ICNOBUF - Checks that no buffers are present between the output ports of a power
domain and the isolation cells
When instructed to do, Leda infers each of the following power domains:
initial $power (<domain_name>, <power_on_net>, <on_sense_expression>,
<power_on_ack_net>, <ack_sense_expression>, <instance1>, <instance1>
, ... , <instanceN> )
19
This is exactly as if you had specified the following Tcl power command:
create_power_domain <domain_name> [-power_down]
[-power_down_ack <net or pin>] [-power_down_ctrl <net or pin>]
[-power_down_ack_sense <0 or 1>] [-power_down_ctrl_sense <0 or 1>]
[-object_list <cell set>]
The Leda checker handles power domains inferred from RTL in exactly the same way as
their equivalent Tcl-specified power domains, with the following restrictions:
Power domains inferred from RTL cannot be removed by the command
remove_power_domain. Leda issues an error message if remove_power_domain is
called in the same Tcl session after command infer_power_domains.
Command report_power_domain is available on the power domains inferred from
RTL.
In Verilog, a power domain is defined through the $power system task called from an
initial statement like:
initial $power (<domain_name>, <power_on_net>, <on_sense_expression>,
<power_on_ack_net>, <ack_sense_expression>, <instance1>, <instance1>
, ... , <instanceN> )
Arguments
domain_name
power_on_net
20
width is wider than one bit, the lowest bit is used. Bus
representation for staggered power-on is not supported in this
version.
ack_sense_expression A constant number indicating the power-available sense of
the power-ack expression. The sense expression must have the
same width as the power-ack expression in a bit-to-bit
correspondence to the power-ack expression, and should only
consist of 1s and 0s (no xs). Presently, only single bits are
supported. If the number has more than one bit, only the
lowest bit is used.
instance_n
For example:
initial $power(pd1, pd_sig, 1`b0, p_ack, 1`b1, a, b*)
Attention
Arguments
domain_name
on_sig
on_sense
ack_sig
The ack_sig must be an output signal and the data type must
match with that of the data type of on_sig. It can take the value
of any constant expressions or a single bit value 0 or 1.
21
ack_sense
instance_n
For example:
power("domain_name", power_on, "1", power_ack, "1", "IP1");
22
VDD1 ( 1. 2V)
VDD2 ( 1. 4V)
TOP
T OP. A
T OP. B
A
A
ALS Y
Y
B
TOP. A. G1
T OP. LS1
Y
B
TOP. B. G2
23
But Leda does not automatically infer power domains from a PG-Netlist description.
You must execute following commands to perform the inference:
infer_power_domains power_nets {VDD1 VDD2}
More precisely, Leda infers the power domains and their corresponding boundaries that
are defined as follows:
The power domain Leda infers for a given power net. For example, VDD1 in
Figure 2 is the set of gates/cells that are connected only to those power nets/ports of
the PG-Netlist that are driven by the primary power port corresponding to the given
power net - e.g. TOP.VDD1 above (the only implies in particular that the cells that
are connected to multiple power supplies are not included in such power domains).
The boundary of an inferred power domain is the list of pins of the corresponding
gates/cells that are either connected directly to primary ports or that are connected to
at least one gate/cell that is not part of the inferred power domain.
The power domain is not considered always on if the supplied power net is switchable.
Moreover, in Leda, you can specify the type of power switch cells with the following
command:
set_power_switch <cell_name_list>
Leda bypasses instances of specified power switch cells to follow the inference. It gets
the internal power net to reach connected cells to infer sub power domains that are not
always on by the presence of these switch boxes.
Note
Leda does not recognize currently the enable and the acknowledge signal of
inferred domains when bypassing a single or daisy-chained power switch
cells.
24
VDD2 ( 1. 4V)
TOP
TOP. A
TOP. B
A
A
B
A
TOP. A. G2
ALS Y
TOP. LS1
B
TOP. B. G1
TOP. A. G1
A
A
Y
ALS Y
TOP. LS2
B
TOP. B. G2
TOP. A. G3
25
VDD1 ( 1. 2V)
VDD2 ( 1. 4V)
TOP
TOP. A
TOP.B
A
A
ALS Y
B
A
TOP. B. G1
TOP. LS1
TOP. A. G1
A
TOP. A. G2
B
TOP. A. G3
TOP. G1
ALS Y
TOP. LS2
Y
TOP. B. G2
26
27
connect _power _
domai n
Power domai ns
speci f i cat i ons
Level shi f t er s
checks
<<OR>>
cr eat e_power _
domai n
i nf er _power _
domai ns
( $power I n RTL)
i sol at i on cel l s
checks
VDD2 ( 1. 4V)
TOP
TOP. A
TOP. B
A
A
B
ALS Y
TO
P.B.G
1
TOP. LS1
T OP. A. G1
A
TOP. A. G2
B
TOP. A. G3
TOP. G1
ALS Y
TOP. LS2
28
Y
TOP. B. G2
Level shifters are correctly instantiated/connected in this example. If you check it using
the following sequence (sequence A) of Tcl commands, power domains are
automatically inferred from the power ports VDD1 and VDD2.
Leda> infer_power_domains power_nets {VDD1 VDD2}
Leda> check
But lets assume you check the same PG-Netlist using the power domains specified
through the following sequence (sequence B) of Tcl commands:
Leda> create_power_net_info VDD1 power nominal_voltages {1.2}
source_port TOP.VDD1
Leda> create_power_net_info VDD2 power nominal_voltages {1.4}
source_port TOP.VDD2
Leda> check
In this case, power net connections in the PG-Netlist are ignored (because no
infer_power_domains is executed), and the checker reports a missing level shifter
between TOP.A.G3 (part of POWA, connected to VDD1) and TOP.G1 (part of
POW_TOP, connected to VDD2), as well as an unnecessary level shifter TOP.LS2
between TOP.G1 and TOP.B.G2 (both gates respectively part of POW_TOP and POWB,
both power domains connected to VDD2).
The reason for these differences between both sequences (one with
create_power_domain commands, one with infer_power_domains commands) is caused
by the difference between the specification of the power domains (using
create_power_domain commands, typically written at RTL stage) and the actual
implementation of the power domains (inferred by infer_power_domains commands
from the PG-Netlist).
29
Leda> check
In this sequence, the first check only the power domains specified with the
create_power_domain commands (so the results are the same as sequence B ),
whereas the second check uses the inferred power domains which have higher priority
for the checks (so the results are the same as sequence A ).
In addition, the execution of the command infer_power_domains in this sequence
reports each instantiated standard cell that is effectively connected (in the PG-Netlist) to
a primary power net (VDD1 or VDD2). This is different from the primary power net
associated with the power domain specified with create_power_domain and including
the instantiated cell.
30
In this example, the first infer_power_domains command (for PD1) reports the
following consistency error:
Inferring power domain PD1 from power net VDD1 ...
Error: Cell 'TOP.G1' is connected to primary power net 'VDD1' while
located in power region of power domain 'POW_TOP' connected to primary
power net 'VDD2'. (POW-014)
Inference of power domain PD1 completed.
Power domai ns
i nf erence f rom
power net
Power domai ns
speci f i cat i ons
connect _power_
domai n
St andard cel l s
checks
<<AND>>
Power Cells
As mentioned previously, cells such as level shifters and isolation cells can be
automatically identified from DB library information or explicitly specified with shell
commands. For isolation cells, Leda can also automatically recognize standard cells
used as isolation cells based on structure analysis. In this section we describe how this is
done.
DB cell
DB cells used as level shifters must have the predefined Boolean attribute
is_level_shifter set to true.
31
Here, the cell names are Verilog module/primitive names or VHDL entity names.
Subsequent calls to the set_level_shifter command add more cells to the list of level
shifter cells. You can remove a cell from the list of level shifters using the
remove_level_shifter Tcl command.
Leda> remove_level_shifter {<list of cell names>}
Note that only the level shifters defined with set_level_shifter can be removed; not the
DB cells.
You can specify the specific type of the level shifter, buffer-type or enabled-type as
follows. You can specify the enable pin of the cell (if any) using the set_enable_pin
routine described in section Specifying Enable Pin Names on page 44. If you do this,
the corresponding cell is an enabled level shifter and can be used as an isolation cell.
32
enable type:
<cell_type_1>
<cell_type_2>
...
<cell_type_N>
* from DB libraries:
buffer type:
<cell_type_1>
<cell_type_2>
...
<cell_type_N>
enable type:
<cell_type_1>
<cell_type_2>
...
<cell_type_N>
by instance:
* with set_level_shifter:
33
<cell_instance_1>
<cell_instance_2>
...
<cell_instance_N>
* from DB libraries:
<cell_instance_1> : <library>
<cell_instance_2> : <library>
...
<cell_instance_N> : <library>
DB cell
DB cells used as isolation cells must have the predefined Boolean attribute
is_isolation_cell set to true.
Some level shifter cells can also be used as isolation cells.
With the set_isolation_cell Tcl command, you can specify either a list of cell names
(Verilog module/primitive names or VHDL entity names) or a list of cell instances. Cell
instances are hierarchical instance names used to differentiate between instances of a
cell that are used for different purposes. For example, they are used to differentiate
several instances of a given NAND cell that are used as isolation cells from other
instances of the same NAND cell that are used as logic gates.
34
Subsequent calls to the set_isolation_cell command add more cells to the list of isolation
cells. You can remove a cell from the list of isolation cells using the
remove_isolation_cell Tcl command.
Leda> remove_isolation_cell {<list of cell names>} | -instances
{<instance_list>}
Note
Only isolation cells defined with set_isolation_cell can be removed and not
the DB cells.
Arguments
output_net
enable_net
input_net
The input data to be isolated. Its type must match exactly the
type of the output variable.
unpowered_expr
always @*
$isolate(<output_net>, <enable_net>, <input_net>, <unpowered_expr>);
or
always @*
begin
$isolate(<output_net>, <enable_net>, <input_net>, <unpowered_expr>);
end
Leda infers an isolation cell instance from any $isolate system call, irrespective of its
declaration place. But a predefined check issues an error message if the $isolate call is
not in an always construct that is level-sensitive (combinatorial, not edge-sensitive) and
that includes all three nets of the $isolate call in its sensitivity list.
35
Ledas inference of isolation cells specified in the RTL code with $isolate will be
automatic (no user control). The $isolate PLI system call is just another way to specify
isolation cells, complementary to the LIB/DB attribute is_isolation_cell or the Tcl
command set_isolation_cell.
Leda will infer an isolation cell instance for the following RTL code:
always @*
begin
$isolate(<output_net>, <enable_net>, <input_net>,
<unpowered_expression>);
end
It does so in exactly the same way as it would have for the following RTL code:
always @*
begin
<output_net> =(<enable_net> ? <input_net> : <unpowered_expression>);
end
The resulting inferred gate instance (with an implicit name such as ~isolate%d) is
specified as an isolation cell using the command:
set_isolation_cell instances {<full_path>.~isolate%d}
36
The only difference is the specific (implicit) naming of the instance and its registration
as an isolation cell instance (equivalent use of set_isolation_cell).
Isolation cells inferred from RTL are handled by the Leda checker exactly as the
isolation cells specified with a DB attribute (in particular, they cannot be removed with
remove_isolation_cell). The command report_isolation_cells will report the $isolate
inferred cells with the file name and line number at which they appear in the RTL code.
Arguments
data_out
iso
data_in
37
clamp
The recognition is done while checking the necessity of an isolation cell on each
connectivity path connected to a power region. Leda performs a structural analysis of
the connection of the other pin of the cell to find a dependency with the power down
control signal in the specification of the power domain. If the cell is a valid isolation
cell, then the other pin is equivalent to the enable pin of the cell.
38
In the following example, Leda recognizes TOP.G1 standard cell as isolation cell
Leda> enable_isolation_cell_recognition
Leda> create_power_domain power_down power_down_ctrl [get_ports EN]
object_list [get_cells A]
TOP
EN
A
TOP. A
TOP. B
B
TOP. G1
39
* from DB libraries:
<cell_type_1>
<cell_type_2>
...
<cell_type_N>
by instance:
* with set_isolation_cell:
<cell_instance_1>
<cell_instance_2>
...
<cell_instance_N>
* from DB libraries:
<cell_instance_1> : <library>
40
<cell_instance_2> : <library>
...
<cell_instance_N> : <library>
* recognized:
<cell_instance_1>
<cell_instance_2>
...
<cell_instance_N>
Leda issues a warning message if you execute the report_isolation_cells command when
the recognition has been enabled but the checks have not been run.
41
VDD1 (1.2V)
TOP
VDD2 (1.4V)
TOP.G1
ACK
EN
TOP.A
TOP.B
A
B
TOP.A.G2
A
Y
ALS Y
TOP.LS1
TOP.B.G1
TOP.A.G1
A
B
A
Y
ALS Y
TOP.LS2
TOP.A.G3
Y
TOP.B.G2
Leda bypasses instances of specified power switch cells to follow inferencing. This step
is similar in getting the internal power net to reach connected cells.
42
Here, cell names are Verilog module/primitive names or VHDL entity names. For
example:
Leda> set_pin_voltage LS12V A 1.2
Leda> set_pin_voltage LS9_12V Y 0.9
43
If the cell is a DB cell, the values set by the set_pin_voltage command supersede the
values of the DB attributes input_signal_level and output_signal_level, if these
attributes are defined.
Leda uses the pin names and voltage level information. For example, when checking
that the pins of a level shifter or an isolation cell are connected to the correct voltage
domains. For example, see rules LSPINVOLT and ICPINVOLT.
You can list all pin voltage values defined for a given cell with the report_pin_voltages
Tcl command.
Leda> report_pin_voltages <cell_name>
For example:
Leda> report_pin_voltages LS9_12V
===== Cell LS9_12V pin voltages =====
Pin A : 1.2 volt (DB)
Pin Y : 0.9 volt (Tcl)
Pin EN : <not found>
For example:
Leda> set_power_pin CELL VDD -power
Leda> set_power_pin "CELL" VSS -gnd
For level shifters and other multi-voltage cells, you need to qualify both power pins.
44
If the cell is a DB cell and if one pin of the cell has the Boolean attribute
isolation_cell_enable_pin set to true, then the corresponding pin is the enable pin.
If the cell was defined with a Tcl command, you can specify the enable pin name
with the set_enable_pin Tcl command as follows:
Leda> set_enable_pin <cell_name> <enable_pin_name>
Here, cell names are Verilog module/primitive names or VHDL entity names. For
example:
Leda> set_enable_pin IC12V EN
The enable pin information is used to determine if a level shifter can be used as an
isolation cell as well, or more generally for checks requiring the enable functionality and
its corresponding pin.
You can find the enable pin for a given cell, if any, with the command
report_enable_pin.
Leda> report_enable_pin <cell_name>
For example:
Leda> report_enable_pin IC12V
Enable pin of IC12V: EN
Leda> report_enable_pin IC12VB
Enable pin of IC12VB: <not found>
Note that the enable pin can also be defined with a set_pin_voltage command. However
each command has a different purpose. Command set_enable_pin defines the enable
functionality of the pin, and set_pin_voltage defines the name of the pin and its voltage,
regardless of its functionality.
Power Checks
This section contains some examples of how Leda can combine power-related
information from different sources (RTL, Tcl, PG-Netlist) with an extensive set of
prepackaged rules to create and test a complete and coherent power environment.
45
TOP. B ( 1. 4V)
A
A
ALS Y
B
A
Y
B
TOP. B. G1
TOP. A. G1
TOP.LS1
A
TOP. A. G2
B
TOP. A. G3
TOP. G1
ALS Y
TOP. B. G2
TOP. LS2
46
G2(INT, A2);
LS1(INT4, INT1);
LSCELL
LS2(INT5, INT3);
endmodule
47
By using the following power Tcl commands, Leda identifies the unwanted level shifter
present in the circuit as shown in Figure 11:
Leda> create_power_net_info VDD12 -power -nominal_voltages {1.2}
Leda> create_power_net_info VDD14 -power -nominal_voltages {1.4}
Leda> create_power_domain POW12
#No cell is specified. So, power domain is associated to TOP
Leda> create_power_domain POW12A -object_list [get_cells IA] -power_down
Leda> create_power_domain POW14B -object_list [get_cells IB] -power_down
Leda> connect_power_domain POW12 -primary_power_net VDD12
Leda> connect_power_domain POW12A -primary_power_net VDD12
Leda> connect_power_domain POW14B -primary_power_net VDD14
Leda> check p POWER
48
49
TOP. PD
TOP
TOP. RST
TOP. G1
TOP. A
TOP.B
A
B
A
TOP. A. G1
A
IC Y
B
Y
TOP. B. G1
TOP. I C1
A
TOP. A. G2
B
TOP. A. G3
TOP. G2
Y
TOP. B. G2
50
BUFCELL
G2(INT5, INT2);
endmodule
By using the $isolate call and replacing the instantiation of ICCELL in the Verilog
code with:
$isolate(INT4, INT3, INT1,1b0);
51
You can see theres an isolation cell missing on the path containing TOP.G2. Regardless
of how you inferred the isolation cells, running the following command causes the rule
ICINSOUT to be flagged as follows:
Leda> check p POWER
51:
52
VDD1 ( 1. 2V)
VDD2 ( 1. 4V)
TOP
TOP. A
TOP. B
A
A
B
TOP. A. G2
ALS Y
TOP. B. G1
TOP. A. G1
A
B
TOP. A. G3
TOP. LS1
A
TOP. G1
ALS Y
A
Y
TOP. B. G2
TOP. LS2
53
You need to make sure that the following conditions are met when setting the operating
voltage to power nets:
The voltages set by the command set_voltage must fall within the ranges specified
by the command create_power_net_info.
The command set_voltage can be applied on an internally generated power net, but
value must fall within its inherited voltage ranges and less than its parent.
The operating voltage of the power net driving the design-level (top) power domain
must match the operating voltage of the design level operating condition.
The significance of relative always on setting is that, even though two power domains
may be shut down, and if one power domain is always on relative to the other power
domain, then you dont need an isolation cell on the net crossing from the power domain
that is always on, to the relative power domain.
The following example illustrates how command set_relative_always_on could be used
in creating a relative always on relationship between power domains.
54
TOP
TOP.A
1)
1)
Y
B
TOP.B
EN
ISO
A
Y
B
TOP.A.G1
2)
2)
TOP.B.G1
A
TOP.A.G2
EN
A
ISO
TOP.B.G2
3)
3)
A
A
Y
B
TOP.B.G3
4)
4)
TOP.A.G3
A
A
Y
TOP.B.G4
TOP.A.G4
Unnecessary Isolation
Cells
Yes
55
Unnecessary Isolation
Cells
Yes
Now, we configure that power domain PDA is always on relative to power domain PDB
using command set_relative_always_on.
Leda> set_relative_always_on PDA -relative_to PDB
The results of isolation cells checks after using set_relative_always_on are tabulated as
follows:
Table 3: Isolation Cells Checks with set_relative_always_on
Paths
Yes
Path 2 - from A to B
Path 3 - from B to A isolated
Path 4 - from B to A
56
Unnecessary Isolation
Cells
Yes
Arguments
save
save_sense
restore
restore_sense
instances
For example:
$retain ( savecntl, 1, savecntl, 0, mmu, rla, u*s );
The above syntax specifies a retention register for the instances named mmu, rla, and all
instances whose name begins with u and end with s. The savecntl signal controls both
the save and restore operations of the retention register. A positive transition saves the
memory state into the retention registers, and a negative transition restores the state
from the retention registers.
You can specify any instance present in the design only once in the $retain system task.
The instance that you specify in a $retain system task completely controls the retention
behavior of the specified instance.
57
If you do not explicitly specify an instance in a $retain system task, then the closest
ancestor in the instance hierarchy that is explicitly specified in the $retain system task
controls the retention behavior. If the ancestor is not present, the instance shall not
exhibit retention.
The following rules have to be followed while using a $retain system task:
A $retain system task can occur only at the top level of an initial block.
A $retain system task should not be present within any control structure like if,
while, for, case, etc.
A $retain system task should not be controlled by a timing construct.
Pin en {
always_on: true
}
}
}
58
Tcl command
You can specify an always_on pin using the set_attribute Tcl command. For example:
set_attribute -type boolean [get_pins H1/U1/A] always_on true
always_on: true
}
}
59
connect_power_domain
Use the connect_power_domain command to connect a power domain to power net
information.
Syntax
connect_power_domain <name>
[-primary_power_net <name>]
[-backup_power_net <name>]
[-internal_power_net <name>]
[-primary_gnd_net <name>]
[-backup_gnd_net <name>]
[-internal_gnd_net <name>]
Arguments
-primary_power_net
-primary_ground_net
-backup_power_net
-backup_ground_net
-internal_power_net
-internal_ground_net
The following conditions should be met during connection to handle internal power nets
generation:
The names supplied for internal_power_net and -internal_ground_net options
should not be used as a name of created power nets.
The corresponding primary connection must be supply to allow inheritance between
the primary net and the internal net.
60
The generated power nets can only be used in primary connections when setting up
subnetting relationships
create_operating_conditions
Use the create_operating_conditions command to create a new operating condition in
the specified library.
Syntax
create_operating_conditions [-name name] \
-library { lib_name1 lib_name2...} -voltage voltage_value
-process <process_value> -temperature <temperature>
[-tree_type tree_type] [-calc_mode calc_mode]
[-rail_voltages rail_value_pairs]
Arguments
-name
-library
-process
-temperature
-voltage
-tree_type
-calc_mode
-rail_voltages
create_power_domain
Use the create_power_domain command to create a power domain.
Syntax
create_power_domain <domain_name> [-power_down]
[-power_down_ack <net or pin>] [-power_down_ctrl <net or pin>]
[-object_list <cell set>] [-power_down_ack_sense <0 or 1>] \
[-power_down_ctrl_sense <0 or 1>]
Arguments
domain_name
-power_down
61
-power_down_ctrl
Specify the single bit net that powers down the domain. If the
value of the net is 1, then the domain is powered-down
(always active high). If this option is not used, then the
corresponding power domain is always on.
-power_down_ack
Specify the single bit net that acknowledges the power down
state of a domain.
-object_list
-power_down_ack
_sense
-power_down_ctrl
_sense
create_power_net_info
Use the create_power_net_info command to create a power net information.
Syntax
create_power_net_info [-power] | [-gnd] [-switchable]
[-voltage_ranges {min_v1 max_v1 min_v2 max_v2 ...}] \
[-nominal_voltages {NOM_V1 NOM_V2 ... }]\
[-source_port design_port] name
Arguments
-power, -gnd
62
-voltage_range
-switchable
-nominal_voltages
-source_port
Specify the top level port in the design that is the source of this
power/gnd net. It is kept to allow inference of power domains
from power net trees.
Note
delete_operating_conditions
Use the delete_operating_conditions command to delete the operating conditions.
Syntax
delete_operating_conditions [-name name] \
-library { lib_name1 lib_name2...}
Arguments
-name
-library
disable_isolation_cell_recognition
Use the disable_isolation_cell_recognition command to disable the recognition of
isolation cells.
Syntax
disable_isolation_cell_recognition
enable_isolation_cell_recognition
By default, Leda accepts only those DB cells with the attribute is_isolation_cell or those
cells/modules specified as isolation cell with the set_isolation_cell command as valid
isolation cells. Use the enable_isolation_cell_recognition command to force the checker
to accept any standard cell having the AND or the OR function as a possible isolation
cell. In such a case, the criteria for a standard cell to be recognized as an isolation cell
for a given power domain is as follows:
Either one of the inputs of the cell is directly or indirectly (through combinatorial
logic) connected to an output of the given power domain, or the output of the cell is
directly/indirectly connected to an input of the given power domain.
An input of the cell is directly/indirectly connected to the control signal(s) specified
for the given power domain.
63
Syntax
enable_isolation_cell_recognition [-strict]
Arguments
-strict
get_all_input_boundaries_from_power_domain
Use the get_all_input_boundaries_from_power_domain command to get the list of input
pins of cells used by the checks on power domains.
Syntax
get_all_input_boundaries_from_power_domain <inferred_power_domain_name>
get_all_output_boundaries_from_power_domain
Use the get_all_output_boundaries_from_power_domain command to get the list of
output pins of cells used by the checks on power domains.
Syntax
get_all_output_boundaries_from_power_domain <inferred_power_domain_name>
get_cells
Use the get_cells command to create a list of cells.
Syntax
get_cells [-hierarchical] [-filter expression] [-quiet] [-regexp]
[-nocase] [-exact] [-of_objects objects] [patterns]
Arguments
-hierarchical
64
expression
-quiet
-regexp
-nocase
-exact
-of_objects
patterns
get_clocks
Use the get_clocks command to create a collection of clocks.
Syntax
get_cells [-hierarchical] [-filter expression] [-quiet] [-regexp]
[-nocase] [-exact] [patterns]
Arguments
-hierarchical
expression
-quiet
-regexp
-nocase
-exact
-of_objects
get_nets
Use the get_nets command to create a list of pins.
Syntax
get_nets [-hierarchical] [-filter expression] [-quiet] [-regexp]
[-nocase] [-exact] [-of_objects objects] [patterns]
Arguments
-hierarchical
expression
-quiet
-regexp
-nocase
-exact
65
-of_objects
patterns
get_nth_power_net
Use the get_nth_power_net command to return the name of the nth power net.
Syntax
get_nth_power_net name
Arguments
name
get_pins
Use the get_pins command to create a list of nets.
Syntax
get_pins [-hierarchical] [-filter expression] [-quiet] [-regexp]
[-nocase] [-exact] [-of_objects objects] [patterns]
Arguments
-hierarchical
expression
-quiet
-regexp
-nocase
-exact
-of_objects
patterns
get_ports
Use the get_ports command to create a list of ports.
66
Syntax
get_ports [-hierarchical] [-filter expression] [-quiet] [-regexp]
[-nocase] [-exact] [-of_objects objects] [patterns]
Arguments
-hierarchical
expression
-quiet
-regexp
-nocase
-exact
-of_objects
patterns
get_power_cells
Use the get_power_cells command to return the cells of a given power domain.
Syntax
get_power_cells name
Arguments
name
get_power_domains
Use the get_power_domains command to create a list of power domains.
Syntax
get_power_domains [-filter expression] [-quiet] [-regexp]
[-nocase] [-exact] [patterns]
Arguments
expression
-quiet
-regexp
67
-nocase
-exact
patterns
get_power_down
Use the get_power_down command to return the power down net associated with the
given power domain.
Syntax
get_power_down name
Arguments
name
get_power_down_ack
Use the get_power_down_ack command to return the power down ack net associated
with the given power domain.
Syntax
get_power_down_ack name
Arguments
name
get_power_net_max_voltage
Use the get_power_net_max_voltage command to return the maximum value of the
power net voltage values.
Syntax
get_power_net_max_voltage name
Arguments
name
68
get_power_net_min_voltage
Use the get_power_net_min_voltage command to return the minimum value of the
power net voltage values.
Syntax
get_power_net_min_voltage name
Arguments
name
get_power_net_source_port
Use the get_power_net_source_port command to return the design port that is the source
of the power net.
Syntax
get_power_net_source_port name
Arguments
name
get_power_net_type
Use the get_power_net_type command to return the type of the power net (GND or
POWER).
Syntax
get_power_net_type name
Arguments
name
getn_power_net
Use the getn_power_net command to return the number of power nets.
69
Syntax
getn_power_net
infer_power_domain
Use the infer_power_domain command to infer a power domain in a PG-Netlist from a
power net.
Syntax
infer_power_domain [-power_net <name>] domain_name ]
Arguments
-power_net
domain_name
infer_power_domains
Use the infer_power_domains command to infer a power domain from the RTL
($power).
Syntax
infer_power_domains [-verbose] [-power_nets <power_net_list>]
Arguments
-verbose
-power_nets
remove_isolation_cell
Use the remove_isolation_cell command to specify the isolation cell to be removed
from the list of isolation cells created by consecutive calls to the set_isolation_cell
command
Syntax
remove_isolation_cell {list of cell names} | -instance {instance_list}
Only the isolation cells defined with set_isolation_cell can be removed (not the DB
cells).
70
remove_level_shifter
Use the remove_level_shifter command to specify the level shifter cells to be removed
from the list of level shifter cells created by consecutive calls to the set_level_shifter
command.
Syntax
remove_level_shifter {list of cell names}
Only the cells defined with set_level_shifter can be removed (not the DB cells).
remove_power_domain
Use the remove_power_domain command to remove a specific power domain or
specific modules/sub-hierarchies from a given power domain.
Syntax
remove_power_domain [power_domains | -all]
remove_power_net_info
Use the remove_power_net_info command to remove a power net specification.
Syntax
remove_power_net_info [ -all ] | domain_name
Arguments
-all
domain_name
71
report_enable_pin
Use the report_enable_pin command to list the enable pin if any for a given cell.
Syntax
report_clock_gating_cells cell_name
Example
This command will list the enable pin of the cell IC12V.
Leda> report_enable_pin IC12V
Enable pin of IC12V: EN
Leda> report_enable_pin IC12VB
Enable pin of IC12V: <not found>
report_isolation_cells
Use the report_isolation_cells command to list all the defined isolation cells.
Syntax
report_isolation_cells
Example
This command will list all the isolation cells.
Leda> report_isolation_cells
Warning
report_level_shifter
Use the report_level_shifter command to list all the defined level shifters.
Syntax
report_level_shifter
Example
This command will list all the defined level shifters.
Leda> report_level_shifter
72
report_operating_conditions
Use the report_operating_conditions command to report all or specific operating
conditions of a given library.
Syntax
report_operating_conditions [-name name] \
-library { lib_name1 lib_name2...}
Arguments
-name
-library
report_pin_voltages
Use the report_pin_voltage command to list all pin voltage values defined for a given
cell.
Syntax
report_pin_voltages cell_name
Example
This command will list all the defined pin voltages of cell LS9_12V.
Leda> report_pin_voltages LS9_12V
report_power_domain
Use the report_power_domain command to report the information about the power
domains.
Syntax
report_power_domain object_list
Arguments
object_list
Example
This command will list all the defined power domains.
Leda> report_power_domain
73
report_power_net_info
Use the report_power_net_info command to remove the power net specifications.
Syntax
report_power_net_info [object_list ]
Arguments
object_list
report_power_pins
Use the report_power_pins command to report the power pins of the given cell.
Syntax
report_power_pins cell
Arguments
cell
report_power_switches
Use the report_power_switches command to report the power switches.
Syntax
report_power_switches
reset_isolation_cell_recognition
Use the reset_isolation_cell_recognition command to reset the isolation cell database.
Syntax
reset_isolation_cell_recognition
set_operating_conditions
Use the set_operating_conditions command to set the operating conditions.
Syntax
set_operating_conditions [-library library] [-object_list object_list] \
[-max max_condition] [-min min_condition] \
[-max_library max_library] [-min_library min_library] \
[-max_phys <max_operating_condition_name>] \
74
[-min_phys <min_operating_condition_name>] \
[-object_list object_list] [-power_domains power_domain_list] \
[condition]
Arguments
-library
-max
-min
-max_library
-min_library
-max_phys
-min_library
-object_list
-power_domains
condition
set_power_domain
Use the set_power_domain command to set the power domain with given instances as
power regions.
Syntax
set_power_domain
Arguments
-name
-instance_list
set_power_domain_ctrl
Use the set_power_domain_ctrl command to associate control signals(s) with each
power domain.
75
Syntax
set_power_domain_ctrl [-name domain_name] [-signals signal |
{signal_list}
value | {value_list}
Arguments
signal_list
value_list
Example
This command will switch on power domain POW1 when TOP.CTRL1 is equal to 1 and
TOP>CTRL2 is equal to 0.
Leda> set_power_domain_ctrl -name POW1 -signals {TOP.CTRL1 TOP.CTRL2}
10
set_power_off_value
Some low-power methodologies impose the output of isolation cells to be set to a
specific fixed value (0 or 1) when the corresponding power domain is switched off. Use
the set_power_off_value command to specify this fixed value for any isolation cell
instance.
Syntax
set_power_off_value
boolean_value
{isolation_cell_instance_list}
Example
Leda> set_power_off_value 0 TOP.A.ISCEL3
set_power_pin
Use the set_power_pin command to specify the power pins of the given cell.
Syntax
set_power_pin
set_power_switch
Use the set_power_switch command to specify the cell list as power switch cells.
76
Syntax
set_power_switch
Attention
set_relative_always_on
Use the set_relative_always_on command to create relative always on relationship
between domains.
Syntax
set_relative_always_on <power_domain_name> [-relative_to \
<power_domain_list>]
Arguments
power_domain_nameSpecify the power domain.
set_voltage
Use the set_voltage command to define the operating voltage for the supplied power
nets.
Syntax
set_voltage <max_case_voltage> [-min <min_case_voltage>] \
-object_list <power_net_list>
Arguments
min_case_voltage
max_case_voltage
77
Level-Shifters Ruleset
The following rules are from the Level-Shifters ruleset.
VDPAR
Message: Avoid disjoint voltage domains: %s1 and voltage
domain: %s2
Description
Do not split multiple voltage domains with the same voltage level
into different sub-hierarchies of the design (disjoint voltage
domain).
Arguments: Disjoint hierarchical module names belonging to the
same voltage domain: %s1 and %s2 are the disjoint voltage domains.
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Warning
78
TOP
T O P . A ( 0 . 9 V v o lt a g e b lo c k )
T O P . B ( 0 . 9 V v o lt a g e b lo c k )
FALSE
T O P . I A B ( 1 . 2 V v o lt a g e b lo c k )
T O P . I A B . B ( 1 . 2 V v o lt a g e
b lo c k )
T O P . I A B . A ( 1 . 2 V v o lt a g e
b lo c k )
OK
T O P . C ( 1 . 5 V v o lt a g e b lo c k )
T O P . I D ( 1 . 8 V v o lt a g e b lo c k )
OK
79
LSINSALL
Message: Missing level shifter from %f1 to %f2: %s1. From
pin/signal (voltage %f1): %s2 to pin/signal (voltage %f2):
%s3
Description
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
80
T O P ( 1 .2 V r e g io n )
T O P .I B ( 0 .9 V v o lt a g e b lo c k )
T O P .I A ( 1 .2 V v o lt a g e b lo c k )
OK
OK
OK
L S I N S H 2 L /L S I N S A L L F A L S E
OK
OK
L S I N S H 2 L /L S I N S A L L F A L S E
T O P .I C ( 0 .9 V v o lt a g e b lo c k )
T O P .I D ( 1 .2 V v o lt a g e b lo c k )
OK
OK
OK
L S I N S L 2 H /L S I N S A L L F A L S E
OK
OK
OK
81
LSINSL2H
Message: Missing level shifter from %f1 to %f2: %s1. From
pin/signal (voltage %f1): %s2 to pin/signal (voltage %f2):
%s3.
Description
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
82
T O P ( 1 .2 V r e g io n )
T O P .I B ( 0 .9 V v o lt a g e b lo c k )
T O P .I A ( 1 .2 V v o lt a g e b lo c k )
OK
OK
OK
L S I N S H 2 L /L S I N S A L L F A L S E
OK
OK
L S I N S H 2 L /L S I N S A L L F A L S E
T O P .I C ( 0 .9 V v o lt a g e b lo c k )
T O P .I D ( 1 .2 V v o lt a g e b lo c k )
OK
OK
OK
L S I N S L 2 H /L S I N S A L L F A L S E
OK
OK
OK
83
LSINSH2L
Message: Missing level shifter from %f1 to %f2: %s1. From
pin/signal (voltage %f1): %s2 to pin/signal (voltage %f2):
%s3.
Description
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
84
T O P ( 1 .2 V r e g io n )
T O P .I B ( 0 .9 V v o lt a g e b lo c k )
T O P .I A ( 1 .2 V v o lt a g e b lo c k )
OK
OK
OK
L S I N S H 2 L /L S I N S A L L F A L S E
OK
OK
L S I N S H 2 L /L S I N S A L L F A L S E
T O P .I C ( 0 .9 V v o lt a g e b lo c k )
T O P .I D ( 1 .2 V v o lt a g e b lo c k )
OK
OK
OK
L S I N S L 2 H /L S I N S A L L F A L S E
OK
OK
OK
85
LSNONEED
Message: Unnecessary level shifter: %s
Description
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
LSREDSER
Message: Level shifter %s is unnecessary (redundant
with %s1): %s2
Description
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
86
T
O
P
T
O
P
.A(1.2Vblock)
T
O
P
.B(0.9Vblock)
FA
L
SE FA
L
SE O
K
TOP(1.2Vblock)
TOP.I_A(1.2Vblock)
FALSE
TOP.I_B(1.0Vblock)
OK
FALSE
87
LSREDPAR
Message: Better split out wires after level shifters than
before: %s1. The level shifter: %s2. The level shifter: %s3
Description
It is better to split out wires after the level shifters than before in
order to minimize the number of level shifters used.
Arguments: Hierarchical name of the wire and hierarchical names of
the level shifter cell instances.
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Warning
TOP
T O P .A (1.2V b lock)
T O P .B (0.9V b lock)
F A L SE
OK
FALSE
OK
88
LSLOCALL
Message: Level shifter must be located in the lower voltage
domain (voltage %f instead of %f / neutral region) %s
Description
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Warning
89
LSLOCL2H
Message: Level shifter (low to high) must be located in the
higher voltage domain (voltage %f instead of %f / neutral
region) %s
Description
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Warning
90
LSLOCH2L
Message: Level shifter (high to low) must be located in the
lower voltage domain (voltage %f instead of %f / neutral
region) %s
Description
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Warning
91
T
O
P
T
O
P. A(1.2Vblock)
T
O
P.B(0.9Vblock)
O
K
L
SL
O
C
A
L
L
/L
SL
O
C
H
2LFA
L
SE
L
SL
O
C
A
L
L
/L
SL
O
C
H
2LFA
L
SE
L
SL
O
C
A
L
L
/L
SL
O
C
H
2LFA
L
SE
O
K
T
O
P
T
O
P.B(1.2Vblock)
T
O
P. A(0.9Vblock)
L
SL
O
C
A
L
LFA
L
SE
L
SL
O
C
A
L
L
/L
SL
O
C
L
2HFA
L
SE
L
SL
O
C
L
2HFA
L
SE
L
SL
O
C
L
2HFA
L
SE
L
SL
O
C
A
L
LFA
L
SE
TOP(1.2Vregion)
TOP.B(0.9Vblock)
TOP.A(1.2Vblock)
OK
LSLOCALL/LSLOCH2LFALSE
LSLOCALL/LSLOCH2LFALSE
OK
LSLOCALL/LSLOCH2LFALSE
92
TOP(0.9Vregion)
TOP.B(1.2Vblock)
TOP.A(0.9Vblock)
LSLOCALLFALSE
LSLOCL2HFALSE
LSLOCL2HFALSE
LSLOCALLFALSE
LSLOCL2HFALSE
TOP(1.2Vregion)
TOP.B(0.9Vblock)
TOP.A(0.9Vblock)
OK
LSLOCALL/LSLOCH2L
FALSE
LSLOCL2HFALSE
LSLOCL2HFALSE
LSLOCALLFALSE
LSLOCL2HFALSE
OK
LSLOCALL/LSLOCH2LFALSE
LSLOCALL/LSLOCH2LFALSE
93
LSPOWALL
Message: Level shifter must be located outside power
domain %s (in a region always powered-on): %s
Description
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Warning
94
TOP
OK
OK
FALSE
OK
FALSE
FALSE
OK
OK
FALSE
OK
OK
OK
FALSE
OK
FALSE
OK
OK
FALSE
OK
95
T
O
P
T
O
P
.A(1.2VP
O
W
1p
ow
er b
lock
)
T
O
P
.A
.B(09VP
O
W
1alw
ays_on
)
E
N
O
K
E
N
F
A
L
S
E
E
N
O
K
E
N
F
A
L
S
E
LSPINVOLT
Message: Level shifter badly connected: %s. Pin voltage is
%f instead of %f: %s
Description
Policy
POWER
Ruleset
LEVEL_SHIFTERS
Language
VHDL/Verilog
Type
Hardware
Severity
Warning
96
ICINSALL
Message: Missing isolation cell for power domain %s1: %s2.
From pin/signal: %s3 to pin/signal: %s4
Description
Policy
POWER
Ruleset
ISOLATION_CELLS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
97
T O P (a lw a y s_ o n )
T O P .A (p o w er b lo c k )
OK
T O P .B (a lw a y s_ o n )
EN
FALSE
EN
OK
EN
OK
OK
EN
FALSE
EN
OK
OK
EN
T
O
P
T
O
P
.A(p
o
w
er b
lo
ck
)
T
O
P
.A
.B(a
lw
a
y
s_
o
n
)
E
N
98
E
N
O
K
O
K
F
A
L
S
E
F
A
L
S
E
ICINSOUT
Message: Missing isolation cell for power domain %s1: %s2.
From pin/signal: %s3 to pin/signal: %s4
Description
Policy
POWER
Ruleset
ISOLATION_CELLS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
99
T O P (a lw a y s_ o n )
T O P .A (p o w er b lo c k )
T O P .B (a lw a y s_ o n )
OK
EN
FALSE
EN
OK
EN
OK
OK
EN
OK
EN
OK
EN
OK
T
O
P
T
O
P
.A(p
o
w
er b
lo
ck
)
T
O
P
.A
.B(a
lw
a
y
s_
o
n
)
E
N
E
N
O
K
O
K
O
K
F
A
L
S
E
T
O
P
T
O
P
.A
(p
o
w
erb
lo
ck
)
E
N
F
A
L
S
E
E
N
O
K
100
ICINSIN
Message: Missing isolation cell for power domain %s1: %s2.
From pin/signal: %s3 to pin/signal: %s4
Description
Policy
POWER
Ruleset
ISOLATION_CELLS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
101
T O P (a lw a y s_ o n )
T O P .A (p o w er b lo c k )
OK
EN
T O P .B (a lw a y s_ o n )
OK
EN
OK
EN
OK
OK
EN
FALSE
EN
OK
OK
EN
T
O
P
T
O
P
.A(p
o
w
er b
lo
ck
)
T
O
P
.A
.B(a
lw
a
y
s_
o
n
)
E
N
O
K
O
K
102
E
N
O
K
F
A
L
S
E
ICNONEED
Message: Isolation cell %s is unnecessary: %s
Description
Policy
POWER
Ruleset
ISOLATION_CELLS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
103
TOP
TOP.A (power block)
EN
EN
OK
FALSE
EN
EN
FALSE
OK
EN
EN
FALSE
OK
TOP.F (power
block)
TOP.E
power
TOP.G
(Non(Non
power
block)block)
FALSE
FALSE
EN
EN
FALSE
FALSE
EN
FALSE
104
EN
FALSE
ICNONEEDIN
Message: Isolation cell %s is unnecessary: %s
Description
Policy
POWER
Ruleset
ISOLATION_CELLS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
105
ICLOCALL
Message: Isolation cell must be located outside power
domain %s (in a region always powered-on): %s
Description
Policy
POWER
Ruleset
ISOLATION_CELLS
Language
VHDL/Verilog
Type
Hardware
Severity
Warning
ICNOBUFF
Message: No buffer is allowed between output port %s of
power domain %s and isolation cell %s
Description
Policy
POWER
Ruleset
ISOLATION_CELLS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
106
TOP
TOP.A (power block)
OK
EN
FALSE
EN
EN
OK
FALSE
EN
FALSE
EN
FALSE
EN
EN
TOP
TOP.A(power block)
FALSE
EN
FALSE
EN
OK
T
O
P
T
O
P
.A
(
p
o
w
e
rb
l
o
c
k
)
T
O
P
.A
.B
(
a
l
w
a
y
s
_
o
n
)
F
A
L
S
E
E
N
E
N
O
K
107
ICPINVOLT
Message: Pin of isolation cell %s should be connected to
voltage %f instead of %f: %s
Description
Policy
POWER
Ruleset
ISOLATION_CELLS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
TOP
TOP.IA (0.9V voltage
block)
EN
TOP.IC0:OK
EN
TOP.IC1:FALSE
EN
TOP.IC2 :FALSE
108
ICOFFVAL
Message: Isolation cell power off value mismatch with
control specification of power domain %s1: %s2. Power off
value is %s3 instead of %s4: %s5. Control signal power on
value %s6: %s7
Description
Isolation cell outputs must be set to a fixed logical value when their
corresponding power domain is switched off (considering the
controls defined by set_power_domain_ctrl, for the cells with values
defined by set_power_off_value).
Arguments:
%s1 is the related power domain name (if domain is named)
%s2 is the hierarchical name of isolation cell instance
%s3 is the actual power off value
%s4 is the specified power off value
%s5 is the related output pin, and for each control signal
%s6 and %s7 are the control signal value and name
Policy
POWER
Ruleset
ISOLATION_CELLS
Language
VHDL/Verilog
Type
Hardware
Severity
Error
109
RTL Ruleset
Leda has got rules to check the semantics and usage of $power and $isolate system calls.
The following rules are from the RTL ruleset.
RTLPOW00
Message: Wrong number of arguments passed - at least 6
arguments are expected. Current $power statement will be
ignored by Leda power checks
Description
This rule checks if the $power system call is provided with the
required number of arguments.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
110
RTLPOW01
Message: First argument to $power (power domain name)
must be a quoted string. Current $power statement will be
ignored by Leda power checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLPOW02
Message: Second argument to $power (power_on net) must
be a valid signal name. Current $power statement will be
ignored by Leda power checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
111
RTLPOW03
Message: Third argument to $power (on_sense expression)
must be a valid expression. Current $power statement will
be ignored by Leda power checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLPOW04
Message: Fourth argument to $power (power_on ack net)
must be a valid signal name. Current $power statement will
be ignored by Leda power checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
112
RTLPOW05
Message: Fifth argument to $power statement (ack_sense
expression) must be a valid expression. Current $power
statement will be ignored by Leda power checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLPOW06
Message: Argument must be a valid instance name. Current
$power statement will be ignored by Leda power checks:
Argument %d
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
113
RTLPOW07
Message: $power must occur in an initial block
Description
This rule checks if the $power system task call is present in an initial
block.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
Example
This is an example of an invalid Verilog code:
module top (out1, in1);
input in1;
output out1;
wire pd_sig1, p_ack1;
mod A (.in(in1), .out(out1) );
always begin
$power("pd1", pd_sig1, p_ack1, "1", "top.A"); // FAIL
end
endmodule // top
module mod (in, out);
input in;
output out;
assign out = in;
endmodule // mod
Violation:
9:
//FAIL
^
pow07_fail1.v:9: RTL> [WARNING] RTLPOW07: $power must occur in an
initial block.
114
RTLPOW08
Message: $power statement must not be nested within any
control structure
Description
This rule checks if the $power system task call is nested within any
control structure.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
115
Example
module top (out1, out2, in1, in2, sel);
input in1, in2, sel;
output out1, out2;
wire pd_sig, p_ack;
Violation:
12:
116
RTLPOW08
Message: Power procedure call must not be nested within
any control structure
Description
This rule checks if the power procedure call is nested within any
control structure.
Policy
POWER
Ruleset
RTL
Language
VHDL
Type
Block-level
Severity
Warning
Example
library SNPS_EXT, IEEE;
use
SNPS_EXT.power.all, IEEE.std_logic_1164.all;
entity power_wrapper is
port (power_on
: std_logic_vector;
power_ack
: inout std_logic_vector;
a, b, en
: std_logic);
end;
architecture behav of power_wrapper is
signal c : std_logic;
begin
-IP1 : entity WORK.IP port map(a,b,c);
P1: process
begin -- process P1
if (en='1') then
power("domain_name", power_on, "1", power_ack, "1", "IP1"); --FAIL
wait;
end if;
end process P1;
end;
117
Violation:
23:
RTLPOW09
Message: $power statement must not be preceded by any
timing control
Description
This rule checks if the $power system task call is not preceded by any
timing control statement.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
118
Example
module top (out1, in1);
input in1;
output out1;
wire pd_sig1, p_ack1;
mod A (.in(in1), .out(out1) );
initial begin
#1 $power("pd1", pd_sig1, p_ack1, "1", "top.A"); /* FAIL */
end
endmodule // top
Violation:
8:
119
RTLPOW09
Message: Power procedure call must not be preceded by
any timing control
Description
This rule checks if the power procedure call is not preceded by any
timing control statement.
Policy
POWER
Ruleset
RTL
Language
VHDL
Type
Block-level
Severity
Warning
120
Example
library SNPS_EXT, IEEE;
use
SNPS_EXT.power.all, IEEE.std_logic_1164.all;
entity power_wrapper is
port (power_on
: std_logic_vector;
: std_logic);
end;
: std_logic;
begin
--
-- process P1
wait on power_on;
power("domain_name", power_on, "1", power_ack, "1", "IP1");
--FAIL
Violation:
23:
121
RTLPOW10
Message: Each instance in a design may be named in a
power statement only once. Instance name will be ignored in
enclosing statement: %s
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
Note
RTLPOW11
Message: Power domains cannot be redefined at different
hierarchical levels. Current statement will be ignored in
power domain elaboration
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
122
Note
RTLPOW20
Message: Signals passed as arguments to $power must be
wires declared in the same module
Description
This rule check if the signals passed to the $power system task call
are wires declared in the same module.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
123
Example
module top (out1, in1);
input in1;
output out1;
wire pd_sig1, p_ack1;
my_mod1 A (.out(out1), .in(in1), .pd_sig(pd_sig1), .p_ack(p_ack1) );
endmodule // top
Violation:
16:
16:
124
RTLPOW20
Message: Signals passed as arguments to the power
procedure call must be declared in the same design entity
Description
Policy
POWER
Ruleset
RTL
Language
VHDL
Type
Block-level
Severity
Warning
125
Example
-- p_package_power_sig.vhd
library ieee;
use ieee.std_logic_1164.all;
package p_package_power_sig is
signal power_on : std_logic;
signal power_ack : std_logic;
end package;
-- pow20_fail1.vhd
library SNPS_EXT, IEEE;
use
SNPS_EXT.power.all, IEEE.std_logic_1164.all;
use work.p_package_power_sig.all;
entity power_wrapper is
port ( a, b: std_logic);
end;
architecture behav of power_wrapper is
signal c
: std_logic;
begin
--
P1: process
begin
-- process P1
126
Violation:
22:
22:
RTLPOW21
Message: Register initialized by a constant
Description
Policy
POWER
Ruleset
RTL
Language
Verilog/VHDL
Type
Block-level
Severity
Warning
127
Example
This is an example of an invalid Verilog code:
module top (out1, out2, in1, cp);
input in1, cp;
output out1, out2;
reg
out1, out2 = 1'b0; /* FAIL -- Register initialized by constant
by not assigned a value in an always block*/
always @ (posedge cp) begin
out1 = in1;
end
endmodule // top
Violation:
4:
reg
RTLPOW22
Message: Extra drivers detected for powerup_ack_net
signal: %s
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Netlist
Severity
Warning
128
Example
This is an example of an invalid Verilog code:
module top (out1, in1);
input in1;
output out1;
wire pd_net, pd_ack;
endmodule // mod
Violation:
4:
129
RTLPOW23
Message: Non edge-sensitive logic detected on boundary of
power-down region.
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Netlist
Severity
Warning
130
Example
This is an example of an invalid Verilog code:
module top (out1, in1);
input in1;
output out1;
wire pd_net, pd_ack;
endmodule // top
endmodule // mod
Violation:
11:
131
RTLPOW24
Message: Nested non-contiguous power regions detected
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Netlist
Severity
Warning
132
Example
This is an example of an invalid Verilog code:
module top (out1, in1);
input in1;
output out1;
endmodule // top
endmodule // mod
endmodule // mod
Tcl commands:
set_power_domain -name POW1 { TOP TOP.A.A} /* FAIL */
set_power_domain -name POW2 { TOP.A }
133
Violation:
13:
RTLISO00
Message: Wrong number of arguments passed - exactly 4
arguments are expected. Current $isolate statement will be
ignored by Leda power checks
Description
This rule checks if the $isolate system call has got 4 arguments.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
134
RTLISO01
Message: First argument to $isolate (output net) must be a
valid signal name. Current $isolate statement will be ignored
by Leda power checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLISO02
Message: Second argument to $isolate (enable net) must be
a valid signal name. Current $isolate statement will be
ignored by Leda power checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
135
RTLISO03
Message: Third argument to $isolate (input net) must be a
valid signal name. Current $isolate statement will be ignored
by Leda power checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLISO04
Message: Output and input signals must be of the same
type. Current $power statement will be ignored by Leda
power checks
Description
This rule checks if the output and input signals are of the same data
type.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
136
RTLISO05
Message: Fourth argument to $isolate statement must have
the same type as the output signal (first argument). Current
$isolate statement will be ignored by Leda power checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLISO06
Message: $isolate must be in an always block
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
137
Example
module top (out1, in1, en1);
input in1, en1;
output out1;
initial
begin
$isolate (out1, in1, en1, 1'b1); /* FAIL */
end
endmodule // top
Violation:
7:
RTLISO07
Message: Enclosing always of $isolate must be
combinational
Description
This rule checks if the always block enclosing the $isolate construct
is a combinational always block.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
138
Example
module top (out1, in1, en1);
input in1, en1;
output out1;
always @ (posedge en1)
begin
$isolate (out1, in1, en1, 1'b1); /* FAIL */
end
endmodule // top
Violation:
7:
RTLISO08
Message: Each signal in $isolate must appear in sensitivity
list of enclosing always block
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
139
Example
module top (out1, in1, en1);
input in1, en1;
output out1;
always @ (en1)
begin
$isolate (out1, in1, en1, 1'b1); /* FAIL */
end
endmodule // top
Violation:
7:
RTLRET00
Message: Wrong number of arguments passed - at least 5
arguments are expected. Current $retain statement will be
ignored by Leda power checks
Description
This rule checks if the $retain system task has atleast 5 arguments.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
140
RTLRET01
Message: First argument to $retain (save_signal net) must
be a valid 1 bit signal name. Current $retain statement will
be ignored by Leda power checks
Description
This rule checks if the first argument of $retain system task is a valid
1-bit signal name.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLRET02
Message: Second argument to $retain (save_sense
expression) must be a valid expression (0 or 1). Current
$retain statement will be ignored by Leda power checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
141
RTLRET03
Message: Third argument to $retain (restore signal) must be
a valid, 1-bit signal name. Current $retain statement will be
ignored by Leda power checks
Description
This rule checks if the third argument of $retain system task is a valid
1-bit signal name.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLRET04
Message: Fourth argument to $retain statement
(restore_sense expression) must be a valid expression.
Current $retain system task will be ignored by Leda power
checks
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
142
RTLRET05
Message: Fifth argument to $retain statement (type) must be
a valid type. Current $retain statement will be ignored by
Leda power checks
Description
This rule checks if the fifth argument of $retain system task is a valid
type.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLRET06
Message: Argument must be a valid instance name. Current
$retain statement will be ignored by Leda power checks:
Argument %d
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
143
RTLRET07
Message: $retain must occur in a TOP level initial block
Description
This rule checks if the $retain system task is present in the top level
initial block.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLRET08
Message: $retain statement must not be nested within any
control structure
Description
This rule checks if the $retain system task is nested within any
control structure.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
144
RTLRET09
Message: $retain statement must not be preceded by any
timing control
Description
This rule checks if the $retain system task is preceded by any timing
control statement.
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
RTLRET10
Message: Extra drivers detected for powerup_ack_net signal
Description
Policy
POWER
Ruleset
RTL
Language
Verilog
Type
Block-level
Severity
Warning
145
146